REALTEK RTL8201L Datasheet
RTL8201(L)
2002-01-18 Rev.1.04
1
REALTEK SINGLE CHIP
SINGLE PORT 10/100MBPS
FAST ETHERNET PHYCEIVER
RTL8201(L)
1. Features........................................................................ 2
2. General Description .................................................... 2
3. Block Diagram............................................................. 3
4. Pin Assignments .......................................................... 4
5. Pin Description ............................................................ 5
5.1 100 Mbps MII & PCS Interface ............................. 5
5.2 Serial Network Interface (SNI) .............................. 5
5.3 Clock Interface....................................................... 5
5.4 100Mbps Network Interface................................... 6
5.5 Device Configuration Interface.............................. 6
5.6 LED Interface/PHY Address Config...................... 6
5.7 Reset and Test pins................................................. 6
5.8 Power and Ground pins.......................................... 6
6. Register Descriptions .................................................. 7
6.1 Register 0 Basic Mode Control .............................. 7
6.2 Register 1 Basic Mode Status................................. 9
6.3. Register 2 PHY Identifier 1................................. 10
6.4. Register 3 PHY Identifier 2................................. 10
6.5. Register 4 Auto-negotiation Advertisement................ 11
6.6 Register 5 Auto-Negotiation Link Partner Ability .................. 12
6.7 Register 6 Auto-negotiation Expansion (ANER). 14
6.8 Register 16 Nway Setup (NSR)....................................... 14
6 . 9 Register 17 Loopback, Bypass, Receiver Error Mask (LBREMR).... 15
6.10 Register 18 RX_ER Counter (REC)................... 15
6.11 Register 19 10Mbps Network Interface Configuration.......... 15
6.12 Register 20 PHY 1_1.......................................... 15
6.13 Register 21 PHY 1_2.......................................... 16
6.13 Register 22 PHY 2 ............................................. 16
6.14 Register 23 Twister_1 ........................................ 16
6.15 Register 24 Twister_2 ........................................ 16
7. Functional Description ............................................. 17
7.1 MII and Management Interface............................ 17
7.2 Auto-negotiation and Parallel Detection.............. 18
7.3 Flow control support ............................................ 18
7.4 Hardware Configuration and Auto-negotiation.............. 19
7.5 LED and PHY Address Configuration................. 20
7.6 Serial Network Interface ...................................... 20
7 .7 Power Down, Link Down, Power Saving, and Isolation Modes 2 1
7.8 Media Interface .................................................... 21
7.8.1 100Base Tx/Rx ............................................. 21
7.8.2 10Base Tx/Rx ............................................... 22
7.9 Repeater Mode Operation .................................... 22
7.10 Reset, Power, and Transmit Bias........................ 22
8. Electrical Characteristics ......................................... 23
8.1 D.C. Characteristics ............................................. 23
8.1.1. Absolute Maximum Ratings........................ 23
8.1.2. Operating Conditions................................... 23
8.1.3. Power Dissipation........................................ 23
8.1.4 Supply Voltage: Vcc ..................................... 23
8.2 A.C. Characteristics ............................................. 24
8.2.1 Transmission Without Collision ................... 24
8.2.2 Reception Without Error............................... 24
9. Mechanical Dimensions............................................ 25
RTL8201(L)
2002-01-18 Rev.1.04
2
1. Features
The Realtek RTL8201(L) is a Fast Ethernet Phyceiver with MII interface to the MAC chip. It provides the following
features:
Supports MII interface
Supports 10/100Mbps operation
Supports half/full duplex operation
IEEE 802.3/802.3u compliant
Supports IEEE 802.3u clause 28 auto negotiation
Supports power down mode
Supports operation under Link Down Power
Saving mode
Supports repeater mode
Speed/duplex/auto negotiation adjustable
3.3V operation with 5V signal tolerance
Low operation power consumption
Adaptive Equalization
25MHz crystal/oscillator as clock source
Multiple network status LED support
Supports 7-wire SNI (Serial Network Interface)
interface
Flow control ability support to co-work with
MAC (by MDC/MDIO)
48-pin LQFP package
2. General Description
The RTL8201(L) is a single-port Phyceiver with an MII (Media Independent Interface). It implements all 10/100M Ethernet
Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair
Physical Medium Dependent Sublayer (TP-PMD), 10Base-Tx Encoder/Decoder and Twisted Pair Media Access Unit
(TPMAU). It is fabricated with an advanced CMOS process to meet low voltage and low power requirements.
The RTL8201(L) can be used as a Network Interface Adapter, MAU, CNR, ACR, Ethernet Hub, Ethernet Switch.
Additionally, it can be used in any embedded system with an Ethernet MAC that needs a twisted pair physical connection.
RTL8201(L)
2002-01-18 Rev.1.04
3
3. Block Diagram
RXIN+
RXIN-
TXO+
TXO -
RXC 25M
25M
TXC 25M
TXD
RXD
TD+
Variable Current
3 Level
Driver
Master
PPL
Adaptive
Equalizer
Peak
Detect
3 Level
Comparator
Control
Voltage
MLT-3
to NRZI
Serial to
Parrallel
ck
data
Slave
PLL
Parrallel
to Serial
Baseline
wander
Correction
5B 4B
Decoder
Data
Alignment
Descrambler
4B 5B
Encoder
Scrambler
10/100
half/full
Switch
Logic
10/100M Auto-negotiation
Control Logic
Manchester coded
waveform
10M Output waveform
shaping
Data Recovery Receive low pass filter
RXD
RXC 25M
TXD
TXC 25M
TXD10
TXC10
RXD10
RXC10
Link pulse
10M
100M
MII
Interface
SNI
Interface
RTL8201(L)
2002-01-18 Rev.1.04
4
4. Pin Assignments
RTL8201
7. TXC
2. TXEN
3. TXD3
4. TXD2
5. TXD1
6. TXD0
16. RXC
1. COL
23. CRS
22. RXDV
18. RXD3
19. RXD2
20. RXD1
21. RXD0
24. RXER
25. MDC
26. MDIO
46. X1
47. X2
33. TPTX-
34. TPTX+
28. RTSET
31. TPRX+
30. TPRX-
43. ISOLATE
40. RPTR/
RTT2
39. Speed
38. Duplex
37. ANE
41. LDPS
44. MII/
SNIB
9. LED0/
PAD0
10. LED1/
PAD1
12. LED2/
PAD2
13. LED3/
PAD3
15. LED4/
PAD4
27. RTT3/
VCTRL
42. RESETB
48. AVDD2
32. AVDD0
36. AVDD1
29. AGND
35. AGND
45. AGND
8. DVDD0
14. DVDD1
17. DGND
11. DGND
RTL8201(L)
2002-01-18 Rev.1.04
5
5. Pin Description
5.1 100 Mbps MII & PCS Interface
Symbol Type Pin(s) No. Description
TXC O 7 Transmit C l o ck: This pin provides a continuous clock as a timing reference
for TXD[3:0] and TXEN.
TXEN I 2 Transmit Enable: The input signal indicates the presence of a valid nibble
data on TXD[3:0].
TXD[3:0] I 3, 4, 5, 6 Transmi t D a ta: MAC will source TXD[0..3] synchronous with TXC when
TXEN is asserted.
RXC O 16 Receive Clock: This pin provides a continuous clock reference for RXDV
and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode and 2.5Mhz in
the 10Mbps mode.
COL O 1 Collision Detected: COL is asserted high when a collision is detected on the media.
CRS I/O 23 Carrier Sense: This pin’s signal is asserted high if the media is not in IDEL state.
RXDV O 22 Receive Data Valid: This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines; the signal is deasserted at the end of the
packet. The signal is valid on the rising of the RXC.
RXD[3:0] O 18, 19, 20, 21 Receive Data: These are the four parallel receive data lines aligned on the
nibble boundaries driven synchronously to the RXC for reception by the
external physical unit (PHY).
RXER O 24 Receive error: if any 5B decode error occurred such as invalid J/K, T/R,
invalid symbol, this pin will go high
MDC I 25 Management Data Clock: This pin provides a clock synchronous to MDIO,
which may be asynchronous to the transmit TXC and receive RXC clocks.
MDIO I/O 26 Management Data Input/Output: This pin provides the bi-directional
signal used to transfer management information.
5.2 Serial Network Interface (SNI)
10Mbps only
Symbol Type Pin(s) No. Description
COL O 1
Collision Detect
RXD0 O 21
Received Serial Data
CRS O 23
Carrier Sense
RXC O 16 Receive Clock: Resolved from received data
TXD0 I 6
Transmit Serial Data
TXC O 7 Transmit Clock: Generate by PHY
TXEN I 2 Transmit Enable: For MAC to indicate transmit operation
5.3 Clock Interface
Symbol Type Pin(s) No. Description
X2 O 47 25Mhz Crystal Output: This pin provides the 25MHz crystal output.
X1 I 46 25Mhz Crystal Input: This pin provides the 25MHz crystal input.
RTL8201(L)
2002-01-18 Rev.1.04
6
5.4 100Mbps Network Interface
Symbol Type Pin(s) No. Description
TPTX+
TPTX-
O
O
34
33
Transmit Output
RTSET I 28 Transmit bias resistor connection: This pin should be pulled to GND by a
2.0K resistor.
TPRX+
TPRX-
I
I
31
30
Receive input
5.5 Device Configuration Interface
Symbol Type Pin(s) No. Description
ISOLATE I 43 Set high to isolate the RTL8201(L) from the MAC. This will also isolate the
MDC/MDIO management interface. In this mode, the power consumption is
minimum.
RPTR/RTT2 I 40 Set high to put the RTL8201(L) into repeater mode. In test mode, this pin is
re-defined as RTT2.
SPEED I 39 Set high to put the RTL8201(L) into 100Mbps operation
DUPLEX I 38 Set high to enable full duplex
ANE I 37 Set high to enable Auto-negotiation mode, set low to force mode
LDPS I 41 Set high to put the RTL8201(L) into LDPS mode,
MII/SNIB/T
XD5(test)
I 44 Pull high to set the RTL8201(L) into MII mode operation
5.6 LED Interface/PHY Address Config
Symbol Type Pin(s) No. Description
LED0/PAD0 O 9
Link LED
LED1/PAD1 O 10
Full Duplex LED
LED2/PAD2 O 12
Link 10/ACT LED
LED3/PAD3 O 13
Link 100/ACT LED
LED4/PAD4 O 15
Collision LED
5.7 Reset and Test pins
Symbol Type Pin(s) No. Description
RTT3/CTRL O 27 Currently a test pin, this pin may be utilized for future functions.
RESETB I 42
RESETB:
Setting low to reset the chip.
5.8 Power and Ground pins
Symbol Type Pin(s) No. Description
AVDD0 P 32
Analog power:
3.3V power supply for analog circuit; should be well
decoupled
AVDD1 P 36
Analog power:
3.3V power supply for analog circuit; should be well
decoupled
AVDD2 P 48 3.3V power supply for PLL, should be well decoupled and use a bead with
100ohm @ 100MHz to connect to analog power
AGND P 29,35,45
Analog Ground:
Should be connected to a larger GND plane
DVDD0 P 8
Digital Power:
3.3V power supply for digital circuit.
DVDD1 P 14
Digital Power:
3.3V power supply for digital circuit.
DGND P 11,17
Digital Ground:
Should be connected to a larger GND plane
RTL8201(L)
2002-01-18 Rev.1.04
7
6. Register Descriptions
This section will describe definitions and usage for each of the registers available in the RTL8201. The first six registers of the
MII are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp. for internal use and are
reserved for specific uses.
Register Description Default (h)
0 Basic Mode Control Register 3100
1 Basic Mode Status Register 7849
2 PHY Identifier 1 Register 0000
3 PHY Identifier 2 Register 8201
4 Auto-negotiation Advertisement Register 1E1
5 Auto-negotiation Link Partner Ability Register 80
6 Auto-negotiation Expansion Register 0
6.1 Register 0 Basic Mode Control
Address Name Description/Usage Default/Attribute
0:<15> Reset Reset: This bit sets the status and control registers of the PHY in a
default state. In order to reset the RTL8201L by software control, a ‘1’
must be written to bit 15 using an MII write operation. The bit clears
itself after the reset process is complete, and does not need to be cleared
using a second MII write. Writes to other Control register bits will have
no effect until the reset process is completed, which requires
approximately 1us. Writing a ‘0’ to this bit has no effect. Because this
bit is self clearing after a few cycles from a write operation, it will
return a ‘0’ when read.
1: Software reset
0: Normal operation
0, RW
0:<14> Loopback Loopback: This bit enables loopback of transmit data nibbles
TXD<3:0> to the receive data path. The RTL8201L may be placed into
loopback mode by writing a ‘1’ to bit 14. Loopback mode may be
cleared either by writing a ‘0’ to bit 14 or by resetting the chip. When
this bit is read, it will return a ‘1’ when the chip is in
software-controlled loopback mode, otherwise it will return a ‘0’.
1: Enable loopback
0: Normal operation
0, RW
0:<13> Spd_Set Speed Set: This bit can set the network speed. If Auto-negotiation is
enabled, this bit has no effect on speed selection. However, if
Auto-negotiation is disabled by software control, the operating speed of
the RTL8201L can be forced by writing the appropriate value to bit 13.
Writing a ‘1’ to this bit forces 100Base-X operation, while writing a ‘0’
forces 10Base-T operation. When this bit is read, it returns the value of
the software controlled forced speed selection only.
1: 100Mbps
0: 10Mbps
When 100Base-FX mode is enabled, this bit=1, and this bit is read only.
1, RW
RTL8201(L)
2002-01-18 Rev.1.04
8
0:<12> Auto
Negotiation
Enable
Auto Negotiation Enable: Auto-negotiation can be disabled by either
hardware or software control. This bit can enable/disable the Nway
auto-negotiation function. If the ANEN input pin is driven to a logic ‘0’,
Auto-negotiation is disabled by software control. When
Auto-negotiation is disabled in this manner, writing a ‘1’ to the same bit
of the control register or resetting the chip will re-enable
Auto-negotiation. Writing to this bit has no effect when
Auto-negotiation has been disabled by hardware control. When read,
this bit will return the value most recently written to this location, or ‘1’
if it has not been written since the last chip reset.
1: Enable auto-negotiation; bits 0:<13> and 0:<8> will be ignored
0: Disable auto-negotiation; bits 0:<13> and 0:<8> will determine the
link speed and the data transfer mode, respectively
When 100Base-FX mode is enabled, this bit=0, and this bit is read only.
1, RW
0:<11> Power Down Power Down: The RTL8201L supports a low power mode which is
intended to decrease power consumption. This bit turns down the power
of the PHY chip including internal crystal oscillator circuit. The MDC,
MDIO is still alive for accessing the MAC.
Writing a ‘1’ will enable power down mode, and writing a ‘0’ will
return the RTL8201L to normal operation. When read, this register will
return a ‘1’ when in power down mode, and a ‘0’ during normal
operation.
1: Power down
0: Normal operation
0, RW
0:<10> Reserved Reserved: Ignore the output of the RTL8201L when these bits are read.
0:<9> Restart Auto
Negotiation
Restart Auto Negotiation: Bit 9 is a self-clearing bit that allows the
Nway auto-negotiation process to be restarted, regardless of the current
status of the Auto-negotiation state machine. In order for this bit to have
an effect, Auto-negotiation must be enabled. Writing a ‘1’ to this bit
restarts Auto-negotiation while writing a ‘0’ to this bit has no effect.
When this bit is read, it will always return a ‘0’.
1: Re-start auto-negotiation
0: Normal operation
0, RW
0:<8> Duplex Mode Duplex Mode: By default, the RTL8201L powers up in half duplex
mode. The chip can be forced into full duplex mode by writing a ‘1’ to
bit 8 while Auto-negotiation is disabled. Half duplex mode can be
resumed either by writing a ‘0’ to bit 8 or by resetting the chip. When
Nway is enabled, this bit reflects the results of the Auto-negotiation, and
is in a read only mode. When Nway is disabled, this bit can be set
through the SMI, and is in a read/write mode. When 100FX is enabled,
this bit can be set through the SMI or FX_DUPLEX pin and is in a
read/write mode. This bit sets the duplex mode if auto negotiation is
disabled (bit 0:<12>=0).
1: Full duplex
0: Normal operation
After auto negotiation completes, this bit will reflect the duplex status.
1, RW
0:<7:0> Reserved Reserved Bits: All reserved MII register bits must be written as ‘0’ at
all times. Ignore the RTL8201L output when these bits are read.
Loading...