Realtek RTL8169 User Manual

REALTEK GIGABIT

ETHERNET MEDIA ACCESS

CONTROLLER

WITH POWER MANAGEMENT

RTL8169

1. Features........................................................................ 2

2. General Description .................................................... 3

3. Block Diagram............................................................. 4

4. Pin Assignments .......................................................... 5

5. Pin Description ............................................................ 6

5.1 Power Management/Isolation Interface ................. 6

5.2 PCI Interface .......................................................... 7

5.3 FLASH/BootPROM/EEPROM/MII Interface ....... 9

5.4 LED Interface....................................................... 10

5.5 GMII, TBI, PHY CP ............................................ 10

5.6 Clock and NC Pins............................................... 12

5.7 Power Pins ........................................................... 12

6. Register Descriptions ................................................ 13

6.1 DTCCR: Dump Tally Counter Command............ 15

6.2 FLASH: Flash Memory Read/Write .................... 16

6.3 ERSR: Early Rx Status......................................... 16

6.4 Command............................................................. 17

6.5 TPPoll: Transmit Priority Polling......................... 17

6.6 Interrupt Mask...................................................... 18

6.7 Interrupt Status..................................................... 19

6.8 Transmit Configuration........................................ 20

6.9 Receive Configuration ......................................... 21

6.10 9346CR: 93C46 (93C56) Command.................. 23

6.11 CONFIG 0.......................................................... 23

6.12 CONFIG 1.......................................................... 24

6.13 CONFIG 2.......................................................... 25

6.14 CONFIG 3.......................................................... 25

6.15 CONFIG 4.......................................................... 26

6.16 CONFIG 5.......................................................... 27

6.17 Multiple Interrupt Select .................................... 28

6.18 PHYAR: PHY Access ........................................ 28

6.19 TBICSR: Ten Bit Interface Control and Status .. 28

6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement .. 29

6 .2 1 TBI_LPAR: TBI Auto-Negotiation Link Partner Ability ....... 29

6.22 PHYStatus: PHY(GMII or TBI) Status.............. 30

6.23 RMS: Receive (Rx) Packet Maximum Size....... 30

6.24 C+CR: C+ Command......................................... 31

6.25 RDSAR: Receive Descriptor Start Address....... 31

6.26 ETThR: Early Transmit Threshold..................... 31

6.27 Function Event ................................................... 32

6.28 Function Event Mask ......................................... 32

6.29 Function Preset State.......................................... 33

6.30 Function Force Event ......................................... 33

7. EEPROM (93C46 or 93C56) Contents ................... 34

7.1 EEPROM Registers.............................................. 35

7.2 EEPROM Power Management Registers............. 35

8. PCI Configuration Space Registers......................... 36

8.1 PCI Bus Interface ................................................. 36

8.1.1 Byte Ordering ............................................... 36

8.1.2 Interrupt Control........................................... 36

8.1.3 Latency Timer............................................... 36

8.1.4 64-Bit Data Operation .................................. 37

8.1.5 64-Bit Addressing......................................... 37

8.2 Bus Operation ...................................................... 37

RTL8169

8.2.1 Target Read................................................... 37

8.2.2 Target Write.................................................. 38

8.2.3 Master Read.................................................. 38

8.2.4 Master Write................................................. 39

8.2.5 Configuration Access ................................... 40

8.3 Packet Buffering .................................................. 40

8.3.1 Transmit Buffer Manager............................. 40

8.3.2 Receive Buffer Manager............................... 40

8.3.3 Packet Recognition....................................... 40

8.4 PCI Configuration Space Table............................ 41

8.5 PCI Configuration Space Functions..................... 42

8.6 Default Value After Power-on (RSTB Asserted). 46

8.7 Power Management functions.............................. 47

8.8 Vital Product Data (VPD).................................... 49

9. Functional Description ............................................. 50

9.1 Transmit & Receive Operations........................... 50

9.1.1 Transmit........................................................ 50

9.1.2 Receive ......................................................... 55

9.2 Loopback Operation............................................. 58

9.3 Collision............................................................... 58

9.4 Flow Control ........................................................ 58

9.4.1. Control Frame Transmission ....................... 58

9.4.2. Control Frame Reception ............................ 58

9.5 Memory Functions ............................................... 59

9.5.1 Memory Read Line (MRL) .......................... 59

9.5.2 Memory Read Multiple (MRM)................... 59

9.5.3 Memory Write and Invalidate (MWI) .......... 60

9.5.4 Dual Address Cycle (DAC).......................... 60

9.6 LED Functions..................................................... 61

9.6.1 Link Monitor ................................................ 61

9.6.2 Rx LED ........................................................ 61

9.6.3 Tx LED......................................................... 62

9.6.4 Tx/Rx LED................................................... 62

9.6.5 LINK/ACT LED........................................... 63

9.7 Physical Layer Interfaces ..................................... 64

9.7.1 Media Independent Interface (MII).............. 64

9.7.2 Gigabit Media Independent Interface (GMII) ...... 64

9.7.3 Ten Bit Interface (TBI) ................................. 64

9.7.4 MII/GMII Management Interface................. 64

10. Application Diagrams............................................. 65

10.1 10/100/1000Base-T Application........................ 65

10.2 1000Base-X Application.................................... 65

11. Electrical Characteristics ....................................... 66

11.1 Temperature Limit Ratings................................. 66

11.2 DC Characteristics ............................................. 66

11.3 AC Characteristics ............................................. 67

11.3.1 FLASH/BOOT ROM Timing..................... 67

11.3.2 Serial EEPROM Interface Timing .............. 69

11.3.3 PCI Bus Operation Timing ......................... 70

11.3.4 MII Timing ................................................. 87

11.3.5 GMII Timing .............................................. 89

11.3.6 TBI Timing ................................................. 90

12. Mechanical Dimensions.......................................... 91

2002/03/27 Rev.1.21

1. Features

 208 pin QFP  Supports descriptor-based buffer management  Supports Microsoft* NDIS5 Checksum Offloads (IP,

TCP, UDP), and Largesend Offload

 Supports IEEE 802.1Q VLAN tagging  Supports Transmit (Tx) Priority Queue for QoS, CoS

applications

 Supports major Tally Counters  10Mbps, 100Mbps, and 1000Mbps operation at

MII/GMII, and 1000Mbps at TBI interfaces

 Supports 10Mbps, 100Mbps, and 1000Mbps N-way

Auto-negotiation operation

 PCI local bus single-chip Fast Ethernet controller

 Compliant to PCI Revision 2.2  Supports both Little-Endian and Big-Endian  Supports 16.75MHz-66MHz PCI clock  Supports both 32-bit and 64-bit PCI bus  Supports PCI target fast back-to-back transaction  Supports Memory Read Line, Memory Read

Multiple, Memory Write and Invalidate, and Dual Address Cycle

 Provides PCI bus master data transfers and PCI

memory space or I/O space mapped data transfers of the RTL8169 operational registers

 Supports PCI VPD (Vital Product Data)  Supports ACPI, PCI power management  Supports optional PCI multi-function with

additional slave mode only functions

 Supports CardBus. The CIS can be stored in 93C56 or

expansion ROM

 Supports Boot ROM interface. Up to 128K bytes Boot

ROM interface for both EPROM and Flash memory can be supported

 Supports 125MHz OSC as the internal clock source or

125MHz clock provided from external PHYceiver

 Compliant to PC97, PC98, PC99 and PC2001 standards

RTL8169

 Supports Wake-On-LAN function and remote wake-up

(Magic Packet*, LinkChg and Microsoft frame)

 Supports 4 Wake-On-LAN (WOL) signals (active high,

active low, positive pulse, and negative pulse)

 Supports auxiliary power-on internal reset, to be ready

for remote wake-up when main power still remains off

 Supports auxiliary power auto-detect, and sets the

related capability of power management registers in PCI configuration space

 Advanced power saving mode when LAN function or

wakeup function is not used

 3.3V and 1.8V power supplies needed  5V tolerant I/Os  Includes a programmable, PCI burst size and early

Tx/Rx threshold

 Supports a 32-bit general-purpose timer with the

external PCI clock as clock source, to generate timer-interrupt

 Contains two large independent transmit (8KB) and

receive (48KB) FIFO devices

 Uses 93C46 (64*16-bit EEPROM) or 93C56

(128*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data. The 93C56 can also be used to store the CIS data structure for CardBus applications

 Supports LED pins for various network activity

indications

 Supports both digital and external analog loopback  Half/Full duplex capability (only Full duplex operation

at 1000Mbps)

 Supports Full Duplex Flow Control (IEEE 802.3x) * Third-party brands and names are the property of their

respective owners.

These specifications are subject to change without notice.

wake-up

2002/03/27 Rev.1.21

RTL8169

2. General Description

The Realtek RTL8169 is a highly integrated, high performance PCI Gigabit Ethernet Media Access Controller for use in network adapters for servers and personal computers. The RTL8169 fully implements the 33/66MHz, 32/64-bit PCI v2.2 bus interface for host communications with power management and is compliant with the IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE 802.3z specification for 1000Mbps Ethernet. The RTL8169 supports the auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space.

It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System directed Power Management (OSPM) to achieve the most efficient power management system possible.

In addition to the ACPI feature, the RTL8169 also supports remote wake-up (including AMD Magic Packet, LinkChg, and Microsoft through the application of auxiliary power. When the auxiliary power is applied and the main power remains off, the RTL8169 is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides four different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8169 LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality.

The PCI specification is inherently little-endian. The RTL8169 contains the ability to do little-endian to big-endian swaps. It is also possible that the RTL8169 can be used as a basis for a RISC CPU platform which expect the data to be in a big-endian format. This feature allows for maximum flexibility.

PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the RTL8169 LAN card). The information may consist of part number, serial number, and other detailed information.

The RTL8169 is fully compliant to Microsoft supports IEEE802.1Q Virtual bridged Local Area Network (VLAN). All the above RTL8169 features contribute to lowering CPU utilization, which is a benefit in operation as a server network card. Also, the RTL8169 boosts its PCI performance by supporting PCI Memory Read Line & Memory Read Multiple when transmitting, and Memory Write and Invalidate when receiving. To be better qualified as a server card, the RTL8169 also supports the PCI Dual Address Cycle (DAC) command, when the assigned buffers reside at a physical memory addresses higher than 4 Gigabytes. For QoS, CoS requirements, the RTL8169 supports hardware high priority queues to reduce software implementation effort and significantly improve performance.

The RTL8169 keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a network from 10/100Mbps to 1000Mbps. It also supports full-duplex operation, making possible 2000Mbps of bandwidth at no additional cost. For special applications, the RTL8169 also supports a TBI interface, which can be used to provide a connection to a Fiber channel, using a Fiber transceiver.

wake-up frame) in both ACPI and APM environments. The RTL8169 is capable of performing an internal reset

NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and

2002/03/27 Rev.1.21

3. Block Diagram

RTL8169

MAC

Boot ROM

Interface

Power Control Logic

Interrupt

Control

Logic

EEPROM Interface

Early Interrupt

Threshold

Early Interrupt

Control Logic

LED Driver

Packet Type

Packet Length

Discriminator

PCI Interface

PCI Interface + Register

FIFO

Control

Logic

Transmit/

Receive

Logic

Interface

MII/GMII/TBI

2002/03/27 Rev.1.21

4. Pin Assignments

RTL8169

131 VDD33 132 RSTPHYB 133 TBILBK 134 GND 135 TXD7 136 TXD6 137 TXD5 138 TXD4 139 TXD3 140 TXD2 141 TXD1 142 TXD0 143 TXEN 144 VDD33 145 GTXCLK 146 TX8 147 TXCLK 148 CRS 149 GND 150 GND 151 COL 152 RXER 153 NC 154 RXCLK1 155 NC 156 RXCLK

157 RXDV 158 RXD0 159 RXD1 160 RXD2 161 RXD3 162 RXD4 163 RXD5 164 RXD6 165 RXD7 166 VDD18 167 VDD33 168 CLOCK125 169 MDC 170 MDIO 171 GND 172 ISOLATEB 173 M66EN 174 INTAB 175 RSTB 176 CLK 177 GNTB 178 REQB 179 VDD33 180 AD31 181 AD30 182 AD29 183 AD28 184 GND 185 AD27 186 AD26 187 AD25 188 AD24 189 VDD33 190 CBE3B 191 IDSEL 192 AD23 193 AD22 194 AD21 195 GND 196 AD20 197 AD19 198 AD18 199 AD17 200 VDD33 201 AD16 202 CBE2B 203 FRAMEB 204 IRDYB 205 TRDYB 206 GND 207 DEVSELB 208 STOPB

RTL8169

130 OEB 129 WEB 128 ROMCSB 127 MD0 126 MD1 125 MD2 124 MD3 123 MD4 122 MD5 121 MD6 120 VDD18 119 MD7 118 LED0 117 GND 116 LED1 115 LED2 114 LED3 113 VDD33 112 MA16 111 MA15 110 MA14 109 MA13 108 NC 107 MA12 106 NC 105 MA11

104 MA10 103 NC 102 MA9 101 MA8 100 MA7 99 MA6 98 GND 97 MA5 96 MA4 95 MA3 94 GND 93 EECS 92 MA2 91 MA1 90 MA0 89 VDD33 88 LWAKE 87 PMEB 86 CLKRUNB 85 AD32 84 AD33 83 AD34 82 GND 81 AD35 80 AD36 79 AD37 78 AD38 77 VDD33 76 AD39 75 AD40 74 AD41 73 AD42 72 GND 71 GND 70 AD43 69 AD44 68 VDD18 67 AD45 66 AD46 65 VDD33 64 AD47 63 AD48 62 AD49 61 AD50 60 GND 59 AD51 58 AD52 57 AD53 56 AD54 55 VDD33 54 AD55 53 AD56

1 PERRB 2NC 3 SERRB 4NC 5 PAR 6NC 7 CBE1B 8 VDD33 9 AD15 10 AD14 11 AD13 12 AD12 13 GND 14 AD11 15 AD10 16 AD9 17 AD8 18 VDD33 19 CBE0B 20 AD7 21 AD6 22 AD5 23 GND 24 AD4 25 AD3 26 AD2

52 AD57 51 NC 50 AD58 49 NC 48 GND 47 NC 46 AD59 45 NC 44 AD60 43 AD61 42 AD62 41 VDD33 40 AD63 39 PAR64 38 CBE4B 37 CBE5B 36 GND 35 CBE6B 34 CBE7B 33 GND 32 REQ64B 31 ACK64B 30 VDD33 29 AD0 28 AD1 27 VDD18

2002/03/27 Rev.1.21

RTL8169

5. Pin Description

In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.

5.1 Power Management/Isolation Interface

Symbol Type Pin No Description

PMEB (PME#)

ISOLATEB (ISOLATE#)

LWAKE/ CSTSCHG

O/D 87

I 172

O 88

Power Management Event: Open drain, active low. Used by the RTL8169 to request a change in its current power management state and/or to indicate that a power management event has occurred.

LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This signal is used to inform the motherboard to execute the wake-up process. The motherboard must support Wake-On-LAN (WOL). There are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that may be asserted from the LWAKE pin. Please refer to LWACT bit in CONFIG1 register and LWPTN bit in CONFIG4 register for the setting of this output signal. The default output is an active high signal. Once a PME event is received, the LWAKE and PMEB assert at the same time when the LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the LWAKE asserts only when the PMEB asserts and the ISOLATEB is low.

CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal is used in CardBus applications only and is used to inform the motherboard to execute the wake-up process whenever a PME event occurs. This is always an active high signal, and the setting of LWACT (bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4) means nothing in this case.

This pin is a 3.3V signaling output pin.

Isolate Pin: Active low. Used to isolate the RTL8169 from the PCI bus. The RTL8169 does not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and PCICLK) as long as the Isolate pin is asserted.

2002/03/27 Rev.1.21

5.2 PCI Interface

Symbol Type Pin No Description

AD63-0 T/S 40, 42-44, 46, 50,

52-54, 56-59, 61-64, 66-67, 69-70, 73-76,

78-81, 83-85, 180-183,

185-188, 192-194,

196-199, 201, 9-12,

14-17, 20-22, 24-26,

28-29

C/BE7-0B T/S 34-35, 37-38, 190, 202,

7, 19

CLK I 176

CLKRUNB I/O 86

DEVSELB S/T/S 207

FRAMEB S/T/S 203

cont...

AD31-0: Low 32-bit PCI address and data multiplexed pins. The address phase is the first clock cycle in which FRAMEB is asserted. During the address phase, AD31-0 contains a physical address (32 bits). For I/O, this is a byte address, and for configuration and memory, it is a double-word address. The RTL8169 supports both big-endian and little-endian byte ordering. Write data is stable and valid when IRDYB is asserted. Read data is stable and valid when TRDYB is asserted. Data I is transferred during those clocks where both IRDYB and TRDYB are asserted.

AD63-32: High 32-bit PCI address and data multiplexed pins.

During an address phase (when using the DAC command or when REQ64B is asserted), the upper 32-bits of a 64-bit address are transferred; otherwise, these bits are reserved, and are stable and indeterminate. During a data phase, an additional 32-bits of data are transferred when a 64-bit transaction has been negotiated by the assertion of REQ64B and ACK64B.

PCI bus command and byte enables multiplexed pins. During the address phase of a transaction, C/BE3-0 define the bus command. During the data phase, C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0 applies to byte 0, and C/BE3 applies to byte 3.

During an address phase (when using DAC commands or when REQ64B is asserted), the actual bus command is transferred on C/BE7-4; otherwise, these bits are reserved and indeterminate. During a data phase, C/BE7-4 are Byte Enables indicating which byte lanes carry meaningful data when a 64-bit transaction has been negotiated by the assertion of REQ64B and ACK64B. C/BE4 applies to byte 4 and C/BE7 applies to byte 7.

PCI clock: This clock input provides timing for all PCI transactions and is input to the PCI device. Supports up to a 66MHz PCI clock. Clock Run: This signal is used by the RTL8169 to request starting (or speeding up) the clock, CLK. CLKRUNB also indicates the clock status. For the RTL8169, CLKRUNB is an open drain output as well as an input. The RTL8169 requests the central resource to start, speed up, or maintain the interface clock by the assertion of CLKRUNB. For the host system, it is an S/T/S signal. The host system (central resource) is responsible for maintaining CLKRUNB asserted, and for driving it high to the negated (deasserted) state.

Device Select: As a bus master, the RTL8169 samples this signal to insure that a PCI target recognizes the destination address for the data transfer. As a target, the RTL8169 asserts this signal low when it recognizes its target address after FRAMEB is asserted.

Cycle Frame: As a bus master, this pin indicates the beginning and duration of an access. FRAMEB is asserted low to indicate the start of a bus transaction. While FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the transaction is in the final data phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it.

RTL8169

2002/03/27 Rev.1.21

GNTB I 177

ACK64B S/T/S 31

REQB T/S 178

REQ64B S/T/S 32

IDSEL I 191

INTAB O/D 174

IRDYB S/T/S 204

TRDYB S/T/S 205

PAR T /S 5

PAR64 T/S 39

cont...

RTL8169

Grant: This signal is asserted low to indicate to the RTL8169 that the

central arbiter has granted the ownership of the bus to the RTL8169. This input is used when the RTL8169 is acting as a bus master.

Acknowledge 64-bit Transfer: This signal is asserted low by the device that has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. ACK64B has the same timing as DEVSELB.

Request: The RTL8169 will assert this signal low to request the ownership of the bus from the central arbiter.

Request 64-bit Transfer: The RTL8169 asserts this signal low to indicate that it wants to perform a 64-bit data transfer.

If the RTL8169 sees the REQ64B asserted on the rising edge of PCI RSTB, the RTL8169 is on 64-bit slot and is capable of 64-bit transaction. Otherwise, the RTL8169 is on 32-bit slot.

Initialization Device Select: This pin allows the RTL8169 to identify when configuration read/write transactions are intended for it.

Interrupt A: Used to request an interrupt. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask.

Initiator Ready: This indicates the initiating agent’s ability to complete the current data phase of the transaction.

As a bus master, this signal will be asserted low when the RTL8169 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low. As a target, this signal indicates that the master has put data on the bus.

Target Ready: This indicates the target agent’s ability to complete the current phase of the transaction.

As a bus master, this signal indicates that the target is ready for the data during write operations and with the data during read operations. As a target, this signal will be asserted low when the (slave) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYB signal. Data transaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low.

Parity: This signal indicates even parity across AD31-0 and C/BE3-0 including the PAR pin. PAR is stable and valid one clock after each address phase. For data phase, PAR is stable and valid one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. As a bus master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. Parity Upper Double Word: This signal indicates even parity across AD63-32 and C/BE7-4 including the PAR64 pin. PAR64 is valid one clock after each address phase on any transaction in which REQ64B is asserted. PAR64 is stable and valid for 64-bit data phase one clock after either IRDYB is asserted on a write transaction or TRDYB is asserted on a read transaction. As a bus master, PAR64 is asserted during address and write data phases. As a target, the RTL8169 only supports 32-bit transfers, so it will not assert PAR64.

2002/03/27 Rev.1.21

M66EN I 173

PERRB S/T/S 1

SERRB O/D 3

STOPB S/T/S 208

RSTB I 175

66MHZ_ENABLE: This pin indicates to the RTL8169 whether the bus segment is operating at 66 or 33MHz. When this pin (active high) is asserted, the current PCI bus segment that the RTL8169 resides on operates in 66-MHz mode. If this pin is deasserted, the current PCI bus segment operates in 33-MHz mode.

Parity Error: This pin is used to report data parity errors during all PCI transactions except a Special Cycle. PERRB Is driven active (low) two clocks after a data parity error is detected by the device receiving data, and the minimum duration of PERRB is one clock for each data phase with parity error detected.

System Error: If an address parity error is detected and Configuration Space Status register bit 15 (detected parity error) is enabled, the RTL8169 asserts the SERRB pin low and bit 14 of Status register in Configuration Space.

Stop: Indicates that the current target is requesting the master to stop the current transaction. Reset: When RSTB is asserted low, the RTL8169 performs an internal system hardware reset. RSTB must be held for a minimum of 120 ns periods.

RTL8169

5.3 FLASH/BootPROM/EEPROM/MII Interface

Symbol Type Pin No Description

MA[16:9], MA7, MA[5:3]

MA8

MA6

MA2/EESK O 92

MA1/EEDI O 91 MA0/EEDO O, I 90 EECS O 93

MD7-0 I/O 119, 121-127 Boot PROM data bus during Boot PROM mode.

O, I

112-109, 107,

105-104, 102, 100,

97-95

101

Boot PROM Address Bus: These pins are used to access up to a 128k-byte flash memory or EPROM.

MA16-3: Output pins to the Boot PROM address bus.

MA8: Input pin as Aux. Power detect pin to detect if Aux. Power exists

or not, when initial power-on. Besides connecting this pin to Boot PROM, it should be pulled high to the Aux. Power via a resistor to detect Aux. power. If this pin is not pulled high to Aux. Power, the RTL8169 assumes that no Aux. power exists. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor.

MA6/9356SEL: Input pin as 9356 select pin at initial power-up. When this pin is pulled high with a 10KΩ resistor, the 93C56 EEPROM is used to store the resource data and CIS for the RTL8169. The RTL8169 latches the status of this pin at power-up to determine what EEPROM (93C46 or 93C56) is used, afterwards, this pin is used as MA6

MA2-0: The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46 (93C56) programming or auto-load mode.

EEPROM Chip Select: 93C46 (93C56) chip select

ROMCSB O 128 OEB O 130

WEB O 129

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ROM Chip Select: This is the chip select signal of the Boot PROM. Output Enable: This enables the output buffer of the Boot PROM or

Flash memory during a read operation. Write Enable: This signal strobes data into the Flash memory during a

write cycle.

5.4 LED Interface

Symbol Type Pin No Description

LED3-0 O 114-116, 118

LED pins (Active low)

1000BaseT mode:

RTL8169

LEDS1-

00 01 10 11

LED0 LED1

LED2 LED3

TBI mode:

LEDS1-

Tx/Rx ACT(Tx/Rx) Tx LINK10/ACT

LINK100 LINK10/100/

1000

LINK10 FULL Rx FULL

LINK1000 - FULL LINK1000/ACT

LINK10/100/

1000

00 01 10 11

0 LED0 LED1 LED2 LED3

During power down mode, the LED signals are logic high.

ACT ACT Tx -

- LINK LINK -

- FULL Rx FULL

LINK - FULL LINK

5.5 GMII, TBI, PHY CP

Gigabit Media Independent Interface, Ten Bit Interface, PHY Control Pin

Symbol Type Pin No Description

GTxCLK O 145

TxCLK I 147

TxEN/

O 143

Tx[9]

Tx[8] O 146

cont...

Gigabit Tx clock: In GMII mode (1000Mbps Tx clock), GTxCLK is a continuous clock used for operation at 1000Mbps. GTxCLK provides the timing reference for the transfer of the TxEN, TxER, and TxD signals. The values of TxEN, TxER, and TxDs are sampled by the PHY on the rising edge of GTxCLK.

In GMII mode or TBI mode, the GTxCLK can be used as a 125MHz reference clock, and it used as the 125MHz transmit clock to an external PMD and is the reference for transmit TBI signaling.

Transmit Clock (MII mode only): TxCLK is a continuous clock that provides a timing reference for the transfer of TxD[3:0], TxEN. In MII mode, it uses the 25MHz or 2.5MHz supplied by the external PMD device. Transmit Enable: In GMII mode (or MII mode), the assertion of TxEN indicates that the RTL8169 is presenting data on the GMII (or MII) for transmission. TxEn is asserted synchronously with the first octet (or nibble) of the preamble and remains asserted while all octets (or nibbles) to be transmitted are presented to the GMII (or MII).

This signal is synchronous to TxCLK and provides precise framing for data carried on TXD3-0/TXD7-0 for the external PMD. It is asserted when TXD3-0/TXD7-0 contains valid data to be transmitted.

Tx[9]: In TBI mode, Tx[9] is the MSB of the 10-bit vector representing one transmission code-group. Tx[0] is the first bit to be transmitted, and Tx[9] is the last bit to be transmitted. Tx[8] (TBI mode only): In TBI mode, Tx[8] is one of the 10-bit vector representing one transmission code-group.

LINK100/ACT

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TxD[7:0]/ Tx[7:0]

RxCLK/ RxCLK0

RxCLK1 I 154

RxER/ Rx[9]

RxDV/ Rx[8]

RxD[7:0]/ Rx[7:0]

COL I 151

cont...

O 135-142

I 156

I 152

I 157

I 165-158

Transmit Data: In GMII mode, TxD[7:0] is a bundle of eight data signals, representing a data byte on GMII for PHY to transmit. In MII mode, only TxD[3:0] represent a data nibble on MII for PHY to transmit. TxD[7:0] or TxD[3:0] transition synchronously with respect to GTxCLK or TxCLK.

Tx[7:0]: In TBI mode, TxD[7:0] is part of the 10-bit vector (TxD[9:0]) representing one transmission code-group. Receive Clock(0): RxCLK: In GMII mode or MII mode, the receive clock is a continuous clock that provides the timing reference for the transfer of the RxDV, RxER, and RxD from PHY device. RxDV, RxER, and RxD are sampled on the rising edge of RxCLK.

RxCLK0: In TBI mode, the 62.5MHz receive clock is a continuous clock and provides timing reference for the RTL8169 to latch odd-numbered receive code-groups from PHY device. Receive Clock1: RxCLK1: In TBI mode, the 62.5MHz receive clock is a continuous clock and provides timing reference for the RTL8169 to latch even-numbered receive code-groups from PHY device. Receive Coding Error: In GMII or MII mode, this pin is asserted synchronously with respect to RxCLK, to indicate that the PHY device detected a symbol that is not part of the valid data or delimiter set somewhere in the frame being received. The RxER may be asserted for one or more clock cycles.

Rx[9]: In TBI mode, Rx[9] is the MSB of the 10-bit vector representing one receive code-group. Rx[0] is the first bit received, and Rx[9] is the last bit received.

Receive Data Valid: In GMII or MII mode, this input pin is asserted synchronously with respect to RxCLK, to indicate that the PHY is presenting recovered, decoded, and valid data to the RTL8169. RxDV remains asserted while valid data is being presented by the PHY.

Rx[8]: In TBI mode, Rx[8] is a bit of the 10-bit vector representing one receive code-group. Rx[0] is the first bit received, and Rx[9] is the last bit received.

Receive Data: In GMII mode, RxD[7:0] is a bundle of eight data signals, representing a data byte transmitted from PHY to the RTL8169 on GMII. In MII mode, only RxD[3:0] represent a data nibble transmitted from PHY to the RTL8169 on MII. RxD[7:0] or RxD[3:0] transition synchronously with respect to RxCLK.

Rx[7:0]: In TBI mode, RxD[7:0] is part of the 10-bit vector (RxD[9:0]) representing one receive code-group.

Collision Detected: In GMII or MII mode, this input pin is asserted high by PHY to indicate the detection of a collision on the twisted pair medium, and remains asserted while the collision condition persists. In full duplex mode, this pin’s status is ignored by the RTL8169. The COL transitions asynchronously with respect to RxCLK, GTxCLK, or TxCLK.

In TBI mode, this pin’s status is ignored by the RTL8169.

RTL8169

2002/03/27 Rev.1.21

CRS I 148

MDC O 169

MDIO I/O 170

TBILBK O 133

RSTPHYB O 132

Carrier Sense: In GMII or MII mode, this pin is asserted high by the GMII/MII PHY device whenever the transmit or receive medium is not idle, and is deasserted when both transmit and receive media are idle. The CRS remains asserted throughout the duration of a collision condition. The CRS transitions asynchronously with respect to RxCLK, GTxCLK, or TxCLK.

In TBI mode, this pin’s status is ignored by the RTL8169. Management Data Clock: In GMII or MII mode, it is a synchronous

clock to the MDIO management data input/output serial interface (about

3.125MHz) which may be asynchronous to transmit and receive clocks.

In TBI mode, this pin is a reserved pin. Management Data Input/Output: Bi-directional signal used to

transfer or receive control and status information from the PHY device. MDIO is driven and sampled synchronously with respect to MDC.

In TBI mode, this pin is a reserved pin. TBI LoopBack: The RTL8169 asserts this pin high when the TBI is in loopback mode. PHY Reset pin: An active low signal used by the RTL8169 to force hardware reset to external PHYceiver at initial power-on.

RTL8169

5.6 Clock and NC Pins

Symbol Type Pin No Description

Clock125 I 168

NC - 2, 4, 6, 45, 47, 49, 51,

103, 106, 108, 153,

155,

125MHz clock input: The 125MHz reference clock for the RTL8169 comes from either external PHYceiver or 125MHz OSC.

Reserved

5.7 Power Pins

Symbol Type Pin No Description

VDD33 P 8, 18, 30, 41, 55, 65,

77, 89, 113, 131, 144,

167, 179, 189, 200 VDD18 P 27, 120, 68, 166 GND P 13, 23, 36, 48, 60, 71,

82, 98, 117, 134, 150,

171, 184, 195, 206, 33,

94, 72, 149

+3.3V

+1.8V Ground

2002/03/27 Rev.1.21

6. Register Descriptions

The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space.

RTL8169

Offset

0000h R/W IDR0

0001h R/W IDR1 0002h R/W IDR2 0003h R/W IDR3 0004h R/W IDR4 0005h R/W IDR5

0006h-0007h - -

0008h R/W MAR0

0009h R/W MAR1 000Ah R/W MAR2 000Bh R/W MAR3 000Ch R/W MAR4 000Dh R/W MAR5 000Eh R/W MAR6

000Fh R/W MAR7 0010h-0017h R/W DTCCR 0018h-001Fh - 0020h-0027h R/W TNPDS

0028h-002Fh R/W THPDS

0030h-0033h R/W FLASH 0034h-0035h R ERBCR

0036h R ERSR

0037h R/W CR

0038h W TPPoll

0039h-003Bh - -

003Ch-003Dh R/W IMR

003Eh-003Fh R/W ISR

0040h-0043h R/W TCR 0044h-0047h R/W RCR

0048h-004Bh R/W TCTR

004Ch-004Fh R/W MPC

0050h R/W 9346CR

0051h R/W CONFIG0

0052h R/W CONFIG1

0053h R/W CONFIG2

0054h R/W CONFIG3

cont...

R/W Tag Description

ID Register 0: The ID registers 0-5 are only permitted to write by

4-byte access. Read access can be byte, word, or double word access. The initial value is autoloaded from EEPROM EthernetID field.

ID Register 1 ID Register 2 ID Register 3

ID Register 4

ID Register 5 Reserved Multicast Register 0: The MAR registers 0-7 are only permitted to

write by 4-bye access. Read access can be byte, word, or double word access. Driver is responsible for initializing these registers.

Multicast Register 1 Multicast Register 2 Multicast Register 3 Multicast Register 4 Multicast Register 5 Multicast Register 6 Multicast Register 7 Dump Tally Counter Command Register (64-byte alignment) Reserved Transmit Normal Priority Descriptors: Start address (64-bit).

(256-byte alignment) Transmit High Priority Descriptors: Start address (64-bit).

(256-byte alignment)

Flash memory read/write register Early Receive (Rx) Byte Count Register Early Rx Status Register Command Register Transmit Priority Polling register Reserved Interrupt Mask Register Interrupt Status Register Transmit (Tx) Configuration Register Receive (Rx) Configuration Register Timer CounT Register: This register contains a 32-bit

general-purpose timer. Writing any value to this 32-bit register will reset the original timer and begin the count from zero.

Missed Packet Counter: This 24-bit counter indicates the number of packets discarded due to Rx FIFO overflow. After a s/w reset, MPC is cleared. Only the lower 3 bytes are valid.

When any value is written to MPC, it will be reset.

93C46 (93C56) Command Register Configuration Register 0 Configuration Register 1 Configuration Register 2 Configuration Register 3

2002/03/27 Rev.1.21

0055h R/W CONFIG4

0056h R/W CONFIG5

0057h - -

0058h-005Bh

005Ch-005Dh R/W MULINT

005Eh-005Fh - -

0060h-0063h R/W PHYAR 0064h-0067h R/W TBICSR0 0068h-0069h R/W TBI_ANAR

006Ah-006Bh R TBI_LPAR

006Ch

006Dh-0081h

0082-0083h - 0084h–008Bh R/W Wakeup0 008Ch–0093h R/W Wakeup1 0094h–009Bh R/W Wakeup2LD

009Ch–00A3h R/W Wakeup2HD 00A4h–00ABh R/W Wakeup3LD 00ACh–00B3h R/W Wakeup3HD 00B4h–00BBh R/W Wakeup4LD 00BCh–00C3h R/W Wakeup4HD

00C4h-00C5h R/W CRC0 00C6h-00C7h R/W CRC1

00C8h-00C9h R/W CRC2 00CAh-00CBh R/W CRC3 00CCh-00CDh R/W CRC4

00CEh-00D9h - 00DAh-00DBh R/W RMS 00DCh-00DFh - -

00E0h-00E1h R/W C+CR 00E2h-00E3h - -

00E4h-00EBh R/W RDSAR

00ECh R/W ETThR

00EDh-00EFh - -

00F0h-00F3h R/W FER

00F4h-00F7h R/W FEMR 00F8h-00FBh R FPSR 00FCh-00FFh W FFER

R /W

TimerInt

PHYStatus

RTL8169

Configuration Register 4 Configuration Register 5 Reserved Timer Interrupt Register: Once having written a nonzero value to

this register, the Timeout bit of ISR register will be set whenever the TCTR reaches to this value. The Timeout bit will never be set as long as TimerInt register is zero.

Multiple Interrupt Select Reserved PHY Access Register TBI Control and Status Register TBI Auto-Negotiation Advertisement Register TBI Auto-Negotiation Link Partner Ability Register PHY(GMII, MII, or TBI) Status Register

Reserved

Reserved Power Management wakeup frame0 (64bit) Power Management wakeup frame1 (64bit) Power Management wakeup frame2 (128bit), low D-Word Power Management wakeup frame2, high D-Word Power Management wakeup frame3 (128bit), low D-Word Power Management wakeup frame3, high D-Word Power Management wakeup frame4 (128bit), low D-Word Power Management wakeup frame4, high D-Word 16-bit CRC of wakeup frame 0 16-bit CRC of wakeup frame 1 16-bit CRC of wakeup frame 2 16-bit CRC of wakeup frame 3 16-bit CRC of wakeup frame 4 Reserved Rx packet Maximum Size Reserved C+ Command Register Reserved Receive Descriptor Start Address Register (256-byte alignment) Early Transmit Threshold Register Reserved Function Event Register (Cardbus only) Function Event Mask Register (CardBus only) Function Present State Register (CardBus only) Function Force Event Register (CardBus only)

2002/03/27 Rev.1.21

6.1 DTCCR: Dump Tally Counter Command (Offset 0010h-0017h, R/W)

Bit R/W Symbol Description

63:6 R/W CntrAddr

5:4 - - Reserved

3 R/W Cmd

2:0 - -

Starting address of the 12 Tally Counters being dumped to. (64-byte alignment address, 64 bytes long)

Offset of

starting address

0 TxOk 64-bit counter of Tx Ok packets. 8 RxOk 64-bit counter of Rx Ok packets. 16 TxER 64-bit packet counter of Tx errors including Tx

24 RxEr 32-bit packet counter of Rx errors including CRC

28 MissPkt 16-bit counter of missed packets (CRC Ok)

30 FAE 16-bit counter of Frame Alignment Error packets

32 Tx1Col 32-bit counter of those Tx Ok packets with only 1

36 TxMCol 32-bit counter of those Tx Ok packets with more

40 RxOkPhy 64-bit counter of all Rx Ok packets with physical

48 RxOkBrd 64-bit counter of all Rx Ok packets with broadcast

56 RxOkMul 32-bit counter of all Rx Ok packets with multicast

60 TxAbt 16-bit counter of Tx abort packets. 62 TxUndrn 16-bit counter of Tx underrun and discard packets

Command: When set, the RTL8169 begins dumping 13 Tally counters to the address specified above.

When this bit is reset by the RTL8169, the dumping has been completed.

Reserved

Counter Description

abort, carrier lost, Tx underrun, and out of window collision.

error packets (should be larger than 8 bytes) and missed packets.

resulted from Rx FIFO full.

(MII mode only)

collision happened before Tx Ok.

than 1, and less than 16 collisions happened before Tx Ok.

address matched destination ID.

destination ID.

(only possible on jumbo frames).

RTL8169

2002/03/27 Rev.1.21

6.2 FLASH: Flash Memory Read/Write (Offset 0030h-0033h, R)

Bit R/W Symbol Description

31:24 R/W MD7-MD0

23:21 - - Reserved

20 W ROMCSB 19 W OEB 18 W WEB 17 W SWRWEn

16:0 W MA16-MA0

Flash Memory Data Bus: These bits set and reflect the state of the MD7 - MD0 pins during the write and read process respectively.

Chip Select: This bit sets the state of the ROMCSB pin. Output Enable: This bit sets the state of the OEB pin. Write Enable: This bit sets the state of the WEB pin. Enable software access to flash memory:

1: Enable read/write access to flash memory via software and disable the EEPROM access during flash memory access via software.

0: Disable read/write access to flash memory via software. Flash Memory Address Bus: These bits set the state of the MA16-0 pins.

6.3 ERSR: Early Rx Status

RTL8169

(Offset 0036h, R)

Bit R/W Symbol Description

7:4 - -

3 R ERGood

2 R ERBad

1 R EROVW

0 R EROK

Reserved Early Rx Good packet: This bit is set whenever a packet is completely

received and the packet is good. Writing a ‘1’ will clear this bit. Early Rx Bad packet: This bit is set whenever a packet is completely

received and the packet is bad. Writing a ‘1’ will clear this bit. Early Rx OverWrite: This bit is set when the RTL8169's local address

pointer is equal to CAPR. In the early mode, this is different from buffer overflow. It happens when the RTL8169 detects an Rx error and wants to fill another packet data from the beginning address of that error packet. Writing a ‘1’ will clear this bit. Early Rx OK: The power-on value is 0. It is set when the Rx byte count of the arriving packet exceeds the Rx threshold. After the whole packet is received, the RTL8169 will set ROK or RER in ISR and clear this bit simultaneously. Setting this bit will invoke a ROK interrupt.

2002/03/27 Rev.1.21

6.4 Command (Offset 0037h, R/W)

Bit R/W Symbol Description

7:5 - -

4 R/W RST

3 R/W RE 2 R/W TE

1:0 - -

Reserved Reset: Setting this bit to 1 forces the RTL8169 into a software reset

state which disables the transmitter and receiver, reinitializes the FIFOs, and resets the system buffer pointer to the initial value (the start address of each descriptor group set in TNPDS, THPDS and RDSAR registers). The values of IDR0-5, MAR0-7 and PCI configuration space will have no changes. This bit is 1 during the reset operation, and is cleared to 0 by the RTL8169 when the reset operation is complete.

Receiver Enable Transmit Enable Reserved

6.5 TPPoll: Transmit Priority Polling (Offset 0038h, R/W)

Bit R/W Symbol Description

7 W HPQ

6 W NPQ

5:1 - -

0 W FSWInt

High Priority Queue polling: Writing a ‘1’ to this bit will notify the RTL8169 that there is a high priority packet(s) waiting to be transmitted. The RTL8169 will clear this bit automatically after all high priority packets have been transmitted.

Writing a ‘0’ to this bit has no effect. Normal Priority Queue polling: Writing a ‘1’ to this bit will notify the RTL8169 that there is a normal priority packet(s) waiting to be transmitted. The RTL8169 will clear this bit automatically after all normal priority packets have been transmitted.

Writing a ‘0’ to this bit has no effect.

Reserved Forced Software Interrupt: Writing a ‘1’ to this bit will trigger an

interrupt, and the SWInt bit (bit8, ISR, offset3Eh-3Fh) will set.

The RTL8169 will clear this bit automatically after the SWInt bit (bit8, ISR) is cleared.

Writing a ‘0’ to this bit has no effect.

RTL8169

2002/03/27 Rev.1.21

6.6 Interrupt Mask (Offset 003Ch-003Dh, R/W)

Bit R/W Symbol Description

15 R/W SERR

14 R/W TimeOut

13:10 - -

9 - 8 R/W SWInt

7 R/W TDU

6 R/W FOVW

5 R/W PUN/LinkChg

4 R/W RDU

3 R/W TER

2 R/W TOK

1 R/W RER

0 R/W ROK

System Error Interrupt:

1: Enable; 0: Disable.

Time Out Interrupt:

1: Enable; 0: Disable.

Reserved Reserved Software Interrupt:

1: Enable; 0: Disable.

Tx Descriptor Unavailable Interrupt:

1: Enable; 0: Disable.

Rx FIFO Overflow Interrupt:

1: Enable; 0: Disable.

Packet Underrun/Link Change Interrupt:

1: Enable; 0: Disable.

Rx Buffer Overflow/Rx Descriptor Unavailable Interrupt:

1: Enable; 0: Disable.

Tx Error Interrupt:

1: Enable; 0: Disable.

Tx Ok:

Transmit (Tx) OK: Indicates that a packet transmission is completed successfully. 1: Enable; 0: Disable.

Rx Error Interrupt:

1: Enable; 0: Disable.

Rx OK Interrupt:

1: Enable; 0: Disable.

RTL8169

2002/03/27 Rev.1.21

6.7 Interrupt Status (Offset 003Eh-003Fh, R/W)

Bit R/W Symbol Description

15 R/W SERR

14 R/W TimeOut

13:10 - -

9 - -

8 R/W SWInt

7 R/W TDU

6 R/W FOVW

5 R/W PUN/LinkChg

4 R/W RDU

3 R/W TER

2 R/W TOK

1 R/W RER

0 R/W ROK

 Writing 1 to any bit in the ISR will reset that bit.

System Error: This bit is set to 1 when the RTL8169 signals a system error on the PCI bus.

Time Out: This bit is set to 1 when the TCTR register reaches the value of the TimerInt register.

Reserved Reserved Software Interrupt: This bit is set to 1 whenever a ‘1’ is written by

software to FSWInt (bit0, offset D9h, TPPoll register). Tx Descriptor Unavailable: When set, this bit indicates that the Tx

descriptor is unavailable. Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI

performance, or overloaded PCI traffic. Packet Underrun/Link Change: This bit is set to 1 when CAPR is

written but the Rx buffer is empty, or when link status is changed. Rx Descriptor Unavailable: When set to 1, this bit indicates that the

Rx descriptor is unavailable.

The MPC (Missed Packet Counter, offset 4Ch-4Fh) indicates the number of packets discarded after Rx FIFO overflowed.

Transmit (Tx) Error: This bit set to 1 indicates that a packet transmission was aborted, due to excessive collisions, according to the TXRR's setting in the TCR register.

Transmit (Tx) OK: When set to 1, this bit indicates that a packet transmission has been completed successfully.

Receive (Rx) Error: When set to 1, this bit indicates that a packet has either a CRC error or a frame alignment error (FAE). A Rx error packet of CRC error is determined according to the setting of RER8, AER, AR bits in RCR register (offset 44h-47h).

Receive (Rx) OK: In normal mode, this bit set to 1 indicates the successful completion of a packet reception. In early mode, this bit set to 1 indicates that the Rx byte count of the arriving packet exceeds the early Rx threshold.

RTL8169

2002/03/27 Rev.1.21

6.8 Transmit Configuration (Offset 0040h-0043h, R/W)

Bit R/W Symbol Description

31 - -

30:26 R HWVERID0

25:24 R/W IFG1, 0

23 R HWVERID1

22:20 -

19 R/W IFG2

18:17 R/W LBK1, LBK0

16 R/W CRC

15:11 - -

cont...

Reserved Hardware Version ID0:

Bit30 Bit29 Bit28 Bit27 Bit26 Bit23

RTL8139 1 1 0 0 0 0

RTL8139A 1 1 1 0 0 0

RTL8139A-G 1 1 1 0 0 1

RTL8139B 1 1 1 1 0 0

RTL8130 1 1 1 1 1 0

RTL8139C 1 1 1 0 1 0

RTL8139C+ 1 1 1 0 1 1

RTL8100 1 1 1 1 0 1 RTL8169 0 0 0 0 0 0 Reserved All other combination

InterFrameGap Time: This field allows adjustment of the interframe gap time to be longer than the standards of 9.6 µs for 10Mbps, 960 ns for 100Mbps, and 96 ns for 1000Mbps. The time can be programmed from 9.6 µs to 14.4 µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns to 144ns (1000Mbps).

The setting of the inter frame gap is:

IFG[2:0] IFG@1000MHz

(ns)

0 1 1 96 960 9.6 1 0 1 96 + 8 960 + 8 * 10 9.6 + 8 * 0.1 1 1 1 96 + 16 960 + 16 * 10 9.6 + 16 * 0.1 0 0 1 96 + 24 960 + 24 * 10 9.6 + 24 * 0.1 0 1 0 96 + 48 960 + 48 * 10 9.6 + 48 * 0.1

-Other values are reserved.

Hardware Version ID1: Please see HWVERID0. Reserved InterFrameGap2 Loopback test: There will be no packets on the (G)MII or TBI interface

in Digital loopback mode, provided the external phyceiver is also set in loopback mode. The digital loopback function is independent of the current link status.

For analog loopback tests, software must force the external phyceiver into loopback mode while the RTL8169 operates normally.

00 : Normal operation 01 : Digital loopback mode 10 : Reserved 11 : Reserved

Append CRC: Setting this bit to 1 means that there is no CRC appended at the end of a packet. Setting to 0 means that there is a CRC appended at the end of a packet.

Reserved

IFG@100MHz

(ns)

RTL8169

IFG@10MHz

(µs)

2002/03/27 Rev.1.21

10:8 R/W MXDMA2, 1, 0

7:0 - -

 The TCR register can only be changed after having set TE (bit2, Command register, offset 0037h).

Max DMA Burst Size per Tx DMA Burst: This field sets the maximum size of transmit DMA data bursts according to the following table:

000 = 16 bytes 001 = 32 bytes 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = Unlimited

Reserved

6.9 Receive Configuration (Offset 0044h-0047h, R/W)

Bit R/W Symbol Description

31:25 - -

24 R/W MulERINT

23:17 - -

16 R/W RER8 When this bit is set to 1, the RTL8169 will calculate the CRC of any

15:13 R/W RXFTH2, 1, 0

12:11 - -

cont...

Reserved Multiple Early Interrupt Select: When this bit is set to 1, any received

packets invoke an early interrupt according to the MULINT<MISR[11:0]> setting in early mode.

Reserved

received packed with a length larger than 8 bytes.

When this bit is cleared, the RTL8169 only calculates the CRC of any received packet with a length larger than 64-bytes. The power-on default is zero.

If AER or AR is set, the RTL8169 always calculates the CRC of any incoming packet with a packet length larger than 8 bytes. The RER8 is in a “Don’t care” state in this situation.

Rx FIFO Threshold: Specifies the Rx FIFO Threshold level. When the number of the received data bytes from a packet, which is being received into the Rx FIFO of the RTL8169, has reached this level (or the FIFO contains a complete packet), the receive PCI bus master function will begin to transfer the data from the FIFO to the host memory. This field sets the threshold level according to the following table:

000 = Reserved 001 = Reserved 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = no Rx threshold. The RTL8169 begins the transfer of data after having received a whole packet in the FIFO.

Reserved

RTL8169

2002/03/27 Rev.1.21

10:8 R/W MXDMA2, 1, 0

7 - 6 R 9356SEL This bit reflects what type of EEPROM is used.

5 R/W AER

4 R/W AR

3 R/W AB 2 R/W AM 1 R/W APM 0 R/W AAP

RTL8169

Max DMA Burst Size per Rx DMA Burst: This field sets the

maximum size of the receive DMA data bursts according to the following table:

000 = Reserved 001 = Reserved 010 = 64 bytes 011 = 128 bytes 100 = 256 bytes 101 = 512 bytes 110 = 1024 bytes 111 = Unlimited

Reserved

1: The EEPROM used is 9356. 0: The EEPROM used is 9346.

Accept Error Packet:

When set to 1, all packets with CRC error, alignment error, and/or collided fragments will be accepted.

When set to 0, all packets with CRC error, alignment error, and/or collided fragments will be rejected.

Accept Runt: This bit set to 1 allows the receiver to accept packets that are smaller than 64 bytes. The packet must be at least 8 bytes long to be accepted as a runt.

Accept Broadcast Packets: 1: Accept, 0: Reject Accept Multicast Packets: 1: Accept, 0: Reject Accept Physical Match Packets: 1: Accept, 0: Reject Accept All Packets with Destination Address: 1: Accept, 0: Reject

2002/03/27 Rev.1.21

6.10 9346CR: 93C46 (93C56) Command (Offset 0050h, R/W)

Bit R/W Symbol Description

7:6 R/W EEM1-0

5:4 - -

3 R/W EECS 2 R/W EESK 1 R/W EEDI 0 R EEDO

Operating Mode: These 2 bits select the RTL8169 operating mode.

EEM1 EEM0 Operating Mode

0 0 Normal (RTL8169 network/host communication mode)

0 1 Auto-load: Entering this mode will make the RTL8169

load the contents of the 93C46 (93C56) as when the RSTB signal is asserted. This auto-load operation will take about 2 ms. Upon completion, the RTL8169 automatically returns to normal mode (EEM1 = EEM0 =

0) and all of the other registers are reset to default values.

1 0 93C46 (93C56) programming: In this mode, both network

and host bus master operations are disabled. The 93C46 (93C56) can be directly accessed via bit3-0 which now reflect the states of EECS, EESK, EEDI, & EEDO pins respectively.

1 1 Config register write enable: Before writing to CONFIGx

registers, the RTL8169 must be placed in this mode. This will prevent RTL8169 configurations from accidental change.

Reserved

These bits reflect the state of the EECS, EESK, EEDI & EEDO pins in auto-load or 93C46 (93C56) programming mode and are valid only when the Flash bit is cleared.

Note: EESK, EEDI and EEDO is valid after boot ROM complete.

RTL8169

6.11 CONFIG 0 (Offset 0051h, R/W)

Bit R/W Symbol Description

7:3 - 2-0 R BS2, BS1, BS0

Reserved Select Boot ROM Size

BS2 BS1 BS0 Description

0 0 0 No Boot ROM

0 0 1 8K Boot ROM

0 1 0 16K Boot ROM

0 1 1 32K Boot ROM

1 0 0 64K Boot ROM

1 0 1 128K Boot ROM

1 1 0 unused

1 1 1 unused

2002/03/27 Rev.1.21

6.12 CONFIG 1 (Offset 0052h, R/W)

Bit R/W Symbol Description

7:6 R/W LEDS1-0 Refer to the LED PIN definition. These bits initial value com from

93C46/93C56.

5 R/W DVRLOAD

4 R/W LWACT

3 R MEMMAP 2 R IOMAP 1 R/W VPD

0 R/W PMEn

Driver Load: Software maybe use this bit to make sure that the driver has been loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN, MEMEN, BMEN of PCI configuration space are written, the RTL8169 will clear this bit automatically.

LWAKE Active Mode: The LWACT bit and LWPTN bit in CONFIG4 register are used to program the LWAKE pin’s output signal. According to the combination of these two bits, there may be 4 choices of LWAKE signal, i.e., active high, active low, positive (high) pulse, and negative (low) pulse. The output pulse width is about 150 ms. In CardBus application, the LWACT and LWPTN have no meaning.

The default value of each of these two bits is 0, i.e., the default output signal of LWAKE pin is an active high signal.

0 Active high* Active low

* Default value.

Memory Mapping: The operational registers are mapped into PCI memory space. I/O Mapping: The operational registers are mapped into PCI I/O space. Vital Product Data: Set to enable Vital Product Data. The VPD data is stored in

93C46 or 93C56 from within offset 40h-7Fh.

Power Management Enable:

PMEn setting:

LWAKE output

LW PT N

1 Positive pulse Negative pulse

Writable only when 93C46CR register EEM1=EEM0=1

Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI Configuration space offset 06h. Let B denote the Cap_Ptr register in the PCI Configuration space offset 34h. Let C denote the Cap_ID (power management) register in the PCI Configuration space offset 0DCh. Let D denote the power management registers in the PCI Configuration space offset from 0DDh to 0E1h. Let E denote the Next_Ptr (power management) register in the PCI Configuration space offset 0DDh.

0: A=B=C=E=0, D is invalid 1: A=1, B=0DCh, C=01h, D is valid, E is valid and depends on whether VPD is enabled or not.

LWACT

0 1

RTL8169

2002/03/27 Rev.1.21

6.13 CONFIG 2 (Offset 0053h, R)

Bit R/W Symbol Description

7:5 - -

4 R Aux_Status

3 R PCIBusWidth

2:0 R PCICLKF2-0

Reserved Auxiliary Power Present Status:

1: The Aux. Power is present. 0: The Aux. Power is absent. The value of this bit is fixed after each PCI reset.

PCI Bus Width:

1: 64-bit slot 0: 32-bit slot

PCI clock frequency:

RTL8169

6.14 CONFIG 3 (Offset 0054h, R/W)

Bit R/W Symbol Description

7 R GNTSel

6 - 5 R/W Magic

cont...

Grant Select: Select the Frame’s asserted time after the Grant signal has been asserted. The Frame and Grant are the PCI signals. 1: delay one clock from GNT assertion. 0: No delay

Reserved Magic Packet: This bit is valid when the PWEn bit of CONFIG1

register is set. The RTL8169 will assert the PMEB signal to wakeup the operating system when the Magic Packet is received.

Once the RTL8169 has been enabled for Magic Packet wakeup and has been put into an adequate state, it scans all incoming packets addressed to the node for a specific data sequence, which indicates to the controller that this is a Magic Packet frame. A Magic Packet frame must also meet the basic requirements: Destination address + Source address + data + CRC

The destination address may be the node ID of the receiving station or a multicast address, which includes the broadcast address.

The specific sequence consists of 16 duplications of 6 byte ID registers, with no breaks or interrupts. This sequence can be located anywhere within the packet, but must be preceded by a synchronization stream, 6 bytes of FFh. The device will also accept a multicast address, as long as the 16 duplications of the IEEE address match the address of the ID registers.

If the Node ID is 11h 22h 33h 44h 55h 66h, then the format of the Magic frame looks like the following:

Destination address + source address + MISC + FF FF FF FF FF FF + MISC + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + MISC + CRC

PCICLKF2-0 MHz

000 33 001 66

Other values Reserved

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4 R/W LinkUp

3 R CardB_En

2 R CLKRUN_En

1 R FuncRegEn

0 R FBtBEn

6.15 CONFIG 4

RTL8169

Link Up: This bit is valid when the PWEn bit of the CONFIG1 register

is set. The RTL8169, in an adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is reestablished.

Card Bus Enable:

1: Enable CardBus related registers and functions. 0: Disable CardBus related registers and functions.

CLKRUN Enable:

1: Enable CLKRUN. 0: Disable CLKRUN.

Functions Registers Enable (CardBus only):

1: Enable the 4 Function Registers (Function Event Register, Function Event Mask Register, Function Present State Register, and Function Force Event Register) for CardBus application.

0: Disable the 4 Function Registers for CardBus application.

Fast Back to Back Enable: 1: Enable; 0: Disable.

(Offset 0055h, R/W)

Bit R/W Symbol Description

7:5 - -

4 R/W LWPME

3 - 2 R/W LWPTN

1:0 - -

Reserved LANWAKE vs PMEB:

1: The LWAKE can only be asserted when the PMEB is asserted and the ISOLATEB is low.

0: The LWAKE and PMEB are asserted at the same time.

In CardBus applications, this bit has no meaning.

Reserved LWAKE Pattern: Please refer to the LWACT bit in CONFIG1 register. Reserved

2002/03/27 Rev.1.21

RTL8169

6.16 CONFIG 5 (Offset 0056h, R/W)

This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable the Config register write prior to writing to Config5.

Bit R/W Symbol Description

7 - 6 R/W BWF

5 R/W MWF

4 R/W UWF

3:2 - -

1 R/W LANWake

0 R/W PME_STS

 Bit1 and bit0 are auto-loaded from the EEPROM Config5 byte to the RTL8169 Config5 register.

Reserved Broadcast Wakeup Frame:

1: Enable Broadcast Wakeup Frame with mask bytes of only DID

field = FF FF FF FF FF FF.

0: Default value. Disable Broadcast Wakeup Frame with mask bytes

of only DID field = FF FF FF FF FF FF.

The power-on default value of this bit is 0.

Multicast Wakeup Frame:

1: Enable Multicast Wakeup Frame with mask bytes of only DID

field, which is a multicast address.

0: Default value. Disable Multicast Wakeup Frame with mask bytes

of only DID field, which is a multicast address.

The power-on default value of this bit is 0.

Unicast Wakeup Frame:

1: Enable Unicast Wakeup Frame with mask bytes of only DID

field, which is its own physical address.

0: Default value. Disable Unicast Wakeup Frame with mask bytes

of only DID field, which is its own physical address.

The power-on default value of this bit is 0.

Reserved LANWake Signal Enable/Disable:

1: Enable LANWake signal.

0: Disable LANWake signal. PME_Status bit: Always sticky/can be reset by PCI RST# and software.

1: The PME_Status bit can be reset by PCI reset or by software.

0: The PME_Status bit can only be reset by software.

2002/03/27 Rev.1.21

RTL8169

6.17 Multiple Interrupt Select (Offset 005Ch-005Dh, R/W)

Bit R/W Symbol Description

15:12 - -

11:0 R/W MISR11-0

 When MulERINT=1, any received packet invokes an early interrupt according to the MISR[11:0] setting in early mode.

Reserved Multiple Interrupt Select: Indicates that the RTL8169 will make a

receive interrupt after the RTL8169 has transferred the data bytes specified in this register into the system memory. If the value of this register is zero, there will be no early receive interrupts before the whole received packet is transferred to system memory. Bit1, 0 must be zero.

6.18 PHYAR: PHY Access (Offset 0060h-0063h, R/W)

PHY address is fixed at 00001.

Bit R/W Symbol Description

31 R/W Flag

30:21 - 20:16 R/W RegAddr4-0

15:0 R/W Data15-0

Flag bit, used as PCI VPD access method:

1: Write data to MII register, and turn to 0 automatically whenever

the RTL8169 has completed writing to the specified MII register.

0: Read data from MII register, and turn to 1 automatically whenever

the RTL8169 has completed retrieving data from the specified MII

Reserved 5-bit GMII/MII register address. 16-bit GMII/MII register data.

6.19 TBICSR: Ten Bit Interface Control and Status (Offset 0064h-0067h, R/W)

Bit R/W Symbol Description

31 R/W ResetTBI

30 R/W TBILoopBack

29 R/W TBINWEn

28 R/W TBIReNW

27:26 - -

25 R TBILinkOk

24 R TBINWComplete

23:20 TXOSETST3-0

19 - -

18:16 ANST2-0

15:13 - -

12:8 RXST4-0

7:4 SYNCST3-0 3:0 TXCGST3-0

Reset TBI: This bit, when set, indicates to the TBI to reset the interfacing PHY device. This bit is cleared when the reset process is completed. TBI Loopback Enable: This bit, when set, indicates to the TBI that the interfacing PHY device is in loopback mode. TBI Auto-negotiation Enable: This bit, when set, enables the auto-negotiation function for the TBI interface. TBI Restart Auto-negotiation: This bit, when set, restarts the auto-negotiation. This bit is cleared when the auto-negotiation completes.

Reserved TBI Link Ok: This bit, when set, indicates that the channel

connecting to the link partner is established. TBI Nway Complete: This bit, when set, indicates that the auto-negotiation process has completed in TBI mode.

Reserved: For Realtek internal testing. Reserved Reserved: For Realtek internal testing. Reserved Reserved: For Realtek internal testing. Reserved: For Realtek internal testing. Reserved: For Realtek internal testing.

2002/03/27 Rev.1.21

+ 64 hidden pages

Realtek RTL8169 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual