REALTEK RTL8139C, RTL8139L Datasheet

RTL8139C(L)

REALTEK 3.3V SINGLE CHIP

FAST ETHERNET CONTROLLER

WITH POWER MANAGEMENT

RTL8139C(L)

1. Features:.................................................................. 2

2. General Description................................................ 3

3. Block Diagram ........................................................ 4

4. Pin Assignments...................................................... 5

5. Pin Descriptions ...................................................... 6

5.1 Power Management/Isolation Interface .............. 6

5.2 PCI Interface....................................................... 6

5.3 FLASH/EEPROM Interface ............................... 8

5.4 Power Pins .......................................................... 9

5.5 LED Interface ..................................................... 9

5.6 Attachment Unit Interface .................................. 9

5.7 Test and Other Pins............................................. 9

6. Register Descriptions............................................ 10

6.1 Receive Status Register in Rx packet header.... 12

6.2 Transmit Status Register................................... 13

6.3 ERSR: Early Rx Status Register....................... 14

6.4 Command Register ........................................... 14

6.5 Interrupt Mask Register .................................... 15

6.6 Interrupt Status Register ................................... 15

6.7 Transmit Configuration Register ...................... 16

6.8 Receive Configuration Register........................ 17

6.9 9346CR: 93C46 (93C56) Command Register ......... 19

6.10 CONFIG 0: Configuration Register 0............. 20

6.11 CONFIG 1: Configuration Register 1............. 21

6.12 Media Status Register ..................................... 22

6.13 CONFIG 3: Configuration Register3.............. 22

5.14 CONFIG 4: Configuration Register4.............. 24

6.15 Multiple Interrupt Select Register ..................... 25

6.16 PCI Revision ID.............................................. 25

6.17 Transmit Status of All Descriptors (TSAD) Register......... 25

6.18 Basic Mode Control Register.......................... 26

6.19 Basic Mode Status Register ............................ 26

6.20 Auto-negotiation Advertisement Register.............. 27

6 .2 1 Auto-Negotiation Link Partner Ability Register ............... 27

6.22 Auto-negotiation Expansion Register .............. 28

6.23 Disconnect Counter ........................................ 28

6.24 False Carrier Sense Counter ........................... 28

6.25 NWay Test Register........................................ 28

6.26 RX_ER Counter.............................................. 29

6.27 CS Configuration Register.............................. 29

6.28 Flash Memory Read/Write Register ........................ 29

6.29 Config5: Configuration Register 5 ................. 30

6.30 Function Event Register ................................. 31

6.31 Function Event Mask Register........................ 31

6.32 Function Present State Register ...................... 32

6.33 Function Force Event Register ....................... 32

7. EEPROM Contents .............................................. 33

7.1 Summary of EEPROM Registers .............................35

7.2 Summary of EEPROM Power Management Registers....... 35

8. PCI Configuration Space Registers..................... 36

8.1 PCI Configuration Space Table ........................ 36

8.2 PCI Configuration Space Functions.................. 37

8.3 Default Values After Power-on (RSTB asserted)...... 42

8.4 PCI Power Management Functions .................. 43

8.5 Vital Product Data (VPD)................................. 45

9. Functional Description ......................................... 46

9.1 Transmit Operation ........................................... 46

9.2 Receive Operation............................................. 46

9.3 Line Quality Monitor ........................................ 46

9.4 Clock Recovery Module ................................... 46

9.5 Loopback Operation ......................................... 46

9.6 Tx Encapsulation ..............................................46

9.7 Collision............................................................ 46

9.8 Rx Decapsulation.............................................. 47

9.9 Flow Control..................................................... 47

9.9.1. Control Frame Transmission..................... 47

9.9.2. Control Frame Reception.......................... 47

9.10 LED Functions................................................ 47

9.10.1 10/100 Mbps Link Monitor...................... 47

9.10.2 LED_RX .................................................. 48

9.10.3 LED_TX ..................................................48

9.10.4 LED_TX+LED_RX.................................49

10. Application Diagram ..........................................50

11. Electrical Characteristics ................................... 51

11.1 Temperature Limit Ratings ............................. 51

11.2 DC Characteristics .......................................... 51

11.2.1 Supply Voltage ........................................ 51

11.3 AC Characteristics .......................................... 52

11.3.1 FLASH/BOOT ROM Timing .................. 52

11.3.2 PCI Bus Operation Timing: ..................... 54

12. Mechanical Dimensions...................................... 60

2002/01/10 Rev.1.4

1

1. Features

 128 pin QFP/LQFP

 Integrated Fast Ethernet MAC, Physical chip and

transceiver in one chip

 10 Mb/s and 100 Mb/s operation

 Supports 10 Mb/s and 100 Mb/s N-way

Auto-negotiation operation

 PCI local bus single-chip Fast Ethernet controller

 Compliant to PCI Revision 2.2

 Supports PCI clock 16.75MHz-40MHz

 Supports PCI target fast back-to-back transaction

 Provides PCI bus master data transfers and PCI memory

space or I/O space mapped data transfers of
RTL8139C(L)'s operational registers

 Supports PCI VPD (Vital Product Data)

 Supports ACPI, PCI power management

 Supports CardBus. The CIS can be stored in 93C56 or

expansion ROM

 Supports up to 128K bytes Boot ROM interface for both

EPROM and Flash memory

 Supports 25MHz crystal or 25MHz OSC as the internal

clock source. The frequency deviation of either crystal or
OSC must be within 50 PPM.

 Compliant to PC99 standard

 Supports Wake-On-LAN function and remote wake-up

(Magic Packet*, LinkChg and Microsoft
frame)

 Supports 4 Wake-On-LAN (WOL) signals (active high,

active low, positive pulse, and negative pulse)

®

wake-up

RTL8139C(L)

 Supports auxiliary power-on internal reset, to be ready

for remote wake-up when main power still remains off

 Supports auxiliary power auto-detect, and sets the

related capability of power management registers in PCI
configuration space.

 Includes a programmable, PCI burst size and early

Tx/Rx threshold.

 Supports a 32-bit general-purpose timer with the

external PCI clock as clock source, to generate
timer-interrupt

 Contains two large (2Kbyte) independent receive and

transmit FIFO’s

 Advanced power saving mode when LAN function or

wakeup function is not used

 Uses 93C46 (64*16-bit EEPROM) or 93C56

(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
application.

 Supports LED pins for various network activity

indications

 Supports digital and analog loopback capability on both

ports

 Half/Full duplex capability

 Supports Full Duplex Flow Control (IEEE 802.3x)

 3.3V power supply with 5V tolerant I/Os.

* Third-party brands and names are the property of their

respective owners.

Note: The model number of the QFP package is RTL8139C. The LQFP package model number is RTL8139CL.

2002/01/10 Rev.1.4

2

RTL8139C(L)

2. General Description

The Realtek RTL8139C(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller that provides 32-bit
performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full
Duplex Flow Control. It also supports Advanced Configuration Power management Interface (ACPI), PCI power management
for modern operating systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management possible. The RTL8139CL is suitable for applications such as CardBus or mobile devices with a
built-in network controller. The CIS data can be stored in either a 93C56 EEPROM or expansion ROM.

In addition to the ACPI feature, the RTL8139C(L) also supports remote wake-up (including AMD Magic Packet, LinkChg, and
Microsoft wake-up frame) in both ACPI and APM environments. The RTL8139C(L) is capable of performing an internal reset
through the application of auxiliary power. When auxiliary power is on and the main power remains off, the RTL8139C(L) is
ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output
signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8139C(L) LWAKE pin
provides motherboards with the Wake-On-LAN (WOL) function. The RTL8139C(L) also supports Analog Auto-Power-down,
that is, the analog part of the RTL8139C(L) can be shut down temporarily according to user requirements or when the
RTL8139C(L) is in a power down state with the wakeup function disabled. In addition, when the analog part is shut down and
the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and power consumption
of the RTL8139C(L) will be negligible. The RTL8139C(L) also supports an auxiliary power auto-detect function, and will
auto-configure related bits of their own PCI power management registers in PCI configuration space.

The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware (i.e., the
RTL8139C(L) LAN card). The information may consist of part number, serial number, and other detailed information.

To provide cost down support, the RTL8139C(L) is capable of using a 25MHz crystal or OSC as its internal clock source.

The RTL8139C(L) keeps network maintenance costs low and eliminates usage barriers. It is the easiest way to upgrade a
network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at no additional cost.
To improve compatibility with other brands’ products, the RTL8139C(L) is also capable of receiving packets with
InterFrameGap no less than 40 Bit-Time. The RTL8139C(L) is highly integrated and requires no “glue” logic or external
memory. It includes an interface for a boot ROM and can be used in diskless workstations, providing maximum network security
and ease of management.

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3

3. Block Diagram

RTL8139C(L)

PCI

Interface

MII

Interface

PHY

half/full

MAC

10/100

Switch

Logic

Boot ROM

Interface

Power Control Logic

Interrupt

Control

Logic

PCI Interface + Register

FIFO

100M

5B 4B
Decoder

4B 5B
Encoder

EEPROM

Early Interrupt

Threshold

Register

Early Interrupt

Control Logic

Data

Alignment

Interface

FIFO

Control

Logic

Scrambler

LED Driver

Transmit/

Descrambler

Register

Packet Type

Packet Length

Receive

Logic

Interface

Discriminator

MII

Interface

RXD

RXC 25M

TXD

TXC 25M

TXC 25M

TXD

RXC 25M

RXD

Transceiver

Serial to
Parrallel

TXC10
TXD10

RXC10
RXD10

10/100M Auto-negotiation

Control Logic

10M

Manchester coded

waveform

Data Recovery Receive low pass filter

TD+

Variable Current

Comparator

Slave

PLL

3 Level

MLT-3

to NRZI

Parrallel
to Serial

ck

data

Baseline

wander

Correction

Control
Voltage

10M Output waveform

shaping

3 Level

Driver

Peak

Detect

Adaptive

Equalizer

Master

PPL

25M

Link pulse

TXO+
TXO -

RXIN+

RXIN-

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4

4. Pin Assignments

85 GND
86 RXIN­87 RXIN+
88 OEB
89 WEB
90 VDD
91 TXD­92 TXD+

93 GND
94 NC
95 ISOLATEB
96 VDD
97 LED2
98 LED1
99 LED0

100 MD7
101 MD6
102 MD5

RTL8139C(L)

83 LWAKE/CSTSCHG84 RTSET
82 RTT2
81 RTT3

80 GND
79 X1
78 X2

77 VDD

76 PMEB
75 CLKRUNB

74 GND

73 NC

72 NC
71 NC
70 MA16
69 MA15
68 MA14
67 MA13
66 MA12
65 MA11

103 MD4
104 MD3
105 MD2
106 VDD
107 MD1
108 MD0
109 VDD

110 ROMCSB
111 GND
112 GND
113 GND
114 INTAB
115 RSTB
116 CLK
117 GNTB
118 REQB
119 VDD
120 AD31
121 AD30
122 AD29
123 AD28
124 GND
125 AD27
126 AD26
127 AD25
128 AD24

1 VDD
2 CBE3B
3 IDSEL
4 AD23
5 AD22

6 AD21
7 GND
8 AD20

9 AD19
10 AD18
11 AD17
12 VDD
13 AD16
14 CBE2B
15 FRAMEB
16 IRDYB
17 TRDYB
18 GND
19 DEVSELB

RTL8139C(L)

64 MA10
63 MA9
62 GND
61 MA8
60 MA7
59 VDD
58 VDD
57 MA6/9356SEL
56 GND
55 GND
54 NC
53 MA5
52 MA4
51 MA3
50

EECS
49 MA2
48 MA1
47 MA0
46 VDD
45 AD0
44 AD1
43 AD2
42 AD3
41 AD4
40 GND
39 AD5

38 AD6
37 AD7
36 CBE0B
35 VDD
34 AD8
33 AD9
32 AD10
31 AD11
30 GND
29 AD12
28 AD13
27 AD14
26 AD15
25 VDD
24 CBE1B
23 PAR
22 SERRB
21 PERRB
20 STOPB

2002/01/10 Rev.1.4

5

RTL8139C(L)

5. Pin Descriptions

In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.

5.1 Power Management/Isolation Interface

Symbol Type Pin No Description

PMEB
(PME#)

ISOLATEB
(ISOLATE#)

LWAKE/
CSTSCHG

O/D 76

I 95

O 83

Power Management Event: Open drain, active low. Used by the
RTL8139C(L) to request a change in its current power management
state and/or to indicate that a power management event has occurred.

Isolate Pin: Active low. Used to isolate the RTL8139C(L) from the PCI
bus. The RTL8139C(L) does not drive its PCI outputs (excluding
PME#) and does not sample its PCI input (including RST# and
PCICLK) as long as the Isolate pin is asserted.
LAN WAKE-UP Signal (When CardB_En=0, bit2 Config3): This
signal is used to inform the motherboard to execute the wake-up
process. The motherboard must support Wake-On-LAN (WOL). There
are 4 choices of output, including active high, active low, positive pulse,
and negative pulse, that may be asserted from the LWAKE pin. Please
refer to the LWACT bit in the CONFIG1 register and the LWPTN bit in
the CONFIG4 register for the setting of this output signal. The default
output is an active high signal.

Once a PME event is received, the LWAKE and PMEB assert at the
same time when the LWPME (bit4, CONFIG4) is set to 0. If the
LWPME is set to 1, the LWAKE asserts only when the PMEB asserts
and the ISOLATEB is low.

CSTSCHG Signal (When CardB_En=1, bit2 Config3): This signal
is used in CardBus applications only and is used to inform the
motherboard to execute the wake-up process whenever a PME event
occurs. This is always an active high signal, and the setting of LWACT
(bit 4, Config1), LWPTN (bit2, Config4), and LWPME (bit4, Config4)
mean nothing in this case.

This pin is a 3.3V signaling output pin.

5.2 PCI Interface

Symbol Type Pin No Description

AD31-0 T/S 120-123, 125-128, 4-6,

8-11, 13, 26-29, 31-34,

37-39, 41-45
C/BE3-0 T/S 2, 14, 24, 36 PCI bus command and byte enables multiplexed pins.
CLK I 116

CLKRUNB I/O 75

2002/01/10 Rev.1.4

PCI address and data multiplexed pins.

Clock: This PCI Bus clock provides timing for all transactions and bus
phases, and is input to PCI devices. The rising edge defines the start of
each phase. The clock frequency ranges from 0 to 33MHz.
Clock Run: This signal is used by the RTL8139C(L) to request starting
(or speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For the RTL8139C(L), CLKRUNB is an open drain output as
well as an input. The RTL8139C(L) requests the central resource to
start, speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host system
(central resource) is responsible for maintaining CLKRUNB asserted,
and for driving it high to the negated (deasserted) state.

6

DEVSELB S/T/S 19

FRAMEB S/T/S 15

GNTB I 117

REQB T/S 118

IDSEL I 3

INTAB O/D 114

IRDYB S/T/S 16

TRDYB S/T/S 17

PAR T/S 23

RTL8139C(L)

Device Select: As a bus master, the RTL8139C(L) samples this signal

to insure that a PCI target recognizes the destination address for the data
transfer. As a target, the RTL8139C(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted.

Cycle Frame: As a bus master, this pin indicates the beginning and
duration of an access. FRAMEB is asserted low to indicate the start of a
bus transaction. While FRAMEB is asserted, data transfer continues.
When FRAMEB is deasserted, the transaction is in the final data phase.

As a target, the device monitors this signal before decoding the address
to check if the current transaction is addressed to it.

Grant: This signal is asserted low to indicate to the RTL8139C(L) that
the central arbiter has granted ownership of the bus to the
RTL8139C(L). This input is used when the RTL8139C(L) is acting as a
bus master.

Request: The RTL8139C(L) will assert this signal low to request the
ownership of the bus from the central arbiter.

Initialization Device Select: This pin allows the RTL8139C(L) to
identify when configuration read/write transactions are intended for it.

Interrupt A: Used to request an interrupt. It is asserted low when an
interrupt condition occurs, as defined by the Interrupt Status, Interrupt
Mask and Interrupt Enable registers.

Initiator Ready: This indicates the initiating agent’s ability to complete
the current data phase of the transaction.

As a bus master, this signal will be asserted low when the
RTL8139C(L) is ready to complete the current data phase transaction.
This signal is used in conjunction with the TRDYB signal. Data
transaction takes place at the rising edge of CLK when both IRDYB and
TRDYB are asserted low. As a target, this signal indicates that the
master has put data on the bus.

Target Ready: This indicates the target agent’s ability to complete the
current phase of the transaction.

As a bus master, this signal indicates that the target is ready for the data
during write operations and with the data during read operations. As a
target, this signal will be asserted low when the (slave) device is ready
to complete the current data phase transaction. This signal is used in
conjunction with the IRDYB signal. Data transaction takes place at the
rising edge of CLK when both IRDYB and TRDYB are asserted low.

Parity: This signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.

2002/01/10 Rev.1.4

7

PERRB S/T/S 21

SERRB O/D 22

STOPB S/T/S 20

RSTB I 115

Parity Error: When the RTL8139C(L) is the bus master and a parity
error is detected, the RTL8139C(L) asserts both SERR bit in ISR and
Configuration Space command bit 8 (SERRB enable). Next, it
completes the current data burst transaction, then stops operation and
resets itself. After the host clears the system error, the RTL8139C(L)
continues its operation.

When the RTL8139C(L) is the bus target and a parity error is detected,
the RTL8139C(L) asserts this PERRB pin low.

System Error: If an address parity error is detected and Configuration
Space Status register bit 15 (detected parity error) is enabled,
RTL8139C(L) asserts both SERRB pin low and bit 14 of Status register
in Configuration Space.

Stop: Indicates the current target is requesting the master to stop the
current transaction.
Reset: When RSTB is asserted low, the RTL8139C(L) performs an
internal system hardware reset. RSTB must be held for a minimum of
120 ns.

RTL8139C(L)

5.3 FLASH/EEPROM Interface

Symbol Type Pin No Description

MA16-3

MA8

MA6/9356SEL I/O 57 When this pin is pulled high with a 10KΩ resistor, the 93C56 EEPROM

MA2/EESK O 49 The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46

MA1/EEDI O 48
MA0/EEDO O, I 47
EECS O 50 93C46 (93C56) chip select
MD0-7 I/O 108, 107, 105-100 Boot PROM data bus
ROMCSB O 110
OEB O 88

WEB O 89

O

I/O

70-63, 61, 60, 57,

53-51

61

Boot PROM Address Bus: These pins are used to access up to a
128k-byte flash memory or EPROM.

Output pin as part of Boot PROM (or Flash) address bus after PCI reset.

Input pin as Aux. Power detect pin to detect if Aux. Power exists or not,
when initial power-on or PCI reset is asserted. Besides connecting this
pin to Boot PROM, it should be pulled high to the Aux. Power via a
resistor to detect Aux. power. If this pin is not pulled high to Aux.
Power, the RTL8139C(L) assumes that no Aux. power exists. To
support wakeup from ACPI D3cold or APM power-down, this pin must
be pulled high to Aux. power via a resistor.

is used to store the resource data and CIS for the RTL8139C(L). The
RTL8139C(L) latches the status of this pin at power-up to determine
what EEPROM (93C46 or 93C56) is used, afterwards, this pin is used
as MA6.

(93C56) programming or auto-load mode.

ROM Chip Select: This is the chip select signal of the Boot PROM.
Output Enable: This enables the output buffer of the Boot PROM or

Flash memory during a read operation.
Write Enable: This signal strobes data into the Flash memory during a

write cycle.

2002/01/10 Rev.1.4

8

5.4 Power Pins

Symbol Type Pin No Description

VDD P 1, 12, 25, 35, 46, 58,

59, 106, 109, 119
P 77, 90, 96
GND

P 74, 80, 85, 93

P 7, 18, 30, 40, 55, 56,

62, 111, 112, 113, 124

Digital Power +3.3V

Analog Power +3.3V
Digital Ground

Analog Ground

5.5 LED Interface

Symbol Type Pin No Description

LED0, 1, 2 O 99, 98, 97

LED pins

RTL8139C(L)

LEDS1-0 00 01 10 11

LED0
LED1
LED2

During power down mode, the LEDs are OFF.

Tx/Rx Tx/Rx Tx Tx

LINK100 LINK10/100 LINK10/100 LINK100

LINK10 FULL Rx LINK10

5.6 Attachment Unit Interface

Symbol Type Pin No Description

TXD+
TXD­RXIN+
RXIN­X1 I 79
X2 O 78

O
O

92

91
I
I

87

86

100/10BASE-T transmit (Tx) Data

100/10BASE-T receive (Rx) Data

25 MHz Crystal/OSC. Input
Crystal Feedback Output: This output is used in crystal connection

only. It must be left open when X1 is driven with an external 25 MHz
oscillator.

5.7 Test and Other Pins

Symbol Type Pin No Description

RTT2-3 TEST 81, 82 Chip test pins.
RTSET I/O 84

NC - 54, 71, 72, 73, 94

This pin must be pulled low by a 1.7KΩ resistor.

Reserved

2002/01/10 Rev.1.4

9

RTL8139C(L)

6. Register Descriptions

The RTL8139C(L) provides the following set of operational registers mapped into PCI memory space or I/O space.

Offset

0000h R/W IDR0

0001h R/W IDR1
0002h R/W IDR2
0003h R/W IDR3
0004h R/W IDR4
0005h R/W IDR5

0006h-0007h - -

0008h R/W MAR0

0009h R/W MAR1
000Ah R/W MAR2
000Bh R/W MAR3
000Ch R/W MAR4
000Dh R/W MAR5
000Eh R/W MAR6

000Fh R/W MAR7
0010h-0013h R/W TSD0
0014h-0017h R/W TSD1

0018h-001Bh R/W TSD2
001Ch-001Fh R/W TSD3

0020h-0023h R/W TSAD0
0024h-0027h R/W TSAD1

0028h-002Bh R/W TSAD2
002Ch-002Fh R/W TSAD3

0030h-0033h R/W RBSTART
0034h-0035h R ERBCR

0036h R ERSR

0037h R/W CR
0038h-0039h R/W CAPR

003Ah-003Bh R CBR

003Ch-003Dh R/W IMR

003Eh-003Fh R/W ISR

0040h-0043h R/W TCR
0044h-0047h R/W RCR

0048h-004Bh R/W TCTR

004Ch-004Fh R/W MPC

0050h R/W 9346CR

0051h R/W CONFIG0

0052h R/W CONFIG1

R/W Tag Description

ID Register 0: The ID registers 0-5 are only permitted to read/write

by 4-byte access. Read access can be byte, word, or double word
access. The initial value is autoloaded from the EEPROM EthernetID
field.

ID Register 1
ID Register 2
ID Register 3

ID Register 4

ID Register 5
Reserved
Multicast Register 0: The MAR registers 0-7 are only permitted to

read/write by 4-byte access. Read access can be byte, word, or double
word access. Driver is responsible for initializing these registers.

Multicast Register 1
Multicast Register 2
Multicast Register 3
Multicast Register 4
Multicast Register 5
Multicast Register 6
Multicast Register 7
Transmit Status of Descriptor 0
Transmit Status of Descriptor 1
Transmit Status of Descriptor 2
Transmit Status of Descriptor 3
Transmit Start Address of Descriptor0
Transmit Start Address of Descriptor1
Transmit Start Address of Descriptor2
Transmit Start Address of Descriptor3
Receive (Rx) Buffer Start Address
Early Receive (Rx) Byte Count Register
Early Rx Status Register
Command Register
Current Address of Packet Read (The initial value is 0FFF0h)
Current Buffer Address: The initial value is 0000h. It reflects total

received byte-count in the rx buffer.

Interrupt Mask Register
Interrupt Status Register
Transmit (Tx) Configuration Register
Receive (Rx) Configuration Register
Timer Count Register: This register contains a 32-bit

general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin to count from zero.

Missed Packet Counter: Indicates the number of packets discarded
due to rx FIFO overflow. It is a 24-bit counter. After s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written, MPC will be reset also.

93C46 (93C56) Command Register
Configuration Register 0
Configuration Register 1

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10

RTL8139C(L)

0053H - ­0054h-0057h

0058h R/W MSR

0059h R/W CONFIG3

005Ah R/W CONFIG4

005Bh - -

005Ch-005Dh R/W MULINT

005Eh R RERID

005Fh - ­0060h-0061h R TSAD
0062h-0063h R/W BMCR
0064h-0065h R BMSR
0066h-0067h R/W ANAR
0068h-0069h R ANLPAR

006Ah-006Bh R ANER
006Ch-006Dh R DIS

006Eh-006Fh R FCSC

0070h-0071h R/W NWAYTR
0072h-0073h R REC
0074h-0075h R/W CSCR

0076-0077h - ­0078h-007Bh R/W PHY1_PARM
007Ch-007Fh R/W TW_PARM

0080h R/W PHY2_PARM

0081-0083h - -

0084h R/W CRC0

0085h R/W CRC1

0086h R/W CRC2
0087h

0088h R/W CRC4
0089h R/W CRC5
008Ah R/W CRC6

008Bh R/W CRC7
008Ch–0093h R/W Wakeup0
0094h–009Bh R/W Wakeup1

009Ch–00A3h R/W Wakeup2
00A4h–00ABh R/W Wakeup3
00ACh–00B3h R/W Wakeup4
00B4h–00BBh R/W Wakeup5
00BCh–00C3h R/W Wakeup6
00C4h–00CBh R/W Wakeup7

00CCh R/W LSBCRC0
00CDh R/W LSBCRC1
00CEh R/W LSBCRC2
00CFh R/W LSBCRC3
00D0h R/W LSBCRC4
00D1h R/W LSBCRC5
00D2h R/W LSBCRC6
00D3h R/W LSBCRC7

00D4h-00D7h R/W FLASH

R /W

R/W

TimerInt

CRC3

Reserved
Timer Interrupt Register: Once having written a nonzero value to

this register, the Timeout bit of ISR register will be set whenever the
TCTR reaches to this value. The Timeout bit will never be set as long
as TimerInt register is zero.

Media Status Register
Configuration register 3
Configuration register 4
Reserved
Multiple Interrupt Select
PCI Revision ID = 10h
Reserved
Transmit Status of All Descriptors
Basic Mode Control Register
Basic Mode Status Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Register
Auto-Negotiation Expansion Register
Disconnect Counter
False Carrier Sense Counter
N-way Test Register
RX_ER Counter
CS Configuration Register
Reserved
PHY parameter 1
Twister parameter
PHY parameter 2
Reserved

Power Management CRC Register0 for Wakeup Frame0

Power Management CRC Register1 for Wakeup Frame1

Power Management CRC Register2 for Wakeup Frame2

Power Management CRC Register3 for Wakeup Frame3

Power Management CRC Register4 for Wakeup Frame4
Power Management CRC Register5 for Wakeup Frame5
Power Management CRC Register6 for Wakeup Frame6
Power Management CRC Register7 for Wakeup Frame7
Power Management Wakeup Frame0 (64bit)
Power Management Wakeup Frame1 (64bit)
Power Management Wakeup Frame2 (64bit)
Power Management Wakeup Frame3 (64bit)
Power Management Wakeup Frame4 (64bit)
Power Management Wakeup Frame5 (64bit)
Power Management Wakeup Frame6 (64bit)
Power Management Wakeup Frame7 (64bit)
LSB of the Mask byte of Wakeup Frame0 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame1 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame2 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame3 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame4 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame5 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame6 Within Offset 12 to 75
LSB of the Mask byte of Wakeup Frame7 Within Offset 12 to 75
Flash Memory Read/Write Register

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RTL8139C(L)

00D8h R/W Config5

00D9h-00EFh - -

00F0h-00F3h R/W FER

00F4h-00F7h R/W FEMR
00F8h-00FBh R FPSR
00FCh-00FFh W FFER

Configuration Register 5
Reserved
Function Event Register (Cardbus only)
Function Event Mask Register (CardBus only)
Function Present State Register (CardBus only)
Function Force Event Register (CardBus only)

6.1 Receive Status Register in Rx packet header

Bit R/W Symbol Description

15 R MAR

14 R PAM

13 R BAR

12-6 - -

5 R ISE

4 R RUNT

3 R LONG

2 R CRC

1 R FAE

0 R ROK

Multicast Address Received: This bit set to 1 indicates that a multicast
packet is received.

Physical Address Matched: This bit set to 1 indicates that the destination
address of this packet matches the value written in ID registers.

Broadcast Address Received: This bit set to 1 indicates that a broadcast
packet is received. BAR, MAR bit will not be set simultaneously.

Reserved
Invalid Symbol Error: (100BASE-TX only) This bit set to 1 indicates

that an invalid symbol was encountered during the reception of this packet.
Runt Packet Received: This bit set to 1 indicates that the received packet

length is smaller than 64 bytes ( i.e. media header + data + CRC < 64
bytes )

Long Packet: This bit set to 1 indicates that the size of the received
packet exceeds 4k bytes.

CRC Error: When set, indicates that a CRC error occurred on the
received packet.

Frame Alignment Error: When set, indicates that a frame alignment
error occurred on this received packet.

Receive OK: When set, indicates that a good packet is received.

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RTL8139C(L)

6.2 Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)

The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139C(L) when the Transmit
Byte Count (bit12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These
registers are only permitted to write by double-word access. After a software reset, all bits except the OWN bit are reset to “0”.

Bit R/W Symbol Description

31 R CRS

30 R TABT

29 R OWC

28 R CDH

27-24 R NCC3-0

23-22 - ­21-16 R/W ERTXTH5-0

15 R TOK

14 R TUN

13 R/W OWN

12-0 R/W SIZE

Carrier Sense Lost: This bit is set to 1 when the carrier is lost during
transmission of a packet.

Transmit Abort: This bit is set to 1 if the transmission of a packet was
aborted. This bit is read only, writing to this bit is not affected.

Out of Window Collision: This bit is set to 1 if the RTL8139C(L)
encountered an "out of window" collision during the transmission of a
packet.

CD Heart Beat: The same as RTL8139(A/B).
This bit is cleared in the 100 Mbps mode.

Number of Collision Count: Indicates the number of collisions
encountered during the transmission of a packet.

Reserved
Early Tx Threshold: Specifies the threshold level in the Tx FIFO to

begin the transmission. When the byte count of the data in the Tx FIFO
reaches this level, (or the FIFO contains at least one complete packet)
the RTL8139C(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must be avoided from exceeding 2K byte.

Transmit OK: Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun occurs.

Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted
during the transmission of a packet. The RTL8139C(L) can re-transfer
data if the Tx FIFO underruns and can also transmit the packet to the
wire successfully even though the Tx FIFO underruns. That is, when
TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).
OWN: The RTL8139C(L) sets this bit to 1 when the Tx DMA
operation of this descriptor was completed. The driver must set this bit
to 0 when the Transmit Byte Count (bit0-12) is written. The default
value is 1.

Descriptor Size: The total size in bytes of the data in this descriptor. If
the packet length is more than 1792 byte (0700h), the Tx queue will be
invalid, i.e. the next descriptor will be written only after the OWN bit of
that long packet's descriptor has been set.

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6.3 ERSR: Early Rx Status Register
(Offset 0036h, R)

Bit R/W Symbol Description

7-4 - -

3 R ERGood

2 R ERBad

1 R EROVW

0 R EROK

Reserved
Early Rx Good packet: This bit is set whenever a packet is completely

received and the packet is good. This bit is cleared when writing 1 to it,
Early Rx Bad packet: This bit is set whenever a packet is completely

received and the packet is bad. Writing 1 will clear this bit.
Early Rx OverWrite: This bit is set when the RTL8139C(L)'s local

address pointer is equal to CAPR. In the early mode, this is different
from buffer overflow. It happens that the RTL8139C(L) detected an Rx
error and wanted to fill another packet data from the beginning address
of that error packet. Writing 1 will clear this bit.
Early Rx OK: The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8139C(L) will set ROK or RER in ISR and clear
this bit simultaneously. Setting this bit will invoke a ROK interrupt.

RTL8139C(L)

6.4 Command Register
(Offset 0037h, R/W)

This register is used for issuing commands to the RTL8139C(L). These commands are issued by setting the corresponding bits for
the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.

Bit R/W Symbol Description

7-5 - -

4 R/W RST

3 R/W RE

2 R/W TE

1 - ­0 R BUFE

Reserved
Reset: Setting to 1 forces the RTL8139C(L) to a software reset state

which disables the transmitter and receiver, reinitializes the FIFOs,
resets the system buffer pointer to the initial value (Tx buffer is at
TSAD0, Rx buffer is empty). The values of IDR0-5 and MAR0-7 and
PCI configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8139C(L) when the reset
operation is complete.

Receiver Enable: When set to 1, and the receive state machine is idle,
the receive machine becomes active. This bit will read back as a 1
whenever the receive state machine is active. After initial power-up,
software must insure that the receiver has completely reset before
setting this bit.

Transmitter Enable: When set to 1, and the transmit state machine is
idle, then the transmit state machine becomes active. This bit will read
back as a 1 whenever the transmit state machine is active. After initial
power-up, software must insure that the transmitter has completely reset
before setting this bit.

Reserved
Buffer Empty: The Rx buffer is empty; There is no packet stored in the

Rx buffer ring.

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RTL8139C(L)

6.5 Interrupt Mask Register
(Offset 003Ch-003Dh, R/W)

This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt.
During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt.
ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit.

Bit R/W Symbol Description

15 R/W SERR

14 R/W TimeOut
13 R/W LenChg

12-7 - -

6 R/W FOVW
5 R/W PUN/LinkChg

4 R/W RXOVW
3 R/W TER
2 R/W TOK
1 R/W RER
0 R/W ROK

System Error Interrupt: 1 => Enable, 0 => Disable.

Time Out Interrupt: 1 => Enable, 0 => Disable.
Cable Length Change Interrupt: 1 => Enable, 0 => Disable.
Reserved
Rx FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.
Packet Underrun/Link Change Interrupt: 1 => Enable, 0 =>

Disable.

Rx Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.
Transmit Error Interrupt: 1 => Enable, 0 => Disable.
Transmit OK Interrupt: 1 => Enable, 0 => Disable.
Receive Error Interrupt: 1 => Enable, 0 => Disable.
Receive OK Interrupt: 1 => Enable, 0 => Disable.

6.6 Interrupt Status Register
(Offset 003Eh-003Fh, R/W)

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt
Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this
register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the
corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.

Bit R/W Symbol Description

15 R/W SERR

14 R/W TimeOut

13 R/W LenChg

12 - 7 - -

6 R/W FOVW
5 R/W PUN/LinkChg

4 R/W RXOVW

3 R/W TER

2 R/W TOK

1 R/W RER

0 R/W ROK

System Error: Set to 1 when the RTL8139C(L) signals a system error
on the PCI bus.

Time Out: Set to 1 when the TCTR register reaches to the value of the
TimerInt register.

Cable Length Change: Cable length is changed after Receiver is
enabled.

Reserved
Rx FIFO Overflow: Set when an overflow occurs on the Rx status FIFO.
Packet Underrun/Link Change: Set to 1 when CAPR is written but

Rx buffer is empty, or when link status is changed.
Rx Buffer Overflow: Set when receive (Rx) buffer ring storage

resources have been exhausted.
Transmit (Tx) Error: Indicates that a packet transmission was

aborted, due to excessive collisions, according to the TXRR's setting
Transmit (Tx) OK: Indicates that a packet transmission is completed

successfully.
Receive (Rx) Error: Indicates that a packet has either CRC error or

frame alignment error (FAE). The collided frame will not be recognized
as CRC error if the length of this frame is shorter than 16 byte.

Receive (Rx) OK: In normal mode, indicates the successful completion
of a packet reception. In early mode, indicates that the Rx byte count of
the arriving packet exceeds the early Rx threshold.

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RTL8139C(L)

6.7 Transmit Configuration Register
(Offset 0040h-0043h, R/W)

This register defines the Transmit Configuration for the RTL8139C(L). It controls such functions as Loopback, Heartbeat, Auto
Transmit Padding, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size.

Bit R/W Symbol Description

31 - -

30-26 R HWVERID

25-24 R/W IFG1, 0

23 R 8139A-G RTL8139A rev.G ID = 1. For others, this bit is 0.

22-19 - -

18, 17 R/W LBK1, LBK0

16 R/W CRC

15-11 - -

10-8 R/W MXDMA2, 1, 0

Reserved
Hardware Version ID:

Bit30 Bit29 Bit28 Bit27 Bit26 Bit23

RTL8139 1 1 0 0 0 0

RTL8139A 1 1 1 0 0 0

RTL8139A-G 1 1 1 0 0 1

RTL8139B 1 1 1 1 0 0

RTL8130 1 1 1 1 1 0

RTL8139C 1 1 1 0 1 0

Reserved All other combination

Interframe Gap Time: This field allows adjustment of the interframe
gap time below the standards of 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.

The formula for the inter frame gap is:
10 Mbps 8.4us + 0.4(IFG(1:0)) us
100 Mbps 840ns + 40(IFG(1:0)) ns

Reserved
Loopback test: There will be no packet on the TX+/- lines under the

Loopback test condition. The loopback function must be independent of
the link state.

00: normal operation
01: Reserved
10: Reserved
11: Loopback mode

Append CRC:
0: A CRC is appended at the end of a packet
1: No CRC appended at the end of a packet

Reserved
Max DMA Burst Size per Tx DMA Burst: This field sets the

maximum size of transmit DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes

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g

7-4 R/W TXRR

3-1 - -

0 W CLRABT

Tx Retry Count: These are used to specify additional transmission
retries in multiples of 16 (IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit 16 times before
aborting due to excessive collisions. If the TXRR is set to a value
greater than 0, the transmitter will re-transmit a number of times equal
to the following formula before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set when
the transmission fails and reaches to this specified retry count.

Reserved
Clear Abort: Setting this bit to 1 causes the RTL8139C(L) to

retransmit the packet at the last transmitted descriptor when this
transmission was aborted. Setting this bit is only permitted in the
transmit abort state.

6.8 Receive Configuration Register

RTL8139C(L)

(Offset 0044h-0047h, R/W)

This register is used to set the receive configuration for the RTL8139C(L). Receive properties such as accepting error packets,
runt packets, setting the receive drain threshold etc. are controlled here.

Bit R/W Symbol Description
31-28 - ­27-24 R/W ERTH3, 2, 1, 0

23-18 - -

17 R/W MulERINT

16 R/W RER8 The RTL8139C(L) receives the error packet whose length is larger than

15-13 R/W RXFTH2, 1, 0

Reserved
Early Rx threshold bits: These bits are used to select the Rx threshold

multiplier of the whole packet that has been transferred to the system
buffer in early mode when the frame protocol is under the
RTL8139C(L)'s definition.
0000 = no early rx threshold 0001 = 1/16
0010 = 2/16 0011 = 3/16
0100 = 4/16 0101 = 5/16
0110 = 6/16 0111 = 7/16
1000 = 8/16 1001 = 9/16
1010 = 10/16 1011 = 11/16
1100 = 12/16 1101 = 13/16
1110 = 14/16 1111 = 15/16

Reserved
Multiple early interrupt select: When this bit is set, any received

packet invokes early interrupt according to MULINT<MISR[11:0]>
setting in early mode. When this bit is reset, the packets of familiar
protocol (IPX, IP, NDIS, etc) invoke early interrupt according to
RCR<ERTH[3:0]> setting in early mode. The packets of unfamiliar
protocol will invoke early interrupt according to the setting of
MULINT<MISR[11:0]>.

8 bytes after setting the RER8 bit to 1.
The RTL8139C(L) receives the error packet larger than 64-byte long
when the RER8 bit is cleared. The power-on default is zero.
If AER or AR is set, the RER will be set when the RTL8139C(L)
receives an error packet whose length is larger than 8 bytes. The RER8
is “ Don’t care “ in this situation.

Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the
number of the received data bytes from a packet, which is being
received into the RTL8139C(L)'s Rx FIFO, has reached to this level (or
the FIFO has contained a complete packet), the receive PCI bus master
function will be

in to transfer the data from the FIFO to the host

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12-11 R/W RBLEN1, 0

10-8 R/W MXDMA2, 1, 0

7 R/W WRAP 0: The RTL8139C(L) will transfer the rest of the packet data into the

6 R 9356SEL

5 R/W AER

4 R/W AR

3 R/W AB

RTL8139C(L)

memory. This field sets the threshold level according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = no rx threshold. The RTL8139C(L) begins the transfer of data
after having received a whole packet in the FIFO.
Rx Buffer Length: This field indicates the size of the Rx ring buffer.
00 = 8k + 16 byte
01 = 16k + 16 byte
10 = 32K + 16 byte
11 = 64K + 16 byte

Max DMA Burst Size per Rx DMA Burst: This field sets the
maximum size of the receive DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = unlimited

beginning of the Rx buffer if this packet has not been completely
moved into the Rx buffer and the transfer has arrived at the end of
the Rx buffer.

1: The RTL8139C(L) will keep moving the rest of the packet data into the

memory immediately after the end of the Rx buffer, if this packet has
not been completely moved into the Rx buffer and the transfer has
arrived at the end of the Rx buffer. The software driver must reserve at
least 1.5K bytes buffer to accept the remainder of the packet. We
assume that the remainder of the packet is X bytes. The next packet will
be moved into the memory from the X byte offset at the top of the Rx
buffer.

This bit is invalid when Rx buffer is selected to 64K bytes.
EEPROM Select: This bit reflects what type of EEPROM is used.

1: The EEPROM used is 9356.
0: The EEPROM used is 9346.

Accept Error Packets: This bit determines if packets with CRC error,
alignment error and/or collided fragments will be accepted or rejected.
0: Reject error packets
1: Accept error packets

Accept Runt Packets: This bit allows the receiver to accept packets
that are smaller than 64 bytes. The packet must be at least 8 bytes long to
be accepted as a runt.
0: Reject runt packets
1: Accept runt packets

Accept Broadcast Packets: This bit allows the receiver to accept or
reject broadcast packets.
0: Reject broadcast packets
1: Accept broadcast packets

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RTL8139C(L)

2 R/W AM

Accept Multicast Packets: This bit allows the receiver to accept or
reject multicast packets.
0: Reject multicast packets
1: Accept multicast packets

1 R/W APM

Accept Physical Match Packets: This bit allows the receiver to accept
or reject physical match packets.
0: Reject physical match packets
1: Accept physical match packets

0 R/W AAP

Accept Physical Address Packets: This bit allows the receiver to
accept or reject packets with a physical destination address.
0: Reject packets with a physical destination address
1: Accept packets with a physical destination address

6.9 9346CR: 93C46 (93C56) Command Register
(Offset 0050h, R/W)

Bit R/W Symbol Description

7-6 R/W EEM1-0

4-5 - -

3 R/W EECS
2 R/W EESK
1 R/W EEDI
0 R EEDO

Operating Mode: These 2 bits select the RTL8139C(L) operating mode.

EEM1 EEM0 Operating Mode

0 0 Normal (RTL8139C(L) network/host communication

mode)

0 1 Auto-load: Entering this mode will make the

RTL8139C(L) load the contents of 93C46 (93C56) as
when the RSTB signal is asserted. This auto-load
operation will take about 2 ms. After it is completed, the
RTL8139C(L) goes back to the normal mode
automatically (EEM1 = EEM0 = 0) and all the other
registers are reset to default values.

1 0 93C46 (93C56) programming: In this mode, both network

and host bus master operations are disabled. The 93C46
(93C56) can be directly accessed via bit3-0 which now
reflect the states of EECS, EESK, EEDI, & EEDO pins
respectively.

1 1 Config register write enable: Before writing to CONFIG0,

1, 3, 4 registers, and bit13, 12, 8 of BMCR(offset
62h-63h), the RTL8139C(L) must be placed in this mode.
This will prevent RTL8139C(L)'s configurations from
accidental change.

Reserved

These bits reflect the state of EECS, EESK, EEDI & EEDO pins in
auto-load or 93C46 (93C56) programming mode and are valid only
when Flash bit is cleared.
Note: EESK, EEDI and EEDO is valid after boot ROM complete.

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