Realtek RTL8111D-GR, RTL8111DL-GR, RTL8111DL-VB-GR, RTL8111D-VB-GR Schematic [ru]
RTL8111D-GR
RTL8111DL-GR
RTL8111D-VB-GR
RTL8111DL-VB-GR
INTEGRATED GIGABIT ETHERNET CONTROLLER
FOR PCI EXPRESS APPLICATIONS
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.6
10 March 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8111D(L)/RTL8111D(L)-VB
6
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
Datasheet
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2008/05/13 First release.
1.1 2008/07/03 Revised section 6.2.6, page 12.
Added section 9.2, page 38.
Added section 9.3, page 39.
1.2 2008/07/29 Updated licensing information.
1.3 2008/08/08 Added Deep Slumber Mode (DSM) power saving to features list on page 2.
1.4 2008/08/29 Revised Figure 2, page 4 (Pin23).
1.5 2009/01/07 Switching regulator output revised from 1.2V to 1.05V.
Revised Table 19 Crystal Requirements, page 28, Drive Level value.
1.6 2009/03/10 Added RTL8111D-VB-GR & RTL8111DL-VB-GR product numbers.
Added Deep Slumber Mode (DSM) V2 Feature on page 2.
Added section 6.2.6 Deep Slumber Mode (DSM) V1 & V2, page 12.
Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.
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Datasheet
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
2. FEATURES.........................................................................................................................................................................2
3. SYSTEM APPLICATIONS...............................................................................................................................................2
4. PIN ASSIGNMENTS .........................................................................................................................................................3
4.1. RTL8111D & RTL8111D-VB (64-PIN QFN) .............................................................................................................3
4.2. PACKAGE IDENTIFICATION...........................................................................................................................................3
4.3. RTL8111DL & RTL8111DL-VB (48-PIN LQFP).......................................................................................................4
4.4. PACKAGE IDENTIFICATION...........................................................................................................................................4
5. PIN DESCRIPTIONS.........................................................................................................................................................5
5.1. POWER MANAGEMENT/ISOLATION ..............................................................................................................................5
5.2. PCI EXPRESS INTERFACE .............................................................................................................................................5
5.3. TRANSCEIVER INTERFACE............................................................................................................................................6
5.4. CLOCK .........................................................................................................................................................................6
5.5. REGULATOR AND REFERENCE......................................................................................................................................6
5.6. EEPROM ....................................................................................................................................................................7
5.7. LEDS ...........................................................................................................................................................................7
5.8. POWER AND GROUND ..................................................................................................................................................8
5.9. GPIO PINS ...................................................................................................................................................................8
5.10. TEST PINS ....................................................................................................................................................................8
5.11. NC PINS .......................................................................................................................................................................8
6. FUNCTIONAL DESCRIPTION.......................................................................................................................................9
6.1. PCI EXPRESS BUS INTERFACE......................................................................................................................................9
6.1.1. PCI Express Transmitter ........................................................................................................................................9
6.1.2. PCI Express Receiver.............................................................................................................................................9
6.2. LED FUNCTIONS..........................................................................................................................................................9
6.2.1. Link Monitor...........................................................................................................................................................9
6.2.2. Rx LED .................................................................................................................................................................10
6.2.3. Tx LED .................................................................................................................................................................10
6.2.4. Tx/Rx LED ............................................................................................................................................................11
6.2.5. LINK/ACT LED ....................................................................................................................................................11
6.2.6. Deep Slumber Mode (DSM) V1 & V2...................................................................................................................12
6.2.7. Customizable LED Configuration ........................................................................................................................12
6.3. PHY TRANSCEIVER ...................................................................................................................................................13
6.3.1. PHY Transmitter...................................................................................................................................................13
6.3.2. PHY Receiver .......................................................................................................................................................13
6.4. NEXT PAGE ................................................................................................................................................................14
6.5. EEPROM INTERFACE ................................................................................................................................................14
6.6. POWER MANAGEMENT...............................................................................................................................................15
6.7. VITAL PRODUCT DATA (VPD)...................................................................................................................................17
6.8. RECEIVE-SIDE SCALING (RSS) ..................................................................................................................................18
6.8.1. Receive-Side Scaling (RSS) Initialization.............................................................................................................18
6.8.2. RSS Operation ......................................................................................................................................................19
7. SWITCHING REGULATOR..........................................................................................................................................19
7.1. PCB LAYOUT.............................................................................................................................................................19
7.2. INDUCTOR AND CAPACITOR PARTS LIST ....................................................................................................................20
7.3. MEASUREMENT CRITERIA..........................................................................................................................................21
7.4. TYPICAL SWITCHING REGULATOR PCB LAYOUT ......................................................................................................25
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7.5. EFFICIENCY MEASUREMENT ......................................................................................................................................26
7.6. POWER SEQUENCE .....................................................................................................................................................27
8. CHARACTERISTICS......................................................................................................................................................28
8.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................28
8.2. RECOMMENDED OPERATING CONDITIONS .................................................................................................................28
8.3. CRYSTAL REQUIREMENTS..........................................................................................................................................28
8.4. OSCILLATOR REQUIREMENTS ....................................................................................................................................29
8.5. THERMAL CHARACTERISTICS.....................................................................................................................................29
8.6. DC CHARACTERISTICS...............................................................................................................................................29
8.7. AC CHARACTERISTICS...............................................................................................................................................30
8.7.1. Serial EEPROM Interface Timing........................................................................................................................30
8.8. PCI EXPRESS BUS PARAMETERS................................................................................................................................31
8.8.1. Differential Transmitter Parameters....................................................................................................................31
8.8.2. Differential Receiver Parameters.........................................................................................................................32
8.8.3. REFCLK Parameters............................................................................................................................................32
8.8.4. Auxiliary Signal Timing Parameters ....................................................................................................................36
9. MECHANICAL DIMENSIONS......................................................................................................................................37
9.1. RTL8111D & RTL8111D-VB (64-PIN QFN) ...........................................................................................................37
9.2. RTL8111DL & RTL8111DL-VB (48-PIN LQFP).....................................................................................................38
9.3. MECHANICAL DIMENSIONS NOTES (RTL8111DL/RTL8111DL-VB 48-PIN)............................................................39
Datasheet
10. ORDERING INFORMATION...................................................................................................................................40
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Datasheet
List of Tables
TABLE 1. POWER MANAGEMENT/ISOLATION ...............................................................................................................................5
TABLE 2. PCI EXPRESS INTERFACE..............................................................................................................................................5
TABLE 3. TRANSCEIVER INTERFACE ............................................................................................................................................6
TABLE 4. CLOCK ..........................................................................................................................................................................6
TABLE 5. REGULATOR AND REFERENCE ......................................................................................................................................6
TABLE 6. EEPROM .....................................................................................................................................................................7
TABLE 7. LEDS............................................................................................................................................................................7
TABLE 8. POWER AND GROUND ...................................................................................................................................................8
TABLE 9. GPIO PINS ....................................................................................................................................................................8
TABLE 10. TEST PINS ....................................................................................................................................................................8
TABLE 11. NC PINS .......................................................................................................................................................................8
TABLE 12. LED SELECT (IO REGISTER OFFSET 18H~19H)..........................................................................................................12
TABLE 13. CUSTOMIZED LEDS ...................................................................................................................................................12
TABLE 14. EEPROM INTERFACE ................................................................................................................................................14
TABLE 15. INDUCTOR AND CAPACITOR PARTS LIST ....................................................................................................................20
TABLE 16. POWER SEQUENCE PARAMETER .................................................................................................................................27
TABLE 17. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................28
TABLE 18. RECOMMENDED OPERATING CONDITIONS .................................................................................................................28
TABLE 19. CRYSTAL REQUIREMENTS..........................................................................................................................................28
TABLE 20. OSCILLATOR REQUIREMENTS ....................................................................................................................................29
TABLE 21. THERMAL CHARACTERISTICS.....................................................................................................................................29
TABLE 22. DC CHARACTERISTICS ...............................................................................................................................................29
TABLE 23. EEPROM ACCESS TIMING PARAMETERS ..................................................................................................................30
TABLE 24. DIFFERENTIAL TRANSMITTER PARAMETERS ..............................................................................................................31
TABLE 25. DIFFERENTIAL RECEIVER PARAMETERS.....................................................................................................................32
TABLE 26. REFCLK PARAMETERS .............................................................................................................................................32
TABLE 27. AUXILIARY SIGNAL TIMING PARAMETERS.................................................................................................................36
TABLE 28. ORDERING INFORMATION ..........................................................................................................................................40
Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.
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Datasheet
List of Figures
FIGURE 1. RTL8111D & RTL8111D-VB (64-PIN QFN) PIN ASSIGNMENTS ...............................................................................3
FIGURE 2. RTL8111DL & RTL8111DL-VB (48-PIN LQFP) PIN ASSIGNMENTS ........................................................................4
FIGURE 3. RX LED.....................................................................................................................................................................10
FIGURE 4. TX LED.....................................................................................................................................................................10
FIGURE 5. TX/RX LED...............................................................................................................................................................11
FIGURE 6. LINK/ACT LED .......................................................................................................................................................11
FIGURE 7. SWITCHING REGULATOR ILLUSTRATION ...................................................................................................................19
FIGURE 8. INPUT VOLTAGE OVERSHOOT <4V (GOOD)...............................................................................................................21
FIGURE 9. INPUT VOLTAGE OVERSHOOT >4V (BAD) .................................................................................................................21
FIGURE 10. CERAMIC 22µF 1210 (X5R) (GOOD).........................................................................................................................22
FIGURE 11. CERAMIC 22µF 0805 (Y5V) (BAD) ...........................................................................................................................22
FIGURE 12. ELECTROLYTIC 100µF (RIPPLE TOO HIGH)...............................................................................................................23
FIGURE 13. 4R7GTSD32 (GOOD) ...............................................................................................................................................24
FIGURE 14. 1µH BEAD (BAD) ......................................................................................................................................................24
FIGURE 15. TYPICAL SWITCHING REGULATOR PCB LAYOUT (TOP LAYER)................................................................................25
FIGURE 16. TYPICAL SWITCHING REGULATOR PCB LAYOUT (BOTTOM LAYER) ........................................................................25
FIGURE 17. SWITCHING REGULATOR EFFICIENCY MEASUREMENT CHECKPOINT........................................................................26
FIGURE 18. POWER SEQUENCE ....................................................................................................................................................27
FIGURE 19. SERIAL EEPROM INTERFACE TIMING......................................................................................................................30
FIGURE 20. SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING .................................................34
FIGURE 21. SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT ..........................................................................34
FIGURE 22. SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING .......................................................34
FIGURE 23. DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD ...................................................................35
FIGURE 24. DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME ...........................................................................35
FIGURE 25. DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK............................................................................................35
FIGURE 26. REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .........................................................................36
FIGURE 27. AUXILIARY SIGNAL TIMING......................................................................................................................................36
Integrated Gigabit Ethernet Controller for PCI Express vi Track ID: JATR-1076-21 Rev. 1.
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Datasheet
1. General Description
The Realtek RTL8111D(L)/RTL8111D(L)-VB Gigabit Ethernet controllers combine a triple-speed IEEE
802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express
bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal
technology, the RTL8111D(L)/RTL8111D(L)-VB offers high-speed transmission over CAT 5 UTP cable
or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction,
polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and
error correction are implemented to provide robust transmission and reception capability at high speeds.
The RTL8111D(L)/RTL8111D(L)-VB complies with the IEEE 802.3u specification for 10/100Mbps
Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power
auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI
configuration space.
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. PCI MSI (Message Signaled
Interrupt) and MSI-X are also supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft®
Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To
support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary
exists), the auxiliary power source must be able to provide the needed power for the
RTL8111D(L)/RTL8111D(L)-VB.
The RTL8111D(L)/RTL8111D(L)-VB is fully compliant with Microsoft
TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and
supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network
(VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance
when in operation on a network server.
The RTL8111D(L)/RTL8111D(L)-VB supports Receive Side Scaling (RSS) to hash incoming TCP
connections and load-balance received data processing across multiple CPUs. RSS improves the number
of transactions per second and number of connections per second, for increased network throughput.
The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin
count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure. The device
embeds an adaptive equalizer in the PCIe PHY for ease of system integration and excellent link quality.
The equalizer enables the length of the PCB traces to reach 40 inches.
The RTL8111D(L)/RTL8111D(L)-VB is suitable for multiple market segments and emerging
applications, such as desktop, mobile, workstation, server, communications platforms, and embedded
applications.
®
NDIS5, NDIS6(IPv4, IPv6,
The RTL8111D(L)/RTL8111D(L)-VB supports the Deep Slumber Mode (DSM) power saving feature.
See the separate DSM application notes for details.
Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.
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2. Features
RTL8111D(L)/RTL8111D(L)-VB
Datasheet
Integrated 10/100/1000 transceiver
Auto-Negotiation with Next Page capability
Supports PCI Express 1.1
Supports pair swap/polarity/skew correction
Crossover Detection & Auto-Correction
Wake-on-LAN and remote wake-up support
Microsoft
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send v1
and Large send v2) support
Supports Full Duplex flow control (IEEE
802.3x)
Supports jumbo frame to 9K bytes
Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
®
NDIS5, NDIS6 Checksum
Serial EEPROM
Transmit/Receive on-chip buffer support
Supports power down/link down power
saving
Built-in Switching regulator
Supports PCI MSI (Message Signaled
Interrupt) and MSI-X
Supports quad core Receive-Side Scaling
(RSS)
Embeds an adaptive equalizer in PCI
express PHY (PCB traces to reach 40
inches)
Supports Deep Slumber Mode (DSM) power
saving V1/V2 features (V2 for
RTL8111D(L)-VB only)
Customized LEDs
Supports IEEE 802.1P Layer 2 Priority
Encoding
Supports IEEE 802.1Q VLAN tagging
Embedded OTP memory can replace the
external EEPROM
Packages
64-pin QFN ‘Green’ package
(RTL8111D & RTL8111D-VB)
48-pin LQFP ‘Green’ package
(RTL8111DL & RTL8111DL-VB)
3. System Applications
PCI Express Gigabit Ethernet on Motherboard, Notebook, or Embedded system
Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.
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4. Pin Assignments
4.1. RTL8111D & RTL8111D-VB (64-Pin QFN)
Datasheet
Figure 1. RTL8111D & RTL8111D-VB (64-Pin QFN) Pin Assignments
4.2. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
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RTL8111D(L)/RTL8111D(L)-VB
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4.3. RTL8111DL & RTL8111DL-VB (48-Pin LQFP)
Datasheet
Figure 2. RTL8111DL & RTL8111DL-VB (48-Pin LQFP) Pin Assignments
4.4. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
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5. Pin Descriptions
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin P: Power
5.1. Power Management/Isolation
Table 1. Power Management/Isolation
Symbol Type Pin No
(64-pin)
LANWAKEB O/D 19 26
ISOLATEB I 36 28
Pin No
(48-pin)
Description
Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and reference
clocks.
Isolate Pin: Active low.
Used to isolate the RTL8111D(L)/RTL8111D(L)-VB from the PCI Express
bus. The RTL8111D(L)/RTL8111D(L)-VB will not drive its PCI Express
outputs (excluding LANWAKEB) and will not sample its PCI Express
input as long as the Isolate pin is asserted.
Datasheet
5.2. PCI Express Interface
Table 2. PCI Express Interface
Symbol Ty pe Pin No
(64-pin)
REFCLK_P I 26 17
REFCLK_N I 27 18
HSOP O 29 20
HSON O 30 21
HSIP I 23 15
HSIN I 24 16
PERSTB I 20 27
CLKREQB O/D 33 25
Pin No
(48-pin)
Description
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.
PCI Express Transmit Differential Pair.
PCI Express Receive Differential Pair.
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the
RTL8111D(L)/RTL8111D(L)-VB returns to a pre-defined reset state and is
ready for initialization and configuration after the de-assertion of the
PERSTB.
Reference Clock Request Signal.
This signal is used by the RTL8111D(L)/RTL8111D(L)-VB to request
starting of the PCI Express reference clock.
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5.3. Transceiver Interface
Table 3. Transceiver Interface
Symbol Type Pin No
(64-pin)
MDIP0 IO 3 2
MDIN0 IO 4 3
MDIP1 IO 6 5
MDIN1 IO 7 6
MDIP2 IO 9 8
MDIN2 IO 10 9
MDIP3 IO 12 11
MDIN3 IO 13 12
Pin No
(48-pin)
Description
In MDI mode, this is the first pair in 1000Base-T, i.e., the BI_DA+/- pair,
and is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
In MDI mode, this is the second pair in 1000Base-T, i.e., the BI_DB+/pair, and is the receive pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
RTL8111D(L)/RTL8111D(L)-VB
Datasheet
5.4. Clock
Table 4. Clock
Symbol Type Pin No
(64-pin)
CKTAL1 I 60 41 Input of 25MHz Clock Reference.
CKTAL2 O 61 42 Output of 25MHz Clock Reference.
Pin No
(48-pin)
Description
5.5. Regulator and Reference
Table 5. Regulator and Reference
Symbol Type Pin No
(64-pin)
SROUT12 O 1 48 Switching Regulator 1.05V Output. Connect to 5µH inductor.
FB12 I 5 4 Feedback Pin for Switching Regulator.
ENSR I 62 43
VDDSR P 63 44, 45 Digital 3.3V Power Supply for Switching Regulator.
RSET I 64 46 Reference. External resistor reference.
Note: See section 7, page 19 for switching regulator layout.
Pin No
(48-pin)
Description
3.3V: Enable switching regulator.
0V: Disable switching regulator.
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5.6. EEPROM
Table 6. EEPROM
Symbol Type Pin No
(64-pin)
EESK O 48 35 Serial Data Clock.
EEDI/AUX O/I 47 34
EEDO I 45 33 Input from Serial Data Output Pin of EEPROM.
EECS O 44 32 EECS: EEPROM chip select.
Pin No
(48-pin)
Description
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
This pin should be connected to EEPROM. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to Aux. Power via
a resistor. If this pin is not pulled high to Aux. Power, the
RTL8111D(L)/RTL8111D(L)-VB assumes that no Aux. Power exists.
5.7. LEDs
Table 7. LEDs
Symbol Type Pin No
(64-pin)
LED0 O
LED1 O
LED2 O 55 34
LED3 O 54 33
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the EEPROM If there is no EEPROM, the default value of the
(LEDS1, LEDS0)=(1, 1).
57 38
56 35
Pin No
(48-pin)
Description
LEDS1-0 00 01 10 11
LED0 Tx/Rx Tx/Rx Tx
LED1 LINK100
LED2 LINK10
LED3 LINK1000 LINK1000 FULL
LINK10/
100/1000
LINK10/
100
LINK
Rx FULL
Datasheet
LINK10/
ACT
LINK100/
ACT
LINK1000
/ACT
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5.8. Power and Ground
Table 8. Power and Ground
Symbol Typ e Pin No
(64-pin)
VDD33 P 16, 37, 46, 53 29, 37 Digital 3.3V Power Supply.
DVDD12 P 21, 32, 38, 43, 49, 52 13, 30, 36 Digital 1.05V Power Supply.
AVDD12 P 8, 11, 14, 58 10, 39 Analog 1.05V Power Supply.
EVDD12 P 22, 28 19 Analog 1.05V Power Supply.
AVDD33 P 2, 59 1, 40 Analog 3.3V Power Supply.
EGND P 25, 31 22 Analog Ground.
GND P 65 7, 14, 31, 47 Ground (Exposed Pad).
Note: Refer to the most updated schematic circuit for correct configuration.
Pin No
(48-pin)
Description
5.9. GPIO Pins
Table 9. GPIO Pins
Symbol Typ e Pin No
(64-pin)
GPI I 50 - General Purpose Input Pin.
GPO O 51 23
Pin No
(48-pin)
Description
General Purpose Output Pin.
This pin reflects the link up or link down state.
High: Link up
Low: Link down
Datasheet
5.10. Test Pins
Table 10. Test Pins
Symbol Typ e Pin No
(64-pin)
Test - 34, 35, 39, 40, 41, 42 - Realtek Internal Use Only.
Pin No
(48-pin)
Description
5.11. NC Pins
Table 11. NC Pins
Symbol Typ e Pin No
(64-pin)
NC - 15, 17, 18 24 Not Connected.
Pin No
(48-pin)
Description
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6
Datasheet
6. Functional Description
6.1. PCI Express Bus Interface
The RTL8111D(L)/RTL8111D(L)-VB is compliant with PCI Express Base Specification Revision 1.1,
and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair.
The RTL8111D(L)/RTL8111D(L)-VB supports four types of PCI Express messages: interrupt messages,
error messages, power management messages, and hot-plug messages. To ease PCB layout constraints,
PCI Express lane polarity reversal and link reversal are also supported.
6.1.1. PCI Express Transmitter
The RTL8111D(L)/RTL8111D(L)-VB’s PCI Express block receives digital data from the Ethernet
interface and performs data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding
technology into 10-bit code groups. Data scrambling is used to reduce the possibility of electrical
resonance on the link, and 8B/10B coding technology is used to benefit embedded clocking, error
detection, and DC balance by adding an overhead to the system through the addition of 2 extra bits. The
data code groups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is
transmitted onto the PCB trace to its upstream device via a differential driver.
6.1.2. PCI Express Receiver
The RTL8111D(L)/RTL8111D(L)-VB’s PCI Express block receives 2.5Gbps serial data from its
upstream device to generate parallel data. The receiver’s PLL circuits are re-synchronized to maintain bit
and symbol lock. Through 8B/10B decoding technology and data de-scrambling, the original digital data
is recovered and passed to the RTL8111D(L)/RTL8111D(L)-VB’s internal Ethernet MAC to be
transmitted onto the Ethernet media.
6.2. LED Functions
The RTL8111D(L)/RTL8111D(L)-VB supports four LED signals in four different configurable operation
modes. The following sections describe the various LED actions.
6.2.1. Link Monitor
The Link Monitor senses link integrity, such as LINK10, LINK100, LINK1000, LINK10/100/1000,
LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link
LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no
network connection exists.
Integrated Gigabit Ethernet Controller for PCI Express 9 Track ID: JATR-1076-21 Rev. 1.
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