Realtek RTL8111C-GR Schematic [ru]
RTL8111C-GR
INTEGRATED GIGABIT ETHERNET CONTROLLER
FOR PCI EXPRESS™ APPLICATIONS
DATASHEET
Rev. 1.1
09 February 2007
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8111C-GR
Datasheet
COPYRIGHT
©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2006/12/12 First release.
1.1 2007/02/09
Changed Figure 1, Pin Assignments, page 3.
Changed Table 8, Power & Ground, page 7.
Removed SMBus table.
Added Table 9, GPIO Pins, page 7.
Changed Table 10, NC (Not Connected) Pins, page 4.
Renamed VDD12 to DVDD12.
Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.1
RTL8111C-GR
Datasheet
Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................2
3. System Applications .................................................................................................... 2
4. Pin Assignments........................................................................................................... 3
4.1. PACKAGE IDENTIFICATION ...............................................................................................................3
5. Pin Descriptions........................................................................................................... 4
5.1. POWER MANAGEMENT/ISOLATION...................................................................................................4
5.2. PCI
5.3. EEPROM.........................................................................................................................................5
5.4. T
5.5. CLOCK..............................................................................................................................................6
5.6. REGULATOR & REFERENCE..............................................................................................................6
5.7. LEDS ...............................................................................................................................................6
5.8. POWER & GROUND...........................................................................................................................7
5.9. GPIO................................................................................................................................................7
5.10. NC (NOT CONNECTED) PINS ............................................................................................................7
EXPRESS INTERFACE .................................................................................................................4
RANSCEIVER INTERFACE ................................................................................................................5
6. Functional Description................................................................................................ 8
6.1. PCI EXPRESS BUS INTERFACE ..........................................................................................................8
6.1.1. PCI Express Transmitter.........................................................................................................................................8
6.1.2. PCI Express Receiver .............................................................................................................................................8
6.2. LED FUNCTIONS ..............................................................................................................................8
6.2.1. Link Monitor...........................................................................................................................................................8
6.2.2. Rx LED...................................................................................................................................................................9
6.2.3. Tx LED ...................................................................................................................................................................9
6.2.4. Tx/Rx LED............................................................................................................................................................10
6.2.5. LINK/ACT LED .................................................................................................................................................... 11
6.3. PHY
6.3.1. PHY Transmitter ...................................................................................................................................................12
6.3.2. PHY Receiver........................................................................................................................................................12
6.4. NEXT PAGE ....................................................................................................................................13
6.5. EEPROM
6.6. P
6.7. V
6.8. MESSAGE SIGNALED INTERRUPT (MSI) .........................................................................................17
6.8.1. MSI Capability Structure in PCI Configuration Space.........................................................................................17
6.8.2. Message Control...................................................................................................................................................18
6.8.3. Message Address ..................................................................................................................................................18
6.8.4. Message Upper Address .......................................................................................................................................19
6.8.5. Message Data.......................................................................................................................................................19
6.9. MSI-X............................................................................................................................................20
6.9.1. MSI-X Capability Structure in PCI Configuration Space.....................................................................................20
TRANSCEIVER ........................................................................................................................12
INTERFACE ....................................................................................................................13
OWER MANAGEMENT ...................................................................................................................14
ITAL PRODUCT DATA (VPD) .......................................................................................................16
Integrated Gigabit Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.1
RTL8111C-GR
Datasheet
6.9.2. Message Control...................................................................................................................................................21
6.9.3. Table Offset/BIR ...................................................................................................................................................21
6.9.4. PBA Offset/PBA BIR.............................................................................................................................................22
6.9.5. Message Address for MSI-X Table Entries ...........................................................................................................22
6.9.6. Message Upper Address for MSI-X Table Entries ................................................................................................23
6.9.7. Message Data for MSI-X Table Entries ................................................................................................................23
6.9.8. Vector Control for MSI-X Table Entries ...............................................................................................................23
6.9.9. Pending Bits for MSI-X PBA Entries....................................................................................................................23
6.10. RECEIVE-SIDE SCALING (RSS).......................................................................................................24
6.10.1. Receive-Side Scaling (RSS) Initialization.............................................................................................................24
6.10.2. RSS Operation ......................................................................................................................................................25
7. Characteristics ........................................................................................................... 26
7.1. ABSOLUTE MAXIMUM RATINGS .....................................................................................................26
7.2. R
7.3. C
7.4. THERMAL CHARACTERISTICS .........................................................................................................27
7.5. DC CHARACTERISTICS ...................................................................................................................27
7.6. AC CHARACTERISTICS ...................................................................................................................28
7.6.1. Serial EEPROM Interface Timing ........................................................................................................................28
7.7. PCI EXPRESS BUS PARAMETERS ....................................................................................................30
7.7.1. Differential Transmitter Parameters.....................................................................................................................30
7.7.2. Differential Receiver Parameters.........................................................................................................................31
7.7.3. REFCLK Parameters............................................................................................................................................31
7.7.4. Auxiliary Signal Timing Parameters ....................................................................................................................35
ECOMMENDED OPERATING CONDITIONS......................................................................................26
RYSTAL REQUIREMENTS ..............................................................................................................26
8. Mechanical Dimensions ............................................................................................ 36
9. Ordering Information ............................................................................................... 36
Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.1
RTL8111C-GR
Datasheet
List of Tables
Table 1. Power Management/Isolation .....................................................................................................4
Table 2. PCI Express Interface .................................................................................................................4
Table 3. EEPROM ....................................................................................................................................5
Table 4. Transceiver Interface ..................................................................................................................5
Table 5. Clock...........................................................................................................................................6
Table 6. Regulator & Reference ...............................................................................................................6
Table 7. LEDs...........................................................................................................................................6
Table 8. Power & Ground.........................................................................................................................7
Table 9. GPIO Pins ...................................................................................................................................7
Table 10. NC (Not Connected) Pins ...........................................................................................................7
Table 11. EEPROM Interface...................................................................................................................13
Table 12. Message Control .......................................................................................................................18
Table 13. Message Address ......................................................................................................................18
Table 14. Message Upper Address ...........................................................................................................19
Table 15. Message Data............................................................................................................................19
Table 16. Message Control .......................................................................................................................21
Table 17. Table Offset/BIR ......................................................................................................................21
Table 18. PBA Offset/PBA BIR...............................................................................................................22
Table 19. Message Address for MSI-X Table Entries..............................................................................22
Table 20. Message Upper Address for MSI-X Table Entries...................................................................23
Table 21. Message Data............................................................................................................................23
Table 22. Vector Control for MSI-X Table Entries..................................................................................23
Table 23. Pending Bits for MSI-X PBA Entries.......................................................................................23
Table 24. Absolute Maximum Ratings.....................................................................................................26
Table 25. Recommended Operating Conditions.......................................................................................26
Table 26. Crystal Requirements ...............................................................................................................26
Table 27. Thermal Characteristics............................................................................................................27
Table 28. DC Characteristics....................................................................................................................27
Table 29. EEPROM Access Timing Parameters ......................................................................................29
Table 30. Differential Transmitter Parameters .........................................................................................30
Table 31. Differential Receiver Parameters..............................................................................................31
Table 32. REFCLK Parameters ................................................................................................................31
Table 33. Auxiliary Signal Timing Parameters ........................................................................................35
Table 34. Ordering Information................................................................................................................36
Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.1
RTL8111C-GR
Datasheet
List of Figures
Figure 1. Pin Assignments........................................................................................................................3
Figure 2. Rx LED .....................................................................................................................................9
Figure 3. Tx LED......................................................................................................................................9
Figure 4. Tx/Rx LED..............................................................................................................................10
Figure 5. LINK/ACT LED .....................................................................................................................11
Figure 6. Message Capability Structure..................................................................................................17
Figure 7. MSI-X Capability Structure ....................................................................................................20
Figure 8. MSI-X Table Structure............................................................................................................20
Figure 9. MSI-X PBA Structure .............................................................................................................20
Figure 10. Serial EEPROM Interface Timing ..........................................................................................28
Figure 11. Single-Ended Measurement Points for Absolute Cross Point and Swing...............................33
Figure 12. Single-Ended Measurement Points for Delta Cross Point ......................................................33
Figure 13. Single-Ended Measurement Points for Rise and Fall Time Matching....................................33
Figure 14. Differential Measurement Points for Duty Cycle and Period .................................................34
Figure 15. Differential Measurement Points for Rise and Fall Time .......................................................34
Figure 16. Differential Measurement Points for Ringback ......................................................................34
Figure 17. Reference Clock System Measurement Point and Loading....................................................35
Figure 18. Auxiliary Signal Timing..........................................................................................................35
Integrated Gigabit Ethernet Controller for PCI Express vi Track ID: JATR-1076-21 Rev. 1.1
RTL8111C-GR
Datasheet
1. General Description
The Realtek RTL8111C-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant
Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and
embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the
RTL8111C-GR offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only)
cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive
equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented to provide robust transmission and reception capability at high speeds.
The RTL8111C-GR is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the
IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect
function, and will auto-configure related bits of the PCI power management registers in PCI configuration
space.
Advanced Configuration Power management Interface (ACPI)—power management for modern
operating systems that are capable of Operating System-directed Power Management (OSPM)—is
supported to achieve the most efficient power management possible. PCI MSI (Message Signaled
Interrupt) and MSI-X are also supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft®
Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To
support WOL from a deep power down state (e.g., D3cold, i.e. main power is off and only auxiliary
exists), the auxiliary power source must be able to provide the needed power for the RTL8111C-GR.
The RTL8111C-GR is fully compliant with Microsoft® NDIS5, NDIS6(IPv4, IPv6, TCP, UDP)
Checksum and Segmentation Task-offload(Large send and Giant send) features, and supports IEEE 802
IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above
features contribute to lowering CPU utilization, especially benefiting performance when in operation on a
network server.
The RTL8111C-GR supports Receive Side Scaling (RSS) to hash incoming TCP connections and
load-balance received data processing across multiple CPUs. RSS improves the number of transactions
per second and number of connections per second, for increased network throughput.
The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin
count, serial, interconnect technology that offers significant improvements in performance over
conventional PCI and also maintains software compatibility with existing PCI infrastructure. The device
embeds an adaptive equalizer in the PCIe PHY for ease of system integration and excellent link quality.
The equalizer enables the length of the PCB traces to reach 40 inches.
The RTL8111C-GR is suitable for multiple market segments and emerging applications, such as desktop,
mobile, workstation, server, communications platforms, and embedded applications.
Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.1
2. Features
RTL8111C-GR
Datasheet
Integrated 10/100/1000 transceiver
Auto-Negotiation with Next Page
capability
Supports PCI Express™ 1.1
Supports pair swap/polarity/skew
correction
Crossover Detection & Auto-Correction
Wake-on-LAN and remote wake-up
support
Microsoft
®
NDIS5, NDIS6 Checksum
Offload (IPv4, IPv6, TCP, UDP) and
Segmentation Task-offload (Large send
and Giant send) support
Supports Full Duplex flow control
(IEEE 802.3x)
Fully compliant with IEEE 802.3,
IEEE 802.3u, IEEE 802.3ab
Supports IEEE 802.1P Layer 2 Priority
Encoding
Supports IEEE 802.1Q VLAN tagging
Serial EEPROM
Transmit/Receive on-chip buffer
support
Supports power down/link down power
saving
Supports PCI MSI (Message Signaled
Interrupt) and MSI-X
Supports Receive-Side Scaling (RSS)
64-pin QFN package (Green package)
Embeds an adaptive equalizer in PCI
express PHY (PCB traces to reach 40
inches)
3. System Applications
PCI Express™ Gigabit Ethernet on Motherboard, Notebook, or Embedded system
Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.1
4. Pin Assignments
RTL8111C-GR
Datasheet
DVDD12
IGPIO
OGPIO
DVDD12
VDD33
LED3
LED2
LED1
LED0
AVDD12
AVDD33
CKTAL1
CKTAL2
ENSR
VDDSR
RSET
EESK
EEDI/AUX
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
123456789
EEDO
VDD33
LLLLLLL TXXXV
65 GND (Exposed Pad)
EECS
DVDD12
NCNCNC
NC
RTL8111C
DVDD12
VDD33
10 11 12 13 14 15 16
ISOLATEB
NC
NC
CLKREQB
2
3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
7
1
DVDD12
EGND
HSON
HSOP
EVDD12
REFCLK_N
REFCLK_P
EGND
HSIN
HSIP
EVDD12
DVDD12
PERSTB
LANW AKEB
NC
NC
NC
MDIP0
AVDD33
SROUT12
FB12
MDIN0
MDIP1
MDIN1
Figure 1. Pin Assignments
AVDD12
MDIP2
MDIN2
AVDD12
MDIP3
MDIN3
AVDD12
VDD33
4.1. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 Rev. 1.1
5. Pin Descriptions
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin
5.1. Power Management/Isolation
Table 1. Power Management/Isolation
Symbol Type Pin No Description
LANWAKEB O/D 19
ISOLATEB I 36
Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
Isolate Pin: Active low.
Used to isolate the RTL8111C-GR from the PCI Express bus. The RTL8111C-GR
will not drive its PCI Express outputs (excluding LANWAKEB) and will not
sample its PCI Express input as long as the Isolate pin is asserted.
RTL8111C-GR
Datasheet
5.2. PCI Express Interface
Table 2. PCI Express Interface
Symbol Type Pin No Description
REFCLK_P I 26
REFCLK_N I 27
HSOP O 29
HSON O 30
HSIP I 23
HSIN I 24
PERSTB I 20
CLKREQB O/D 33
PCI Express Differential Reference Clock Source: 100MHz ± 300ppm.
PCI Express Transmit Differential Pair.
PCI Express Receive Differential Pair.
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8111C-GR returns
to a pre-defined reset state and is ready for initialization and configuration
after the de-assertion of the PERSTB.
Reference clock request signal. This signal is used by the RTL8111C-GR to
request starting of the PCI Express reference clock.
Integrated Gigabit Ethernet Controller for PCI Express 4 Track ID: JATR-1076-21 Rev. 1.1
5.3. EEPROM
Table 3. EEPROM
Symbol Type Pin No Description
EESK O 48 Serial data clock.
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
EEDI/AUX O/I 47
EEDO I 45 Input from serial data output pin of EEPROM.
EECS O 44 EECS: EEPROM chip select.
This pin should be connected to EEPROM. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to Aux. Power
via a resistor. If this pin is not pulled high to Aux. Power, the
RTL8111C-GR assumes that no Aux. Power exists.
5.4. Transceiver Interface
Table 4. Transceiver Interface
Symbol Type Pin No Description
MDIP0 I/O 3
4
MDIN0 I/O
MDIP1 I/O 6
7
MDIN1 I/O
MDIP2 I/O 9
MDIN2 I/O 10
MDIP3 I/O 12
MDIN3 I/O 13
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is
the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive
pair in 10Base-T and 100Base-TX.
In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and
is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit
pair in 10Base-T and 100Base-TX.
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
RTL8111C-GR
Datasheet
Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.1
5.5. Clock
Table 5. Clock
Symbol Type Pin No Description
CKTAL1 I 60 Input of 25MHz clock reference.
CKTAL2 O 61 Output of 25MHz clock reference.
5.6. Regulator & Reference
Table 6. Regulator & Reference
Symbol Type Pin No Description
SROUT12 O 1 Switching regulator 1.2V output. Connect to 5uH inductor.
FB12 I 5 Feedback pin for switching regulator.
ENSR I 62
VDDSR Power 63 Digital 3.3V power supply for switching regulator.
RSET I 64 Reference. External resistor reference.
3.3V: Enable switching regulator.
0 V: disable switching regulator.
RTL8111C-GR
Datasheet
5.7. LEDs
Table 7. LEDs
Symbol Type Pin No Description
LED0 O 57
LED1 O 56
LED2 O 55
LED3 O 54
Note 1: During power down mode, the LED signals are logic high.
Note 2: LEDS1-0’s initial value comes from the 93C46. If there is no 93C46, the
default value of the (LEDS1, LEDS0) = (1, 1).
LEDS1-0 00 01 10 11
LED0 Tx/Rx Tx/Rx Tx LINK10/ACT
LED1 LINK100
LED2 LINK10 LINK10/100 Rx FULL
LED3 LINK1000 LINK1000 FULL
LINK10/100/
1000
LINK
LINK100/
ACT
LINK1000/
ACT
Integrated Gigabit Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.1
5.8. Power & Ground
Table 8. Power & Ground
Symbol Type Pin No Description
VDD33 Power 16, 37, 46, 53 Digital 3.3V power supply.
DVDD12 Power 21, 32, 38, 43, 49, 52 Digital 1.2V power supply.
AVDD12 Power 8, 11, 14, 58 Analog 1.2V power supply.
EVDD12 Power 22, 28 Analog 1.2V power supply.
AVDD33 Power 2, 59 Analog 3.3V power supply.
EGND Power 25, 31 Analog Ground.
GND Power 65 Ground (Exposed Pad).
Note: Refer to the most updated schematic circuit for correct configuration.
5.9. GPIO
Table 9. GPIO Pins
Symbol Type Pin No Description
IGPIO I 50 Input GPIO Pin.
Output GPIO Pin. This pin reflects the link up or link down state.
OGPIO O 51
High: Link up
Low: Link down.
RTL8111C-GR
Datasheet
5.10. NC (Not Connected) Pins
Table 10. NC (Not Connected) Pins
Symbol Type Pin No Description
NC -
15, 17, 18, 34, 35, 39,
40, 41, 42
Not Connected.
Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.1
Loading...