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USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
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REVISION HISTORY
Revision Release Date
1.0 2004/08/19 First release.
1.1 2004/11/05 Package changes. See section 8, Mechanical Dimensions, page 23, and
1.2 2005/03/24 Changed Table 8, Power & Ground, page 6.
Summary
section 9, Ordering Information, page 24.
Changed Table 6, Regulator & Reference, page 5.
Added lead (Pb)-free package identification information on page 3 and on
page 24.
Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.2
TL8111
Datasheet
Table of Contents
1. GENERAL DESCRIPTION...............................................................................................................1
2. FEATURES ..........................................................................................................................................2
3. SYSTEM APPLICATIONS................................................................................................................2
Figure 2. Rx LED ......................................................................................................................................8
Figure 3. Tx LED ......................................................................................................................................8
Figure 5. LINK/ACT LED ......................................................................................................................10
Figure 6. Serial EEPROM Interface Timing ...........................................................................................18
Figure 7. REFCLK Single-Ended Measurement Points for T
Figure 8. REFCLK Single-Ended Measurement Points for V
Figure 9. REFCLK Differential Measurement Points for T
Figure 10. REFCLK V
Range .............................................................................................................22
cross
Figure 11. Auxiliary Signal Timing..........................................................................................................22
Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.2
and T
rise
, V
ovs
, Duty Cycle, and Jitter........................21
period
...............................................21
fall
and Vrb......................................21
uds,
TL8111
Datasheet
1. General Description
The Realtek RTL8111 Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media
Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and
embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, they offer
high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as
Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation,
echo cancellation, timing recovery, and error correction are implemented to provide robust transmission
and reception capability at high speeds.
The device supports the PCI Express 1.0a bus interface for host communications with power management
and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab
specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will
auto-configure related bits of the PCI power management registers in PCI configuration space.
Advanced Configuration Power management Interface (ACPI)--power management for modern operating
systems that are capable of Operating System-directed Power Management (OSPM)—is also supported to
achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also
supported.
In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™, Re-LinkOk, and
Microsoft® Wake-up frame) is supported in both ACPI and APM (Advanced Power Management)
environments. To support WOL from a deep power down state (e.g., D3cold, i.e. main power is off and
only auxiliary exists), the auxiliary power source must be able to provide the needed power for the
RTL8111.
The RTL8111 is fully compliant with Microsoft® NDIS5 (IP, TCP, UDP) Checksum and Segmentation
Task-offload features, and supports IEEE 802 IP Layer 2 priority encoding and 802.1Q Virtual bridged
Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially
benefiting performance when in operation on a network server.
The device features next-generation PCI Express interconnect technology. PCI Express is a
high-bandwidth, low pin count, serial, interconnect technology that offers significant improvements in
performance over conventional PCI and also maintains software compatibility with existing PCI
infrastructure.
The RTL8111 is suitable for multiple market segments and emerging applications, such as desktop, mobile,
workstation, server, communications platforms, and embedded applications.
The signal type codes below are used in the following tables:
I: Input S/T/S: Sustained Tri-State
O: Output O/D: Open Drain
T/S: Tri-State bi-directional input/output pin
5.1. Power Management/Isolation
Table 1. Power Management/Isolation
Symbol Type Pin No Description
LANWAKEB O/D 36
ISOLATEB I 71
Power Management Event: Open drain, active low.
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
Isolate Pin: Active low.
Used to isolate the RTL8111 from the PCI Express bus. The RTL8111 will not drive
its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI
Express input as long as the Isolate pin is asserted.
TL8111
Datasheet
5.2. PCI Express Interface
Table 2. PCI Express Interface
Symbol Type Pin No Description
REFCLK_P I 50
REFCLK_N I 51
HSOP O 54
HSON O 55
HSIP I 47
HSIN I 48
PCI Express Reset Signal: Active low.
When the PERSTB is asserted at power-on state, the RTL8111 returns to a
pre-defined reset state and is ready for initialization and configuration after
the de-assertion of the PERSTB.
5.3. EEPROM
Table 3. EEPROM
Symbol Type Pin No Description
EESK O 75 Serial data clock.
EEDI: Output to serial data input pin of EEPROM.
AUX: Input pin to detect if Aux. Power exists or not on initial power-on.
EEDI/AUX O/I 74
EEDO I 72 Input from serial data output pin of EEPROM.
EECS O 71 EECS: EEPROM chip select.
This pin should be connected to EEPROM. To support wakeup from ACPI
D3cold or APM power-down, this pin must be pulled high to Aux. Power
via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111
assumes that no Aux. Power exists.