Realtek RTD2120K, RTD2120L, RTD2120S, RTD2120L-LF, RTD2120S-LF User Manual

Realtek RTD2120-series

RTD2120-series

8051 Embedded Micro-Controller for Monitor

Fully Technology

Revision

Version 1.06

Last updated: 2007/4/3

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Realtek RTD2120-series

All NC pin must be left unconnected or be connected

Revision History

Rev. Description Date

1.02 1. CLKO2( XFR FF01[1] ) default value 1 à 0

2. PLL_TEST(XFR FF10[7] ) à PLL_STA

3. revise the “Reset table”

1.03 1. revise the SFR table à delete address 93 , B3

2. add PWM description

3. add power supply current

4. add description “

to GND.”

1.04 1. added RTD2120K, QFP44 pin config.

2. added RTD2120K, QFP44 pin description.

1.05 1. added reset pulse minimum length is 16 MCU clk cycle (page-10) 2007/2/9

1.06 1. modified WDT block diagram 2007/4/3

2006/2/9

2006/8/1

2007/1/16

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Realtek RTD2120-series

Overview

This chip is the micro-processor of LCD monitor. It uses the Designware DW8051 of Synopsys
as the 8051 core of this chip and is compatible with other industry 8051 series. Also, 96Kbyte
FLASH with 8 bit bus is embedded in this chip which is licensed from TSMC 0.18um e-FLASH
process. Here we use the package of PLCC44/LQFP48/QFP44 if we would like to have a discrete
MCU controller or we make a multi-chip package with our LCD monitor controller to form one
chip package to save the cost of package and PCB material.

Features

l Operating voltage range : 3.0V to 3.6V
l 8051 core, CPU operating frequency up to 50MHz
l 4 clocks per machine cycle
l 256-byte internal RAM
l 512-byte external data RAM, including 256-byte DDC RAM(128-byte x 2) and 256-byte

general purpose RAM

l 96K-byte flash memory, 64k for program and 32k for saving parameter
l Two DDC ports compliant with VESA DDC1/2B/2Bi/CI
l Three channels of PWM DAC with programmable frequency from 100K to 100Hz
l Watchdog timer with programmable interval
l Three 16-bit counters/timers (T0, T1, and T2)
l One PLL to provide programmable operating frequency and clock output, 2 clock output

ports

l One full-duplex serial port
l Six interrupt sources with 2 external interrupts
l Four channels of 6-bit ADC
l Hardware In System Programming(ISP) capability, no boot code required
l Built-in Low voltage reset circuit
l Embedded 1.8V regulator
l Code protection
l Available in 44-pin PLCC, 44-pin QFP or 48-pin LQFP package

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Realtek RTD2120-series

Pin Configurations

P5.0/PWM0

P5.1/PWM1

P5.2/PWM2

P5.3/PWM3

P5.4/PWM4

NC

P1.0/T2

VCC

P1.1

P1.3

P1.2

P5.5/PWM5

DSCL/P5.6
DSDA/P5.7

RST

ASCL/P3.0/RXD

NC

ASDA/P3.1/TXD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

44

1

2

3

4

5

6

7
8

9
10
11
12

13
14

15
16

17

19

18

P7.6/CLKO2

P7.7

P5.2/PWM2

P5.3/PWM3

P5.4/PWM4

20

XO

RTD2120S

21

XI

P5.0/PWM0

P5.1/PWM1

44-PIN

PLCC

23

22

VSS

NC

24

P6.0/ADC0

NC

42

43

26

25

P6.2/ADC2

P6.1/ADC1

P1.0/T2

VCC

40

41

39
38

37
36
35
34

33

32
31
30

29

28

27

P6.3/ADC3

P6.4

P1.4
P1.5
P1.6

P1.7

NC

NC
NC

VSYNC

P6.7

P6.6/CLKO1

P6.5

P1.3

P1.2

P1.1

40

41

43

44

45

46

47

P5.5/PWM5

DSCL/P5.6

DSDA/P5.7

RST

ASCL/P3.0/RXD

NC
NC

ASDA/P3.1/TXD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

48

1

2
3
4
5
6

7
8

9

10

11

12

13

P7.6/CLKO2

15

14

P7.7

XO

17

16

VSS

XI

42

RTD2120L

48-PIN

LQFP

19

18

NC

NCNC

21

20

P6.1/ADC1

P6.0/ADC0

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38

39

22

P6.2/ADC2

37

36
35
34
33
32
31
30
29
28
27
26
25

23

24

P6.3/ADC3

P6.4

P1.4
P1.5
P1.6

P1.7

NC
NC

NC
NC

VSYNC

P6.7

P6.6/CLKO1

P6.5

Realtek RTD2120-series

P5.0/PWM0

P5.1/PWM1

P5.2/PWM2

P5.3/PWM3

P5.4/PWM4

NC

39

40

41

42

43

44

P1.0/T2

VCC

38

P1.1

36

37

P1.3

P1.2

34

35

P5.5/PWM5

DSCL/P5.6

DSDA/P5.7

ASCL/P3.0/RXD

ASDA/P3.1/TXD

P3.2/INT0
P3.3/INT1

P3.4/T0
P3.5/T1

RST

NC

1

2

3

4

5

6

7

8
9

10

11

13

12

P7.6/CLKO2

P7.7

14

XO

RTD2120K

44-PIN

16

15

VSS

XI

QFP

17

NC

18

P6.0/ADC0

20

19

P6.2/ADC2

P6.1/ADC1

33
32

31
30

29
28

27

26
25
24

23

22

21

P6.3/ADC3

P6.4

P1.4
P1.5
P1.6

P1.7

NC

NC
NC

VSYNC

P6.7

P6.6/CLKO1

P6.5

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Realtek RTD2120-series

Block Diagram

Internal RAM

00-FF

Watch dog

timer

Interrupt

Controller

Serial
port 0

DW8051_core

256 byt`e

GPIO

IRAM_bus

Timer 2

Timer 0

Timer 1

TSMC FLASH

96K byte

FLASH/ISP

interface

MEM_bus

External RAM

Interface

External RAM

256 byte

F800-F8FF

DDC_RAM1

128 byte

F900-F97FF980-F9FF

XFR

register

FF00

-FFFF

DDC_RAM2

128 byte

Routing

Box

I2C slave 1

I2C slave 2

PWM

PWM

PWM

generator

generator

generator

6 bit ADC

6 bit ADC

6 bit ADC

6 bit ADC

PLL

(clock gen.)

XTAL

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Realtek RTD2120-series

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

Pin Description

Pin No.

PLCC

LQFP

44

2 44 40

3 45 41

4 46 42

5 47 43

6 48 44

7 1 1 P5.5/PWM5 I/O -- 1(P5.5)

8 2 2 P5.6/DSCL I/O -- 1(P5.6)

9 3 3 P5.7/DSDA I/O -- 1(P5.7)

10 4 4 RST I Down 0 Input High active RESET

48

QFP

44

Name I/O Internal

Pull

Up/Down

P5.0/PWM0 I/O -- 1(P5.0)

P5.1/PWM1 I/O -- 1(P5.1)

P5.2/PWM2 I/O -- 1(P5.2)

P5.3/PWM3 I/O -- 1(P5.3)

P5.4/PWM4 I/O -- 1(P5.4)

Default

output

value

Pin Type

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Open

Drain

Description

PWM0 output

PWM1 output

PWM2 output

PWM3 output

PWM4 output

PWM5 output

DVI DDC SCL

General purpose I

DVI DDC SDA

11 5 5 ASCL/P3.0/RXD I/O -- 1(ASCL) Open

Drain

13 8 7 ASDA/P3.1/TXD I/O -- 1(ASDA) Open

Drain

14 9 8 P3.2/INT0 I/O -- 1(P3.2) Standard

8051

15 10 9 P3.3/INT1 I/O -- 1(P3.3) Standard

8051

16 11 10

17 12 11

18 13 12

19 14 13

20 15 14

21 16 15

22 17 16

P3.4/T0 I/O -- 1(P3.4) Standard

8051

P3.5/T1 I/O -- 1(P3.5) Standard

8051

P7.6/CLKO2 I/O Up 1 Push-Pull

P7.7 I/O Up 1 Push-Pull

XO

XI

VSS

O -- -- -- Crystal out

I -- -- -- Crystal in

-- -- -- -- Ground

ADC DDC SCL /

RXD

ADC DDC SDA /

TXD

External interrupt 0

External interrupt 1

Timer 0

Timer 1

Clock out 2

General purpose I/O

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Realtek RTD2120-series

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

General purpose I/O /

Pin No.

PLCC LQFP QFP

24 20 18

25 21 19

26 22 20

27 23 21

28 24 22

29 25 23

30 26 24

31 27 25

32 28 26

36 33 30

37 34 31

38 35 32

39 36 33

40 37 34

41 38 35

42 39 36

43 40 37

44 41 38

Note: All NC pin must be left unconnected or be connected to GND.

Name I/O Internal

Pull

Up/Down

P6.0/ADC0 I/O Up 1(P6.0) Push-Pull

P6.1/ADC1 I/O Up 1(P6.1) Push-Pull

P6.2/ADC2 I/O Up 1(P6.2) Push-Pull

P6.3/ADC3 I/O Up 1(P6.3) Push-Pull

P6.4 I/O Up 1 Push-Pull

P6.5 I/O Up 1 Push-Pull

P6.6/CLKO1 I/O Up 1(P6.6) Push-Pull

P6.7 I/O Up 1 Push-Pull

VSYNC

P1.7 I/O -- 1 Standard

P1.6 I/O -- 1 Standard

P1.5 I/O -- 1 Standard

P1.4 I/O -- 1 Standard

P1.3 I/O -- 1 Standard

P1.2 I/O -- 1 Standard

P1.1 I/O -- 1 Standard

P1.0/ET2 I/O -- 1(P1.0) Standard

VCC

I Down 0 Input VSYNC input

-- -- -- -- Power

Default

output

value

Pin Type

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

8051/

Push-Pull

Description

ADC 0 input

ADC 1 input

ADC 2 input

ADC 3 input

General purpose I/O

General purpose I/O

Clock out 1

General purpose I/O

General purpose I/O

General purpose I/O

General purpose I/O

General purpose I/O

General purpose I/O

General purpose I/O

General purpose I/O

External Timer 2

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Realtek RTD2120-series

DW8051 micro-processor

The DW8051 contained in RTD2120 is compatible with industry standard 803x/805x and

provides the following design features and enhancements to the standard 8051 microcontroller:

1. High speed architecture

Compared to standard 8051, the DW8051 processor core provides increased performance by

executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard

8051. The shortened bus timing improves the instruction execution rate for most instructions by a
factor of three over the standard 8051 architectures. The average speed improvement for the entire
instruction set is approximately 2.5X.

2. Stretch Memory Cycles

The stretch memory cycle feature enables application software to adjust the speed of data
memory access. The DW8051 can execute the MOVX instruction in as little as 2 instruction cycles.
However, it is sometimes desirable to stretch this value; for example, to access slow memory or slow
memory-mapped peripherals such as UARTs or LCDs.

The three LSBs of the Clock Control Register (at SFR location 8Eh) control the stretch value.
You can use stretch values between zero and seven. A stretch value of zero adds zero instruction
cycles, resulting in MOVX instructions executing in two instruction cycles. A stretch value of seven
adds seven instruction cycles, resulting in MOVX instructions executing in nine instruction cycles.
The stretch value can be changed dynamically under program control.

By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory
access, the software must set the stretch value to zero. The stretch value affects only data memory
access. The only way to reduce the speed of program memory (ROM) access is to use a slower clock.

3. Dual Data Pointers

The DW8051 employs dual data pointers to accelerate data memory block moves. The standard
8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The
DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h. It is not
necessary to modify code to use DPTR0.

The DW8051 adds a second data pointer (DPTR1) at SFR locations 84h and 85h. The SEL bit in
the DPTR Select register, DPS (SFR 86h), selects the active pointer. When SEL = 0, instructions that
use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use
DPL1 and DPH1. SEL is the bit 0 of SFR location 86h. No other bits of SFR location 86h are used.

All DPTR-related instructions use the currently selected data pointer. To switch the active
pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).
This requires only one instruction to switch from a source address to a destination address, saving
application code from having to save source and destination addresses when doing a block move.

Using dual data pointers provides significantly increased efficiency when moving large blocks of

data.

4. Timer Rate Control

One important difference exists between the RTD2120 and 80C32 regarding timers. The original
80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud
rates(depending on the mode). The RTD2120 architecture normally runs using 4 clocks per cycle.
However, in the area of timers, it will default to a 12 clock per cycle scheme on a reset. This allows
existing code with real–time dependencies such as baud rates to operate properly. If an application
needs higher speed timers or serial baud rates, the timers can be set to run at the 4 clock rate.

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Realtek RTD2120-series

The Clock Control register (CKCON – 8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control
bit is set to a zero, the device uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer zero. Note that
unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls
are independent.

Memory Organization

Internal Data memory

l 256 bytes of internal RAM
l 128 bytes of Special Function Register (SFR)

External Data memory

l 128 bytes of External Special Function Register (XFR)
l 256 bytes of DDCRAM(128-bytex2)
l 256 bytes of general purpose RAM
l 32k bytes of flash for EDID data and other parameters

External Program memory

l 64k bytes of flash for program memory
l The program content can not be read out unless user mass erase the flash first.

Internal Data Memory

External Data Memory

External Program Memory

FF

Internal RAM

Indirect addressing

80
7F

Internal RAM

Direct/Indirect

00

addressing

SFR

Direct addressing

FFFF

FF00

F9FF
F900

F8FF
F800

7FFF

0000

XFR

Unused

DDC_RAM1&2

General Purpose RAM

Unused

flash 64~96K

FFFF

flash 0~64K

0000

Reset

There are five reset sources in RTD2120, as described below:
l RST pin

The external reset is high active and its pulse width must be larger than 16 mcu clock cycles. The

RST pin can reset the whole chip of RTD2120.
l Low voltage reset(LVR) and power on reset(POR)

The LVR and POR monitor the power status of RTD2120. The same as external reset, the LVR

and POR will reset the whole chip of RTD2120 when triggered.
l Software reset

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Realtek RTD2120-series

1

INT

1

INT

To activate software reset, set FF39[1](SOF_RST). When software reset is triggered, it will reset

all modules except debug mode.
l Watchdog timer(WDT)

The watchdog timer generates reset when it is overflowed. The watchdog timer resets almost the

same modules as software reset except itself(watchdog timer module).
l In System Programing(ISP) reset

ISP reset will generate when entering ISP mode. Compared to Watchdog timer reset, ISP mode

resets almost the same modules as Watchdog timer except itself(ISP module).

Debug mode

module
RST pin O O O O
LVR & POR O O O O
Software reset x O O O
WDT reset x x O x
ISP reset x x O x
Note: O = Reset , x = No effect

Interrupt

Six interrupts are provided in RTD2120. Four of these are generated automatically by internal
operation: timer 0, timer 1, timer 2 and the serial port interrupt. The other two interrupts are triggered
by external pins: INT0 and INT1. Moreover, the DDC and IIC interrupts are connected to DW8051

source as the following figure.

PIN_INT1_EN

pin INT1

Watchdog timer
module

CPU ISP module and

other modules

A_WR_I

D_WR_I

128VS_I

STOP_I

D_OUT_I

D_IN_I

SUB_I

SLV_I

AWRI_EN

DWRI_EN

VSI_EN

STOPI_EN

DOLI_EN

DILI_EN

SUBI_EN

SLVI_EN

to DW8051

Timer/Counter

RTD2120 has three timers/counters: T0, T1 andT2. T0 and T1 are fully compatible to
timer/counter in standard 8051’s. Like timer2 in 8052, T2 of RTD2120 has three operating modes: 16­bit timer/counter with capture, 16-bit auto-reload timer/counter and Baud rate generator. However, T2
of RTD2120 does not support “Timer2 output enable(T2OE)” and “downcount enable(DCEN)”. The
SFRs associated with Timer2 are listed below.

Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Addr
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 C8h
RCAP2L CAh

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Realtek RTD2120-series

RCAP2H CBh
TL2 CCh
TH2 CDh

1. 16-bit timer/counter with capture

The Timer 2 capture mode is the same as the 16-bit timer/counter with the addition of the capture
registers and control signals. If EXEN2 = 0, Timer2 is a 16-bit timer/counter . The C/T2 bit determines
whether the 16-bit counter counts osc cycles (divided by 4 or 12), or high-to-low transitions on the
P1.0 pin. The TR2 bit enables the counter. When the count increments from FFFFh, the TF2 flag is set.

The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-low
transition on P1.1 when EXEN2 = 1 causes the Timer 2 value to be loaded into the capture registers
(RCAP2L and RCAP2H).

2. 16-bit timer/counter with auto-reload

When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode. Control of counter input is the
same as for the other 16-bit counter modes. When the count increments from FFFFh, Timer 2 sets the
TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting
value into the RCAP2L and RCAP2H registers. When Timer 2 is in auto-reload mode, a reload can be
forced by a high-to-low transition on the P1.1 pin, if enabled by EXEN2 = 1.

3. Baud rate generator
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in

serial mode 1 or 3. In baud rate generator mode, Timer 2 functions in auto-reload mode. However,
instead of setting the TF2 flag, the counter overflow generates a shift clock for the serial port function.
As in normal auto-reload mode, the overflow also causes the preloaded start value in the RCAP2L and
RCAP2H registers to be reloaded into the TL2 and TH2 registers. When either TCLK = 1 or RCLK =
1, Timer 2 is forced into auto-reload operation, regardless of the state of the CP/RL2 bit. When
operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode, a Timer 2 interrupt
can only be generated by a high-to-low transition on the P1.1 pin setting the EXF2 bit, and only if
enabled by EXEN2 = 1.

The counter time base in baud rate generator mode is osc/2. To use an external clock source,

set C/T2 to 1 and apply the desired clock source to the P1.0 pin.

Special Function Registers(SFR)

Register

SP 07 81
DPL0 00 82
DPH0 00 83

DPL1 00 84
DPH1 00 85
DPS 0 0 0 0 0 0 0 SEL 00 86

PCON SMOD0 1 1 GF1 GF0 STOP IDLE 30 87
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 88
TMOD GATE C/T M1 M0 GATE C/T M1 M0 00 89
TL0 00 8A

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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset
Value
(Hex)

Addr

(Hex)