Realtek ALC269Q-GR, ALC269QSRS-GR Schematics
ALC269
(ALC269Q-GR, ALC269QSRS-GR)
HIGH DEFINITION AUDIO CODEC WITH
EMBEDDED CLASS D SPEAKER AMPLIFIER
DATASHEET
Rev. 1.1
25 April 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
ii Track ID: JATR-1076-21 Rev. 1.1
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC269 codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2008/04/15 First Release
1.1 2008/04/25 Revised Figure 1 Block Diagram, page 5.
Revised Table 83 Analog Performance, page 64 (DAC/ADC Full-Scale Input Voltage).
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
iii Track ID: JATR-1076-21 Rev. 1.1
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................2
2.1. HARDWARE FEATURES .................................................................................................................................................2
2.2. SOFTWARE FEATURES ..................................................................................................................................................3
3. SYSTEM APPLICATIONS ...............................................................................................................................................4
4. BLOCK DIAGRAM...........................................................................................................................................................5
4.1. ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................6
5. PIN ASSIGNMENTS..........................................................................................................................................................7
5.1. GREEN PACKAGE AND VERSION IDENTIFICATION.........................................................................................................7
6. PIN DESCRIPTIONS.........................................................................................................................................................8
6.1. DIGITAL I/O PINS .........................................................................................................................................................8
6.2. ANALOG I/O PINS ........................................................................................................................................................8
6.3. FILTER/REFERENCE ......................................................................................................................................................9
6.4. POWER/GROUND..........................................................................................................................................................9
7. HIGH DEFINITION AUDIO LINK PROTOCOL........................................................................................................10
7.1. LINK SIGNALS ............................................................................................................................................................10
7.1.1. Signal Definitions ................................................................................................................................................. 11
7.1.2. Signaling Topology ...............................................................................................................................................12
7.2. FRAME COMPOSITION ................................................................................................................................................13
7.2.1. Outbound Frame – Single SDO............................................................................................................................13
7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................14
7.2.3. Inbound Frame – Single SDI................................................................................................................................15
7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................16
7.2.5. Variable Sample Rates ..........................................................................................................................................16
7.3. RESET AND INITIALIZATION ........................................................................................................................................19
7.3.1. Link Reset .............................................................................................................................................................19
7.3.2. Codec Reset ..........................................................................................................................................................20
7.3.3. Codec Initialization Sequence ..............................................................................................................................21
7.4. VERB AND RESPONSE FORMAT...................................................................................................................................22
7.4.1. Command Verb Format ........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................22
7.5. POWER MANAGEMENT...............................................................................................................................................23
8. SUPPORTED VERBS AND PARAMETERS ................................................................................................................24
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .............................................................................................................24
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................24
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................24
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................25
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................25
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................25
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................26
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................27
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................28
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................28
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
iv Track ID: JATR-1076-21 Rev. 1.1
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)...........................29
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h).........................29
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)........................................................30
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)..................................................30
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..................................................30
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...........................................................31
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)...............................................31
8.2. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................32
8.3. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................32
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..........................................................................................33
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................35
8.6. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................35
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................36
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................36
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................37
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................37
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................38
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).............................................................................................................40
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH) ....................................................................................................41
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H)......................................................................................................42
8.15. VERB – GET POWER STATE (VERB ID=F05H) ............................................................................................................43
8.16. VERB – SET POWER STATE (VERB ID=705H) .............................................................................................................43
8.17. VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................44
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................44
8.19. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...............................................................................................45
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H)................................................................................................45
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................46
8.22. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................46
8.23. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................47
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................47
8.25. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ........................................................................................48
8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) .48
8.27. VERB – GET BEEP GENERATOR (VERB ID=F0AH)....................................................................................................49
8.28. VERB – SET BEEP GENERATOR (VERB ID=70AH).....................................................................................................49
8.29. VERB – GET GPIO DATA (VERB ID=F15H)................................................................................................................50
8.30. VERB – SET GPIO DATA (VERB ID=715H).................................................................................................................50
8.31. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................51
8.32. VERB – SET GPIO ENABLE MASK (VERB ID=716H)..................................................................................................51
8.33. VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................52
8.34. VERB – SET GPIO DIRECTION (VERB ID=717H)........................................................................................................52
8.35. VERB – GET GPIO WAKE ENABLE MASK(VERB ID=F18H).......................................................................................53
8.36. VERB-SET GPIO WAKE ENABLE MASK(VERB ID=718H)..........................................................................................53
8.37. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .........................................................54
8.38. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................54
8.39. VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................55
8.40. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH) ...........................................55
8.41. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................56
8.42. GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH)........................................................................................57
8.43. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H/723H~720H TO SET BIT[31:0]).....................................................57
8.44. GET/SET EAPD ENABLE (VERB ID= F0CH/70CH) ....................................................................................................58
9. ELECTRICAL CHARACTERISTICS...........................................................................................................................59
9.1. DC CHARACTERISTICS...............................................................................................................................................59
9.1.1. Absolute Maximum Ratings..................................................................................................................................59
9.1.2. Threshold Voltage.................................................................................................................................................59
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Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
v Track ID: JATR-1076-21 Rev. 1.1
9.1.3. Digital Filter Characteristics ...............................................................................................................................60
9.1.4. S/PDIF Output Characteristics ............................................................................................................................60
9.2. AC CHARACTERISTICS...............................................................................................................................................61
9.2.1. Link Reset and Initialization Timing.....................................................................................................................61
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................62
9.2.3. S/PDIF Output Timing..........................................................................................................................................63
9.2.4. Test Mode..............................................................................................................................................................63
9.3. ANALOG PERFORMANCE ............................................................................................................................................64
9.4. CLASS D POWER AMPLIFIER PERFORMANCE..............................................................................................................65
10. APPLICATION CIRCUITS .......................................................................................................................................66
10.1. FILTER CONNECTION..................................................................................................................................................66
10.2. POWER AND JACK CONNECTION.................................................................................................................................67
10.3. SPDIF-OUT CONNECTION ........................................................................................................................................68
11. MECHANICAL DIMENSIONS......................................................................................................................................69
11.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................70
12. ORDERING INFORMATION ...................................................................................................................................71
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
vi Track ID: JATR-1076-21 Rev. 1.1
List of Tables
TABLE 1. DIGITAL I/O PINS .........................................................................................................................................................8
TABLE 2. ANALOG I/O PINS.........................................................................................................................................................8
TABLE 3. FILTER/REFERENCE......................................................................................................................................................9
TABLE 4. POWER/GROUND ..........................................................................................................................................................9
TABLE 5. LINK SIGNAL DEFINITIONS.........................................................................................................................................11
TABLE 6. HDA SIGNAL DEFINITIONS ........................................................................................................................................ 11
TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE ....................................................................................................17
TABLE 8. 48KHZ VARIABLE RATE O F DELIVERY TIMING ...........................................................................................................17
TABLE 9. 44.1KHZ VARIABLE RAT E O F DELIVERY TIMING ........................................................................................................18
TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT..............................................................................................................22
TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT............................................................................................................22
TABLE 12. SOLICITED RESPONSE FORMAT ..................................................................................................................................22
TABLE 13. UNSOLICITED RESPONSE FORMAT .............................................................................................................................22
TABLE 14. SYSTEM POWER STATE DEFINITIONS .........................................................................................................................23
TABLE 15. POWER CONTROLS IN NID=01H ................................................................................................................................23
TABLE 16. POWERED DOWN CONDITIONS...................................................................................................................................23
TABLE 17. VERB – GET PARAMETERS (VERB ID=F00H) .............................................................................................................24
TABLE 18. PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H)..........................................................................24
TABLE 19. PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) ........................................................................24
TABLE 20. PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H) ................................................25
TABLE 21. PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H) .......................................................25
TABLE 22. PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H) ..........................................25
TABLE 23. PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H)..............................................26
TABLE 24. PARAMETER – SUPPORTED PCM SIZE, RATE S (VERB ID=F00H, PARAMETER ID=0AH) ............................................27
TABLE 25. PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)............................................28
TABLE 26. PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH) ................................................................28
TABLE 27. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH) ........................29
TABLE 28. PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H) .....................29
TABLE 29. PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH) .......................................................30
TABLE 30. PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) .................................................30
TABLE 31. PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H)...................................................30
TABLE 32. PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) .............................................................31
TABLE 33. PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H) ..............................................31
TABLE 34. VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H)................................................................................32
TABLE 35. VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................32
TABLE 36. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................33
TABLE 37. VERB – GET PROCESSING STATE (VERB ID=F03H)....................................................................................................35
TABLE 38. VERB – SET PROCESSING STATE (VERB ID=703H).....................................................................................................35
TABLE 39. VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................36
TABLE 40. VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................36
TABLE 41. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................37
TABLE 42. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................37
TABLE 43. VERB – GET AMPLIFIER GAIN (VERB ID=BH)...........................................................................................................38
TABLE 44. VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................40
TABLE 45. VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................41
TABLE 46. VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................42
TABLE 47. VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................43
TABLE 48. VERB – SET POWER STATE (VERB ID=705H).............................................................................................................43
TABLE 49. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................44
TABLE 50. VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................45
TABLE 51. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................45
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Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
vii Track ID: JATR-1076-21 Rev. 1.1
TABLE 52. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................46
TABLE 53. VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H)............................................................................46
TABLE 54. VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................47
TABLE 55. VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................47
TABLE 56. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH)........................................................................................48
TABLE 57. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)48
TABLE 58. VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................49
TABLE 59. VERB – SET BEEP GENERATOR (VERB ID=70AH) ....................................................................................................49
TABLE 60. VERB – GET GPIO DATA (VERB ID=F15H) ...............................................................................................................50
TABLE 61. VERB – SET GPIO DATA (VERB ID=715H) ................................................................................................................50
TABLE 62. VERB – GET GPIO ENABLE MASK (VERB ID=F16H) ................................................................................................51
TABLE 63. VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................51
TABLE 64. VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................52
TABLE 65. VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................52
TABLE 66. VERB – GET GPIO WAKE ENABLE MASK (VERB ID=F18H)......................................................................................53
TABLE 67. VERB – SET GPIO WAKE ENABLE MASK (VERB ID=718H).......................................................................................53
TABLE 68. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................54
TABLE 69. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................54
TABLE 70. VERB – FUNCTION RESET (VERB ID=7FFH)..............................................................................................................55
TABLE 71. VERB –GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)............................................55
TABLE 72. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................56
TABLE 73. GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH) .......................................................................................57
TABLE 74. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0])....................................................57
TABLE 75. GET/SET EAPD ENABLE (VERB ID=F0CH / 70CH ) ..................................................................................................58
TABLE 76. ABSOLUTE MAXIMUM RAT IN G S .................................................................................................................................59
TABLE 77. THRESHOLD VOLTAGE ...............................................................................................................................................59
TABLE 78. DIGITAL FILTER CHARACTERISTICS ...........................................................................................................................60
TABLE 79. S/PDIF INPUT/OUTPUT CHARACTERISTICS................................................................................................................60
TABLE 80. LINK RESET AND INITIALIZATION TIMING..................................................................................................................61
TABLE 81. LINK TIMING PARAMETERS AT THE CODEC ................................................................................................................62
TABLE 82. S/PDIF OUTPUT TIMING............................................................................................................................................63
TABLE 83. ANALOG PERFORMANCE............................................................................................................................................64
TABLE 84. CLASS D POWER AMPLIFIER PERFORMANCE .............................................................................................................65
TABLE 85. ORDERING INFORMATION ..........................................................................................................................................71
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
viii Track ID: JATR-1076-21 Rev. 1.1
List of Figures
FIGURE 1. BLOCK DIAGRAM .......................................................................................................................................................5
FIGURE 2. ANALOG INPUT/OUTPUT UNIT....................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS - ALC269 (QFN-48).....................................................................................................................7
FIGURE 4. HDA LINK PROTOCOL ..............................................................................................................................................10
FIGURE 5. BIT TIMING...............................................................................................................................................................11
FIGURE 6. SIGNALING TOPOLOGY .............................................................................................................................................12
FIGURE 7. SDO OUTBOUND FRAME ..........................................................................................................................................13
FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC...............................................................................................................14
FIGURE 9. STRIPED STREAM ON MULTIPLE SDOS.....................................................................................................................14
FIGURE 10. SDI INBOUND STREAM.............................................................................................................................................15
FIGURE 11. SDI STREAM TAG AND DATA ....................................................................................................................................15
FIGURE 12. CODEC TRANSMITS DATA OVER MULTIPLE SDIS .....................................................................................................16
FIGURE 13. LINK RESET TIMING.................................................................................................................................................20
FIGURE 14. CODEC INITIALIZATION SEQUENCE ..........................................................................................................................21
FIGURE 15. LINK RESET AND INITIALIZATION TIMING ................................................................................................................61
FIGURE 16. LINK SIGNALS TIMING .............................................................................................................................................62
FIGURE 17. OUTPUT TIMING .......................................................................................................................................................63
FIGURE 18. FILTER CONNECTION................................................................................................................................................66
FIGURE 19. POWER AND JACK CONNECTION ...............................................................................................................................67
FIGURE 20. SPDIF-OUT CONNECTION.......................................................................................................................................68
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
1 Track ID: JATR-1076-21 Rev. 1.1
1. General Description
The ALC269 is a High Definition Audio Codec that integrates a 2+2-channel DAC, a 4-channel ADC,
and a Class D Speaker Amplifier.
The 2+2-channel DAC supports two independent stereo sound outputs simultaneously. The 4-channel
ADC integrates two stereo and independent analog sound inputs (multiple streaming).
The ALC269 incorporates Realtek converter technology to achieve a 98dB dynamic range playback
quality and a 98dB dynamic range recording quality. It meets the current WLP3.10 (Windows Logo
Program) and future WLP requirements that become effective from 01 June 2008.
The ALC269 also supports stereo digital microphone channels (microphone array) with Acoustic Echo
Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,
significantly improving voice quality for PC VoIP applications.
As well as basic audio functions, the ALC269 has two independent S/PDIF outputs; one could be used to
connect a PC to high-quality consumer electronic products such as digital decoders and speakers, the
other could provide a dedicated digital output to a HDMI transmitter (common in high end PCs).
There are three integrated power amplifiers. The first is a linear headphone amplifier at port C. The
second headphone amplifier at port A removes the need for external DC blocking capacitors, eliminating
pop noise caused by these capacitors. The third is an integrated stereo Class D amplifier to directly drive a
mini-speaker. The Class D amplifier is designed to drive speakers with as low as 4Ω impedance. Its
maximum output power is 2.3W per channel at 5V power supply. The advantage of an integrated Class D
amplifier in the ALC269 is high efficiency with low power consumption.
The ALC269 integrates five hardware equalizer bands composed of one low-pass filter, one high-pass
filter, and three band-pass filters to compensate for mini-speaker frequency response. All the equalizer
filters are programmable via the BIOS, allowing the equalizer to function without the need to customize
the audio driver.
The ALC269 conforms to Intel’s Audio Codec low power state white paper and is ECR compliant.
Note: ALC269 version differences are listed in section 12 Ordering Information, page 71.
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
2 Track ID: JATR-1076-21 Rev. 1.1
2. Features
2.1.
Hardware Features
98dB Signal-to-Noise Ratio (A-weighting) for DAC output
98dB Signal-to-Noise Ration (A-weighting) for ADC input
Meets WLP (Windows Logo Program) 3.10 and future WLP requirements that become effective
from 01 June 2008
2+2-channel DAC supports 16/20/24-bit PCM format for independent two stereo channel audio
playback
4-channel ADC supports 16/20/24-bit PCM format for independent two stereo channel audio inputs
All DACs supports 44.1/48/96/192kHz sample rate
All ADCs support 44.1/48/96kHz sample rate
S/PDIF-OUT support 16/20/24-bit format and 32/44.1/48/88.2/96/192kHz rate
Supports MONO line level output
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.2V/4.2V VREFOUT as bias voltage for analog microphone input
Two jack detection pins each designed to detect up to 4 jacks
1dB resolution of input and output volume control
Programmable +10/+20/+30dB boost gain for analog microphone input
Built-in headphone amplifiers for port-A and port-C.
2 GPIOs are supported for customized applications (pin shared with digital microphone interface)
EAPD (External Amplifier Power Down) is supported (pin shared with secondary S/PDIF-OUT)
Supports Anti-pop mode when analog power AVDD is on and digital power is off
Power support: 3.3V digital core power; 1.5V~3.3V digital IO power for HDA link; 3.3V~5.0V
analog power; 3.3V~5.0V power stage voltage
Enhanced power management features
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
3 Track ID: JATR-1076-21 Rev. 1.1
Secondary S/PDIF-OUT supports 16/20/24-bit format and 32k/44.1k/48k/88.2k/96k/192kHz rate
Supports stereo digital microphone input
Programmable boost gain and volume control for digital microphone input
Headphone amplifier for port-A does not require DC blocking capacitors
Stereo Bridge-Tied Load Class-D amplifier at port-D has 2Watt (rms)/4Ω per channel output
Short circuit and thermal overload protection for Class D amplifier
Supports digital PWM output at port-D which system integrator can easily connect the output to
external power amplifier receives digital audio stream
Five band hardware equalizer designed for BTL output (port-D) to compensate for frequency
response while driving the mini-speaker
Intel low power ECR compliant: supports power status control, jack detection, and wake-up event in
D3 mode
48-pin QFN ‘Green’ package
2.2.
Software Features
Compatible with Windows Logo Program 3.10 and future requirements that become effective from
01 June 2008
WaveRT-based audio function driver for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio (Windows XP only)
Emulation of 26 sound environments to enhance gaming experience
Multi-band software equalizer and tools
Voice Cancellation and Key Shifting in Karaoke mode
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
4 Track ID: JATR-1076-21 Rev. 1.1
Dynamic range control (expander, compressor, and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) to enhance user experience
Provides 10-foot GUI for Windows Media Center
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
HDMI audio driver for AMD platform
Dolby® PCEE program™ (optional software feature)
SRS
®
TrueSurround HD (optional software feature)
Fortemedia
®
SAM™ technology for voice processing (Beam Forming and Acoustic Echo
Cancellation) (optional software feature)
3. System Applications
Windows Vista premium desktop and laptop PCs
Information appliances (IA) with High Definition Audio Controller
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
5 Track ID: JATR-1076-21 Rev. 1.1
4. Block Diagram
Digital Interface
Parameters
1
16h
MONO-OUT
PCM-IN1
PCM-IN2
LINE2 (port-
E)
1Bh
PCBEEP
1Dh
S/PDIF-OUT
Digital Converter
Digital Converter
S/PDIF-OUT2
32K, 44.1K, 48K, 8 8.2K, 96K,192K
32K, 44.1K, 48K, 88.2K, 96K,192K
S/PDIF-OUT
S/PDIF-OUT2
HP-OUT(Port-A)
LINE1(Port-C)
MIC1(Port-B)
MIC2(Port-F)
Sample Rate : 44.1K, 48K , 96K, 192K
-63~+1dB (1. 0dB/Step)
Digital MIC
19h
18h
LOUT2
LOUT2
LOUT1
LOUT1
1Eh
06h
Digital MIC-IN
O
DA
10h
BEEP Gen
I
1Ah
15h
PCM-OUT1
PCM-OUT2
SP-OUT2 PCM
O
M
LOUT1
LOUT2
I/O
M
Boost
LOUT1
LOUT2
I/O
M
Boost
LOUT1
LOUT2
I/O
M
Boost
A
LOUT1
LOUT2
I/O
M
Boost
-17 ~ +29dB (1dB/Step)
11h
M
MMM
M
M
MMMMM
VOL
VOL
VOL
VOL
VOL
0Bh
-34.5 ~ +12dB
(1.5dB/Step)
24h
23h
VOL
07h
08h
M
SRC
SRC
ADC Sample Rate:
44.1K, 48K, 96K
SP-OUT1 PCM
12h
ADC
VOL
M
ADC
0Ch
0Dh
M
M
DAC VOL
SRC
M
M
DAC VOL
SRC
M
LOUT1
LOUT2
03h
02h
SPK-OUT+ (Port-D)
SPK-OUT- (Port-D)
Power
Stages
Equalizer
M
2W/ch BTL Class D
14h
Cap-Free Amp
LOUT1
LOUT2
M
0Eh
M
/2
Figure 1. Block Diagram
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
6 Track ID: JATR-1076-21 Rev. 1.1
4.1.
Analog Input/Output Unit
Pin widgets NID=18h, 19h, 1Ah, and 1Bh are re-tasking IO supporting input units. NID=15h and 1Ah
support amplifier units.
A
EN_AMP
R
R
Left
EN_IBUF
EN_OBUF
Input_Signal_Left
Output_Signal_Left
Right
Output_Signal_Right
Input_Signal_Right
EN_OBUF
Figure 2. Analog Input/Output Unit
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
7 Track ID: JATR-1076-21 Rev. 1.1
5. Pin Assignments
CBP
MIC1- VREFO- L
VREF
AVSS1
AVDD1
SDAT A-OUT
BCLK
SDATA-IN
SYNC
RESET#
GPIO0/D MI C-D A T A
PD#
DVDD
CBN
CPV EE
DVDD-IO
PCBEEP
MIC1-VREFO-R
MIC2-VREFO
CPV REF
DVSS
GPI O1/D MI C-CL K
ALC269
LLLLLLL TXXXVV
HPOUT-R
HPOUT- L
1
2
3
4
5
6
7891011 12
36
35
34 33
32
31
30 29 28
27
26 25
44
43
42
41
37
38
39
40
48
47
46
45
17
18
19
20
24
23
22
21
13
14
15
16
LINE 1- L
LINE 1- R
Sense A
MIC 1 - R
MIC 1 - L
Sense B
MONO - OUT
JDREF
MIC 2 - L
MIC 2 - R
LINE 2 - L
LINE 2 - R
PVDD1
SPDIFO
PVSS2
AVDD 2
SPK- OUT- L +
AVSS2
SPK- OUT- L-
EAPD/ SPDIFO2
SPK- OUT- R-
SPK- OUT- R+
PVDD2
PVSS1
Figure 3. Pin Assignments - ALC269 (QFN-48)
5.1.
Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version number is shown
in the location marked ‘VV’.
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
8 Track ID: JATR-1076-21 Rev. 1.1
6. Pin Descriptions
6.1.
Digital I/O Pins
Table 1. Digital I/O Pins
Name Type Pin Description Characteristic Definition
RESET# I 11 H/W Reset Control Vt=0.5*DVDD
SYNC I 10 Sample Sync (48kHz) Vt=0.5*DVDD
BCLK I 6 24MHz Bit Clock Input Vt=0.5*DVDD
SDATA-OUT I 5 Serial TDM Data Input Vt=0.5*DVDD
SDATA-IN O 8 Serial TDM Data Output VOH=0.9*DVDD, VOL=0.1*DVDD
EAPD /
SPDIFO2
O 47 Signal to power down ext. amp
Secondary S/PDIF output
Output to mute/un-mute external amplifier
Output has 12 mA@75Ω driving capability.
SPDIFO O 48 S/PDIF Output
Output has 12mA@75Ω driving capability.
GPIO0 /
DMIC-DATA
IO 2 General Purpose Input/Output 0
Data input from digital MIC1&2
Input Vt=(1/2)*DVDD, output V
OH
=DVDD,
V
OL
=DVSS, internal pulled up by 50KΩ
GPIO1 /
DMIC-CLK
IO 3 General Purpose Input/Output 1
Clock output for digital MIC
Input Vt=(1/2)*DVDD, output V
OH
=DVDD,
V
OL
=DVSS, Default 2.048MHz clock output
PD# I 4
Low to Power Down Speaker
(BTL) Output
Input Vt=(1/2)*DVDD, internal pulled up by 50KΩ
Total: 10 pins
6.2.
Analog I/O Pins
Table 2. Analog I/O Pins
Name Type Pin Description Characteristic Definition
PCBEEP I 12 External PCBEEP Input Analog input, 1.6Vrms of full-scale input
LINE2-L IO 14 2nd Line Input Left Channel Analog input/output, default is input (JACK-E)
LINE2-R IO 15 2nd Line Input Right Channel Analog input/output, default is input (JACK-E)
MIC2-L IO 16 2nd Stereo Microphone Input Left Channel Analog input/output, default is input (JACK-F)
MIC2-R IO 17 2nd Stereo Microphone Input Right Channel Analog input/output, default is input (JACK-F)
MONO-OUT O 20 MONO Output Analog mono output is summation of (L+R)/2.
MIC1-L IO 21 1st Stereo Microphone Input Left Channel
Analog input/output, default is input
(JACK-B)
MIC1-R IO 22 1st Stereo Microphone Input Right Channel
Analog input/output, default is input
(JACK-B)
LINE1-L IO 23 1st Line Input Left Channel
Analog input/output, default is input
(JACK-C)
LINE1-R IO 24 1st Line Input Right Channel
Analog input/output, default is input
(JACK-C)
SPK-OUT-L+ O 40 BTL Mode Positive Left Channel Pulse width modulation output (JACK-D)
SPK-OUT-L- O 41 BTL Mode Negative Left Channel Pulse width modulation output (JACK-D)
SPK-OUT-R- O 44 BTL Mode Negative Right Channel Pulse width modulation output (JACK-D)
SPK-OUT-R+ O 45 BTL Mode Positive Right Channel Pulse width modulation output (JACK-D)
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
9 Track ID: JATR-1076-21 Rev. 1.1
Name Type Pin Description Characteristic Definition
HP-OUT-L O 32 First Out Left Channel Analog output (JACK-A)
HP-OUT-R O 33 First Out Right Channel Analog output (JACK-A)
Sense A I 13 Jack Detect Pin L
Resistor (5.1K, 10K, 20K, 39.2K) w/ 1%
accuracy
Sense B I 18 Jack Detect Pin 2
Resistor (5.1K, 10K, 20K, 39.2K) w/ 1%
accuracy
Total: 18 pins
6.3.
Filter/Reference
Table 3. Filter/Reference
Name Type Pin Description Characteristic Definition
JDREF - 19 Ref. Resistor for Jack Detect 20K, 1% accuracy resistor to analog ground
VREF - 27 2.5V Reference Voltage 1µf capacitor to analog ground
MIC1-VREFO-L O 28 Bias Voltage for MIC1 Jack 2.5V/3.2V/4.2Vreference voltage
MIC2-VREFO O 29 Bias Voltage for MIC2 Jack 2.5V/3.2V/4.2Vreference voltage
MIC1-VREFO-R O 30 Secondary Bias voltage for MIC1 jack 2.5V/3.2V/4.2Vreference voltage
CPVREF 31 0V Reference Voltage Analog ground
CBN - 35 Reference Capacitor 2.2µf capacitor to CBP
CBP - 36 Reference Capacitor 2.2µf capacitor to CBN
Total: 8 pins
6.4.
Power/Ground
Table 4. Power/Ground
Name Type Pin Description Characteristic Definition
AVDD1 P 25 Analog VDD (5.0V or 3.3V) Analog power for mixer and amplifier
AVSS1 G 26 Analog GND Analog ground for mixer and amplifier
AVDD2 P 38 Analog VDD (5.0V or 3.3V) Analog power for DACs and ADCs
AVSS2 G 37 Analog GND Analog ground for DACs and ADCs
DVDD P 1 Digital VDD (3.3V) Digital core power for core logic
DVDD-IO P 9 Digital VDD (3.3V or 1.5V) Digital I/O power for HDA link
DVSS G 7 Digital GND Digital ground
PVDD1 P 39 Power Stage VDD 5.0V Power supply for full-bridge left channel
PVSS1 G 42 Power Stage GND Ground for full-bridge left channel
PVSS2 G 43 Power Stage GND Ground for full-bridge right channel
PVDD2 P 46 Power Stage VDD 5.0V Power supply for full-bridge right channel
CPVEE P 34 Reference Voltage Output 2.2µf capacitor to analog ground
Total: 12 pins
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
10 Track ID: JATR-1076-21 Rev. 1.1
7. High Definition Audio Link Protocol
7.1.
Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Figure 4. HDA Link Protocol
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
11 Track ID: JATR-1076-21 Rev. 1.1
7.1.1. Signal Definitions
Table 5. Link Signal Definitions
Item Description
BCLK 24.0MHz bit clock sourced from the HDA controller and connected to all codecs.
SYNC
48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
SDO
Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are
carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec
samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at
least one SDO. To extend outbound bandwidth, multiple SDOs may be supported.
SDI
Serial Data Input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be
supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at
each rising edge of BCLK. SDI can be driven by the controller to initialize the codec’s ID.
RST#
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Signal Name Source Controller Type Description
BCLK Controller Output Global 24.0MHz Bit Clock.
SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal.
SDO Controller Output Serial Data Output from Controller.
SDI Codec/Controller Input/Output
Serial Data Input from codec. Weakly pulled down by the
controller.
RST# Controller Output Global Active Low Reset Signal.
SDO
SYNC
SDI
BCLK
Start of Frame
8-Bit Frame SYNC
7654 0123 999 998997 996 995 994 993 992 991 990
3210 499
498
497 496 495 494
Controller samples SDI at rising edge of BCLK
Codec samples SDO at both rising and falling edge of BCLK
Figure 5. Bit Timing
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
12 Track ID: JATR-1076-21 Rev. 1.1
7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 6 shows the possible connections between the HDA controller and codecs:
• Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
• Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
• Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
• Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 13 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC269 is
designed to receive a single SDO stream.
RST#
BCLK
SYNC
SDO0
SDI0
Codec 0
RST#
BCLK
SYNC
SDO0
SDO1
SDI0
Codec 1
RST#
BCLK
SYNC
SDO0
SDI1
Codec 2
HDA
Controller
RST#
BCLK
SYNC
SDO0
SDO1
SDI0
SDI2
SDI14
RST#
BCLK
SYNC
SDO0
SDO1
SDI1
Codec N
SDI0
SDI0
SDI1
SDI13
. . .
.
.
.
.
.
.
Single SDO
Single SDI
Two SDOs
Single SDI
Single SDO
Two SDIs
SDI2
Two SDOs
Multiple SDIs
Figure 6. Signaling Topology
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
13 Track ID: JATR-1076-21 Rev. 1.1
7.2.
Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 7).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 8).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
Command Stream
SDO
SYNC
A 48kHz Frame is composed of Command stream and multiple Data streams
Stream 'X' DataStream 'A' Data
Stream 'A' Tag Stream 'X' Tag
Frame SYNC
(Here 'A' = 5) (Here 'X' = 6)
Next FramePrevious Frame
0s
Null Field
Sample Block(s)
Block 1
Block 2
..
.
Block Y
Sample 1 Sample 2
..
.
Sample Z
msb
...
lsb
For 48kHz rate, only Block1 is included
One or multiple blocks in a stream
For 96kHz rate, Block1 includes (N)
th
time of samples, Block2
includes (N+1)
th
time of samples
Z channels of PCM Sample
msb first in a sample
Padded at the
end of Frame
Figure 7. SDO Outbound Frame
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
14 Track ID: JATR-1076-21 Rev. 1.1
SDO
SYNC
BCLK
Data of Stream 10
7654 0123
Preamble
Stream=10
110
0
msb lsb
msb
Previous Stream
Stream Tag
(4-Bit) (4-Bit)
Figure 8. SDO Stream Tag is Indicated in SYNC
7.2.2. Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the stripe control bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 9) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not striped. It
is always transmitted on SDO0, and copied on SDO1.
Figure 9. Striped Stream on Multiple SDOs
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
15 Track ID: JATR-1076-21 Rev. 1.1
7.2.3. Inbound Frame – Single SDI
An Inbound Frame – Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 10).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 11).
Response Stream
SDI
SYNC
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Stream 'X'
Stream 'A'
Frame SYNC
Next FramePrevious Frame
0s
Null Field
Sample 1 Sample 2 ... Sample Z
msb ... lsb
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)
th
(N+1)th} time of samples
Z channels of PCM Sample
msb first in a sample
Padded at the end of Frame
Sample Block(s)Stream Tag
Block 1
Block 2
... Block Y
Null Pad
Figure 10. SDI Inbound Stream
BCLK
SDI
Data Length in Bytes
D
n-1
00
00
Stream Tag
B
0
D
n-2
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
D
0
(Data Length in Bytes *8)-Bit
Next Stream
Null Pad
n-Bit Sample Block
A Complete Stream
Figure 11. SDI Stream Tag and Data
ALC269
Datasheet
High Definition Audio Codec with Embedded
Class D Speaker Amplifier
16 Track ID: JATR-1076-21 Rev. 1.1
7.2.4. Inbound Frame – Multiple SDI
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
Response Stream
SDI
0
SYNC
Stream 'X'
Frame SYNC
SDI
1
0s
Tag A
Stream A, B, X, and Y are independent and have separate IDs
Data A
Tag B Data B
Codec drives SDI
0
and SDI
1
Stream 'A'
Stream 'B'
Response Stream
0s
Stream 'Y'
Figure 12. Codec Transmits Data Over Multiple SDIs
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 17, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 17, shows the delivery cadence
of variable rates based on 48kHz.
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames.
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