Realtek ALC268-GR, ALC268Q-GR Schematics
ALC268-GR
ALC268Q-GR
2+2 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.0
04 September 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
ALC268 Series
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC268 Series Audio Codecs.
Though every effort has been made to assure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2006/09/04 First release.
2+2 Channel High Definition Audio Codec ii Track ID: JATR-1076-21 Rev. 1.0
ALC268 Series
Datasheet
Table of Contents
1. General Description .................................................................................................... 1
2. Features ........................................................................................................................2
2.1. HARDWARE FEATURES.....................................................................................................................2
2.2. S
3. System Applications .................................................................................................... 3
4. Block Diagram ............................................................................................................. 4
4.1. ANALOG INPUT/OUTPUT UNIT .........................................................................................................4
5. Pin Assignments........................................................................................................... 5
5.1. ALC268-GR (LQFP-48)..................................................................................................................5
5.2. ALC268Q-GR (QFN-48) ................................................................................................................6
5.3. GREEN PACKAGE AND VERSION IDENTIFICATION ............................................................................6
OFTWARE FEATURES ......................................................................................................................3
6. Pin Descriptions........................................................................................................... 7
6.1. DIGITAL I/O PINS .............................................................................................................................7
6.2. ANALOG I/O PINS.............................................................................................................................8
6.3. FILTER/REFERENCE/NOT CONNECTED .............................................................................................9
6.4. POWER/GROUND ..............................................................................................................................9
7. High Definition Audio Link Protocol ...................................................................... 10
7.1. LINK SIGNALS ................................................................................................................................10
7.1.1. Signal Definitions.................................................................................................................................................11
7.1.2. Signaling Topology...............................................................................................................................................12
7.2. F
7.3. R
7.4. VERB AND RESPONSE FORMAT.......................................................................................................22
7.5. POWER MANAGEMENT ...................................................................................................................23
RAME COMPOSITION.....................................................................................................................13
7.2.1. Outbound Frame – Single SDO............................................................................................................................13
7.2.2. Outbound Frame – Multiple SDO ........................................................................................................................14
7.2.3. Inbound Frame – Single SDI................................................................................................................................15
7.2.4. Inbound Frame – Multiple SDI ............................................................................................................................16
7.2.5. Variable Sample Rates..........................................................................................................................................16
ESET AND INITIALIZATION............................................................................................................19
7.3.1. Link Reset.............................................................................................................................................................19
7.3.2. Codec Reset..........................................................................................................................................................20
7.3.3. Codec Initialization Sequence ..............................................................................................................................21
7.4.1. Command Verb Format ........................................................................................................................................22
7.4.2. Response Format..................................................................................................................................................22
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ALC268 Series
Datasheet
8. Supported Verbs and Parameters............................................................................ 24
8.1. VERB – GET PARAMETERS (VERB ID=F00H) .................................................................................24
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................24
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................24
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................25
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................26
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................26
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................27
8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................28
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................29
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................30
8.1.10. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................31
8.1.11. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................31
8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................32
8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................32
8.1.14. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................32
8.1.15. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................33
8.1.16. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................33
8.2. V
8.3. V
8.4. VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................35
8.5. VERB – GET PROCESSING STATE (VERB ID=F03H)........................................................................38
8.6. VERB – SET PROCESSING STATE (VERB ID=703H) ........................................................................38
8.7. VERB – GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................39
8.8. VERB – SET COEFFICIENT INDEX (VERB ID=5H)............................................................................39
8.9. VERB – GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................40
8.10. VERB – SET PROCESSING COEFFICIENT (VERB ID=4H) ..................................................................40
8.11. VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................41
8.12. VERB – SET AMPLIFIER GAIN (VERB ID=3H).................................................................................45
8.13. VERB – GET CONVERTER FORMAT (VERB ID=AH)........................................................................46
8.14. VERB – SET CONVERTER FORMAT (VERB ID=2H) .........................................................................47
8.15. VERB – GET POWER STATE (VERB ID=F05H)................................................................................48
8.16. VERB – SET POWER STATE (VERB ID=705H).................................................................................48
8.17. V
8.18. VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................49
8.19. V
8.20. VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................51
8.21. VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................52
8.22. V
8.23. V
8.24. VERB – EXECUTE PIN SENSE (VERB ID=709H) ..............................................................................53
8.25. VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................54
8.26. VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
8.27. VERB – GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................55
8.28. VERB – SET BEEP GENERATOR (VERB ID=70AH) ........................................................................55
8.29. VERB – GET GPIO DATA (VERB ID=F15H) ...................................................................................56
8.30. VERB – SET GPIO DATA (VERB ID=715H)....................................................................................56
ERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................34
ERB – SET CONNECTION SELECT (VERB ID=701H) .....................................................................34
ERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................49
ERB – GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................50
ERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................52
ERB – GET PIN SENSE (VERB ID=F09H) ......................................................................................53
BYTES 0, 1, 2, 3).............................................................................................................................54
2+2 Channel High Definition Audio Codec iv Track ID: JATR-1076-21 Rev. 1.0
ALC268 Series
Datasheet
8.31. VERB – GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................57
8.32. VERB – SET GPIO ENABLE MASK (VERB ID=716H)......................................................................57
8.33. VERB – GET GPIO DIRECTION (VERB ID=F17H)...........................................................................58
8.34. VERB – SET GPIO DIRECTION (VERB ID=717H)............................................................................58
8.35. VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).............................59
8.36. VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H).............................59
8.37. VERB – FUNCTION RESET (VERB ID=7FFH) ..................................................................................60
8.38. VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)..............61
8.39. VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)................62
8.40. GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH)............................................................63
8.41. GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0])......................63
9. Electrical Characteristics ......................................................................................... 64
9.1. DC
9.1.1. Absolute Maximum Ratings..................................................................................................................................64
9.1.2. Threshold Voltage .................................................................................................................................................64
9.1.3. Digital Filter Characteristics ...............................................................................................................................65
9.1.4. S/PDIF Output Characteristics ............................................................................................................................65
CHARACTERISTICS ...................................................................................................................64
9.2. AC CHARACTERISTICS ...................................................................................................................66
9.2.1. Link Reset and Initialization Timing.....................................................................................................................66
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................67
9.2.3. S/PDIF Output Timing..........................................................................................................................................68
9.2.4. Test Mode..............................................................................................................................................................68
9.3. ANALOG PERFORMANCE ................................................................................................................69
10. Application Notes ...................................................................................................... 70
10.1. APPLICATION CIRCUITS..................................................................................................................70
10.2. DIGITAL MICROPHONE IMPLEMENTATION......................................................................................73
11. Mechanical Dimensions ............................................................................................ 74
11.1. LQFP-48 MECHANICAL DIMENSIONS ............................................................................................74
11.2. LQFP-48 MECHANICAL DIMENSIONS NOTES.................................................................................75
11.3. QFN-48
MECHANICAL DIMENSIONS ..............................................................................................76
12. Ordering Information ............................................................................................... 77
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ALC268 Series
Datasheet
List of Tables
Table 1. Digital I/O Pins ...........................................................................................................................7
Table 2. Analog I/O Pins...........................................................................................................................8
Table 3. Filter/Reference...........................................................................................................................9
Table 4. Power/Ground.............................................................................................................................9
Table 5. Link Signal Definitions.............................................................................................................11
Table 6. HDA Signal Definitions............................................................................................................11
Table 7. Defined Sample Rate and Transmission Rate...........................................................................17
Table 8. 48kHz Variable Rate of Delivery Timing .................................................................................17
Table 9. 44.1kHz Variable Rate of Delivery Timing ..............................................................................18
Table 10. 40-Bit Commands in 4-Bit Verb Format...................................................................................22
Table 11. 40-Bit Commands in 12-Bit Verb Format.................................................................................22
Table 12. Solicited Response Format .......................................................................................................22
Table 13. Unsolicited Response Format ...................................................................................................22
Table 14. System Power State Definitions ...............................................................................................23
Table 15. Power Controls in NID=01h.....................................................................................................23
Table 16. Powered Down Conditions .......................................................................................................23
Table 17. Verb – Get Parameters (Verb ID=F00h) ...................................................................................24
Table 18. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h) ...................................................24
Table 19. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................24
Table 20. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................25
Table 21. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................26
Table 22. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................26
Table 23. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................27
Table 24. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................28
Table 25. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................29
Table 26. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................30
Table 27. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....31
Table 28. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...31
Table 29. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................32
Table 30. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................32
Table 31. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................32
Table 32. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................33
Table 33. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................33
Table 34. Verb – Get Connection Select Control (Verb ID=F01h)...........................................................34
Table 35. Verb – Set Connection Select (Verb ID=701h).........................................................................34
Table 36. Verb – Get Connection List Entry (Verb ID=F02h)..................................................................35
Table 37. Verb – Get Processing State (Verb ID=F03h)...........................................................................38
Table 38. Verb – Set Processing State (Verb ID=703h) ............................................................................38
Table 39. Verb – Get Coefficient Index (Verb ID=Dh).............................................................................39
Table 40. Verb – Set Coefficient Index (Verb ID=5h) ..............................................................................39
Table 41. Verb – Get Processing Coefficient (Verb ID=Ch).....................................................................40
Table 42. Verb – Set Processing Coefficient (Verb ID=4h) ......................................................................40
Table 43. Verb – Get Amplifier Gain (Verb ID=Bh) ................................................................................41
Table 44. Verb – Set Amplifier Gain (Verb ID=3h)..................................................................................45
2+2 Channel High Definition Audio Codec vi Track ID: JATR-1076-21 Rev. 1.0
ALC268 Series
Datasheet
Table 45. Verb – Get Converter Format (Verb ID=Ah)............................................................................46
Table 46. Verb – Set Converter Format (Verb ID=2h)..............................................................................47
Table 47. Verb – Get Power State (Verb ID=F05h) ..................................................................................48
Table 48. Verb – Set Power State (Verb ID=705h) ...................................................................................48
Table 49. Verb – Set Converter Stream, Channel (Verb ID=706h)...........................................................49
Table 50. Verb – Get Pin Widget Control (Verb ID=F07h) ......................................................................50
Table 51. Verb – Set Pin Widget Control (Verb ID=707h) .......................................................................51
Table 52. Verb – Get Unsolicited Response Control (Verb ID=F08h) .....................................................52
Table 53. Verb – Set Unsolicited Response Control (Verb ID=708h) ......................................................52
Table 54. Verb – Get Pin Sense (Verb ID=F09h)......................................................................................53
Table 55. Verb – Execute Pin Sense (Verb ID=709h)...............................................................................53
Table 56. Verb – Get Configuration Default (Verb ID=F1Ch) .................................................................54
Table 57. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................54
Table 58. Verb – Get BEEP Generator (Verb ID=F0Ah)..........................................................................55
Table 59. Verb – Set BEEP Generator (Verb ID=70Ah)...........................................................................55
Table 60. Verb – Get GPIO Data (Verb ID=F15h) ...................................................................................56
Table 61. Verb – Set GPIO Data (Verb ID=715h) ....................................................................................56
Table 62. Verb – Get GPIO Enable Mask (Verb ID=F16h)......................................................................57
Table 63. Verb – Set GPIO Enable Mask (Verb ID=716h).......................................................................57
Table 64. Verb – Get GPIO Direction (Verb ID=F17h)............................................................................58
Table 65. Verb – Set GPIO Direction (Verb ID=717h).............................................................................58
Table 66. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................59
Table 67. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)...................................59
Table 68. Verb – Function Reset (Verb ID=7FFh)....................................................................................60
Table 69. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh).........................61
Table 70. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................62
Table 71. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh) ..............................................................63
Table 72. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0]) ..........................63
Table 73. Absolute Maximum Ratings .....................................................................................................64
Table 74. Threshold Voltage .....................................................................................................................64
Table 75. Digital Filter Characteristics.....................................................................................................65
Table 76. S/PDIF Input/Output Characteristics ........................................................................................65
Table 77. Link Reset and Initialization Timing ........................................................................................66
Table 78. Link Timing Parameters at the Codec.......................................................................................67
Table 79. S/PDIF Output Timing..............................................................................................................68
Table 80. Analog Performance .................................................................................................................69
Table 81. Ordering Information................................................................................................................77
2+2 Channel High Definition Audio Codec vii Track ID: JATR-1076-21 Rev. 1.0
ALC268 Series
Datasheet
List of Figures
Figure 1. Block Diagram ..........................................................................................................................4
Figure 2. Analog Input/Output Unit .........................................................................................................4
Figure 3. Pin Assignments ALC268-GR (LQFP-48)................................................................................5
Figure 4. Pin Assignments ALC268Q-GR (QFN-48)...............................................................................6
Figure 5. HDA Link Protocol .................................................................................................................10
Figure 6. Bit Timing ...............................................................................................................................11
Figure 7. Signaling Topology .................................................................................................................12
Figure 8. SDO Outbound Frame.............................................................................................................13
Figure 9. SDO Stream Tag is Indicated in SYNC ..................................................................................13
Figure 10. Stripped Stream on Multiple SDOs.........................................................................................14
Figure 11. SDI Inbound Stream................................................................................................................15
Figure 12. SDI Stream Tag and Data ........................................................................................................15
Figure 13. Codec Transmits Data Over Multiple SDIs.............................................................................16
Figure 14. Link Reset Timing...................................................................................................................20
Figure 15. Codec Initialization Sequence.................................................................................................21
Figure 16. Link Reset and Initialization Timing.......................................................................................66
Figure 17. Link Signals Timing ................................................................................................................67
Figure 18. Output Timing .........................................................................................................................68
Figure 19. Filter Connection.....................................................................................................................70
Figure 20. Power and Rear Panel Jack Connection..................................................................................71
Figure 21. Front Panel Header and Front Panel I/O Cable.......................................................................72
Figure 22. S/PDIF-OUT Connection........................................................................................................72
Figure 23. Digital Microphone Implementation-1....................................................................................73
Figure 24. Digital Microphone Implementation-2....................................................................................73
2+2 Channel High Definition Audio Codec viii Track ID: JATR-1076-21 Rev. 1.0
ALC268 Series
Datasheet
1. General Description
The ALC268 series are 4-Channel High Definition Audio Codecs with UAA (Universal Audio
Architecture), featuring two stereo DACs and two stereo ADCs. The 4 channels of DAC support stereo
sound playback on the rear panel and independent stereo sound output on the front panel simultaneously
(multiple streaming). The two stereo ADCs integrate two stereo and independent analog sound inputs.
The ALC268 series incorporates Realtek proprietary converter technology to achieve 95dB dynamic
range playback quality and 90dB dynamic range recording quality. They are designed for Windows Vista
premium desktop and laptop systems.
The ALC268 series also supports up to 4 digital microphone channels (microphone array) with Acoustic
Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,
significantly improving sound quality for PC VoIP applications.
The S/PDIF output offers easy connection of PCs to high quality consumer electronic products such as
digital decoders and speakers.
The ALC268 supports host/soft audio from the Intel ICH chipset, and also from any other HDA
compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities like Karaoke mode, environment emulation, and software equalizer audio technology to
provide an excellent entertainment package and game experience for PC users.
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
1
ALC268 Series
2. Features
2.1.
Hardware Features
95dB SNR DACs meet Windows Vista Premium requirement
90dB SNR ADCs meet Windows Vista Premium requirement
Two stereo DACs support 16/20/24-bit PCM format for stereo audio playback
Two stereo ADCs support 16/20-bit PCM format for two stereo independent sound inputs
All DACs supports 44.1k/48K/96k/192kHz sample rate
All ADCs support 44.1k/48k/96kHz sample rate
16/20/24-bit S/PDIF-OUT supports 44.1k/48k/88.2k/96k/192kHz sample rate
Up to four channels of digital microphone input are supported
Supports MONO line output with independent volume control
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Datasheet
Software selectable 2.5V/3.75V/4.2V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
1dB resolution of analog output volume control
Programmable 20dB and 40dB boost for analog microphone input
Supports hardware digital volume control for digital microphone input
Built-in headphone amplifiers for port-A and port-D
4 GPIOs (GPIO0/GPIO3 are digital GPIO shared with digital MIC interface, GPIO1/GPIO2 are
analog) for customized applications
EAPD (External Amplifier Power Down) is supported
Supports Anti-pop mode when analog power AVDD is on and digital power is off.
Power support: 3.3V digital core power; 1.5V~3.3V digital IO power for HDA link; 3.3V~5.0V
analog power
Power management features
48-pin LQFP ‘Green’ package
48-pin QFN ‘Green’ package
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
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ALC268 Series
Datasheet
2.2.
Software Features
Meets Microsoft WLP 3.0x audio requirements
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
A3D™ compatible
I3DL2 compatible
HRTF 3D Positional Audio
Emulation of 26 sound environments to enhance gaming experience
10 Software Equalizer Bands
Voice Cancellation and Key Shifting in Karaoke mode
Realtek Media Player
Enhanced Configuration Panels (2 feet UI and 10 feet UI for Media Center)
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice applications
3. System Applications
Windows Vista premium desktop and laptop PCs
Information appliances (IA) with High Definition Audio Controller
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
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4. Block Diagram
ALC268 Series
Datasheet
Figure 1. Block Diagram
4.1.
Analog Input/Output Unit
Pin widgets NID=14h, 15h, 18h and 1Ah are re-tasking IO support input unit, NID=14h and 15h support
amplifier unit.
R
Output_Signal_Left
Output_Signal_Right
Input_Signal_Left
Input_Signal_Right
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
R
Figure 2. Analog Input/Output Unit
EN_OBUF
4
A
EN_AMP
EN_OBUF
EN_IBUF
Left
Right
5. Pin Assignments
5.1.
ALC268-GR (LQFP-48)
ALC268 Series
Datasheet
Figure 3. Pin Assignments ALC268-GR (LQFP-48)
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
5
5.2.
ALC268Q-GR (QFN-48)
ALC268 Series
Datasheet
Figure 4. Pin Assignments ALC268Q-GR (QFN-48)
5.3.
Green Package and Version Identification
The ALC268 series includes the parts listed in section 12 Ordering Information, page 77.
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 4. The version number is shown
in the location marked ‘VV’.
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
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6. Pin Descriptions
6.1.
Digital I/O Pins
Table 1. Digital I/O Pins
Name Type ALC268-GR
(LQFP-48)
Pin No.
RESET# I 11 11 H/W reset control Vt=0.5*DVDD
SYNC I 10 10 Sample Sync (48kHz) Vt=0.5*DVDD
BCLK I 6 6 24MHz Bit clock input Vt=0.5*DVDD
SDATA-OUT I 5 5 Serial TDM data input Vt=0.5*DVDD
SDATA-IN O 8 8
EAPD O 47 47
SPDIFO O 48 48 S/PDIF output
GPIO0 /
DMIC-12
GPIO3 /
DMIC-34
DMIC-CLK O 46 46
Total 10 pins 10 pins
I/O 2 2
I/O 3 4
ALC268Q-GR
(QFN-48)
Pin No.
Description Characteristic Definition
Serial TDM data
output
Signal to power down
ext. amp
General Purpose
Input/Output 0
Data input from digital
MIC 1&2
General Purpose
Input/Output 3
Data input from digital
MIC 3&4
Clock output for
digital MIC
VOH=0.9*DVDD, VOL=0.1*DVDD
Output VOH=DVDD, VOL=DVSS
Output has 12mA@75Ω driving capability.
Input Vt=(2/3)*DVDD, output V
=DVSS, internal pulled up by 50KΩ
V
OL
Input Vt=(2/3)*DVDD, output V
=DVSS, internal pulled up by 50KΩ
V
OL
Default 2.048MHz clock output
ALC268 Series
Datasheet
=DVDD,
OH
=DVDD,
OH
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ALC268 Series
Datasheet
6.2.
Analog I/O Pins
Table 2. Analog I/O Pins
Name Ty pe ALC268-GR
(LQFP-48)
Pin No.
MIC2-L I/O 16 16
MIC2-R I/O 17 17
CD-L I 18 18 CD input left channel Analog input, 1.6Vrms of full scale input
CD-G I 19 19
CD-R I 20 20 CD input right channel Analog input, 1.6Vrms of full scale input
MIC1-L I/O 21 21
MIC1-R I/O 22 22
LINE1-L I/O 23 23
LINE1-R I/O 24 24
PCBEEP I 12 pin 12 pin External PCBEEP input Analog input, 1.6Vrms of full scale input
LINE-OUT-L I/O 35 35 Line output left channel Analog output (PORT –D)
LINE-OUT-R I/O 36 36
HP-OUT-L I/O 39 39
HP-OUT-R I/O 41 41
MONO-OUT O 37 32 MONO output
Sense A I 13 13 Jack Detect pin l
Sense B I 34 34 Jack Detect pin 2
GPIO1 I/O 31 31
GPIO2 I/O - 30
Total 18 pins 19 pins
ALC268Q-GR
(QFN-48)
Pin No.
Description Characteristic Definition
nd
stereo microphone
2
input left channel
nd
stereo microphone
2
input right channel
CD input reference
ground
st
stereo microphone
1
input left channel
st
stereo microphone
1
input right channel
st
line input left
1
channel
st
line input right
1
channel
Line output right
channel
Headphone out left
channel
Headphone out right
channel
General Purpose
Input/Output 1
General Purpose
Input/Output 2
Analog input/output, default is input
(PORT –F)
Analog input/output, default is input
(PORT –F)
Analog input, 1.6Vrms of full scale input
Analog input/output, default is input
(PORT –B)
Analog input/output, default is input
(PORT –B)
Analog input/output, default is input
(PORT –C)
Analog input/output, default is input
(PORT –C)
Analog output (PORT –D)
Analog output (PORT –A)
Analog output (PORT –A)
Analog mono output is summation of
(L+R)/2
Resistor {5.1K, 10K, 20K, 39.2K} w/ 1%
accuracy
Resistor {5.1K, 10K, 20K, 39.2K} w/ 1%
accuracy
Input Vt=(2/3)*AVDD, output V
V
Input Vt=(2/3)*AVDD, output V
V
=AVSS, internal pulled up by 50KΩ
OL
=AVSS, internal pulled up by 50KΩ
OL
=AVDD,
OH
=AVDD,
OH
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ALC268 Series
Datasheet
6.3.
Filter/Reference/Not Connected
Table 3. Filter/Reference
Name Type ALC268-GR
(LQFP-48)
Pin No.
VREF - 27 27 2.5V Reference voltage 1uf capacitor to analog ground
MIC1-VREFO-L O 28 28 Bias voltage for MIC1 jack 2.5V/3.2/4.2Vreference voltage
LINE1-VREFO O 29 29
MIC2-VREFO O 30 - Bias voltage for MIC2 jack 2.5V/3.2/4.2Vreference voltage
MIC1-VREFO-R O 32 - Bias voltage for MIC1 jack 2.5V/3.2/4.2Vreference voltage
JDREF - 40 33 Ref. resistor for Jack Detect 20K, 1% resistor to analog ground
NC - 14 14 Not Connected
NC - 15 15 Not Connected
NC - 33 37 Not Connected
NC - 43 43 Not Connected
NC - 44 44 Not Connected
NC - 45 45 Not Connected
NC - - 40 Not Connected
Total 12 pins 11 pins
ALC268Q-GR
(QFN-48)
Pin No.
Description Characteristic Definition
Bias voltage for LINE1
jack
2.5V/3.2/4.2Vreference voltage
6.4.
Power/Ground
Table 4. Power/Ground
Name Type ALC268-GR
(LQFP-48)
Pin No
AVDD1 I 25 25 Analog VDD (5V or 3.3V) Analog power for mixer and amplifier
AVSS1 I 26 26 Analog GND Analog ground for mixer and amplifier
AVDD2 I 38 38 Analog VDD (5V or 3.3V) Analog power for DACs and ADCs
AVSS2 I 42 42 Analog GND Analog ground for DACs and ADCs
DVDD I 1 1 Digital VDD (3.3V) Digital power
DVSS I 4 - Digital GND Digital ground
DVDD-IO I 9 3 Digital VDD (1.5V~3.3V) Scalable digital power for HDA link.
DVSS I 7 7 Digital GND Digital ground
DVDD I - 9 Digital VDD (3.3V) Digital power
Total 8 pins 8 pins
ALC268Q-GR
(QFN-48)
Pin No.
Description Characteristic Definition
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ALC268 Series
Datasheet
7. High Definition Audio Link Protocol
7.1.
Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 5 shows the basic concept of the HDA link protocol.
Previous Frame
BCLK
SYNC
SDO
SDI
RST#
Frame SYNC= 8 BCLK
Command Stream
(40-bit data)
Response Stream
(36-bit data)
T
frame_sync
Stream 'A' Tag
Stream 'A' Data
= 20.833 µs (48KHz)
(Here 'A' = 5)
Stream
'C' Tag
(n bytes + 10-bit data)
Figure 5. HDA Link Protocol
Next Frame
Stream 'B' Tag
(Here 'B' = 6)
Stream 'B' Data
Stream 'C' Data
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7.1.1. Signal Definitions
Table 5. Link Signal Definitions
Item Description
BCLK 24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs.
SYNC
SDO
SDI
RST#
Signal Name Source Type for Controller Description
BCLK Controller Output Global 24.0MHz bit clock.
SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal.
SDO Controller Output Serial data output from controller.
SDI Codec/Controller Input/Output
RST# Controller Output Global active low reset signal.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDI’s can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codec’s ID.
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.
Table 6. HDA Signal Definitions
Serial data input from codec. Weakly pulled down by the
controller.
ALC268 Series
Datasheet
BCLK
SYNC
SDO
SDI
Controller samples SDI at rising edge of BCLK
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
8-Bit Frame SYNC
Start of Frame
7654 0123 999 998 997 996995 994 993 992 991 990
3 2 1 0 499
Codec samples SDO at both rising and falling edge of BCLK
Figure 6. Bit Timing
11
498
497 496 495 494
ALC268 Series
Datasheet
7.1.2. Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 7 shows the possible connections between the HDA controller and codecs:
Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 13 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 7 can be implemented concurrently in an HDA system. The ALC268 is
designed to receive a single SDO stream.
HDA
Controller
SDI14
.
.
.
SDI13
SDI2
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#
SYNC
RST#
BCLK
Codec 0
Single SDO
Single SDI
.
.
.
SDO0
SDI0
SYNC
BCLK
RST#
Codec 1
Two SDOs
Single SDI
SDO0
SDO1
SDI0
SYNC
BCLK
RST#
Codec 2
Single SDO
Two SDIs
SDO0
SDI1
SDI0
. . .
SYNC
BCLK
RST#
Codec N
Two SDOs
Multiple SDIs
SDO0
SDO1
SDI0
SDI1
SDI2
Figure 7. Signaling Topology
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ALC268 Series
Datasheet
7.2.
Frame Composition
7.2.1. Outbound Frame – Single SDO
An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 8).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 9).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
SYNC
SDO
A 48kHz Frame is composed of Command stream and multiple Data streams
Frame SYNC
Command Stream
Sample Block(s)
Block 1
Sample 1 Sample 2
msb
Block 2
...
BCLK
SYNC
Stream 'A' Tag Stream 'X' Tag
(Here 'A' = 5) (Here 'X' = 6)
One or multiple blocks in a stream
..
.
..
.
msb first in a sample
lsb
Figure 8. SDO Outbound Frame
Block Y
Sample Z
Stream Tag
msb lsb
Stream 'X' DataStream 'A' Data
Null Field
For 48kHz rate, only Block1 is included
For 96kHz rate, Block1 includes (N)
includes (N+1)
Z channels of PCM Sample
0
110
time of samples
th
th
Next FramePrevious Frame
0s
Padded at the
end of Frame
time of samples, Block2
Stream=10
Data of Stream 10
msb
SDO
Preamble
(4-Bit) (4-Bit)
7654 0123
Previous Stream
Figure 9. SDO Stream Tag is Indicated in SYNC
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ALC268 Series
Datasheet
7.2.2. Outbound Frame – Multiple SDO
The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the ‘Strip Control’ bit in the controller’s Output Stream Control Register to initiate a
specific stream (Stream ‘A’ in Figure 10) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not stripped. It
is always transmitted on SDO0, and copied on SDO1.
SYNC
SDO
SDO
0
1
Stream 'A' Tag
Frame SYNC
Command Stream
Command Stream
Command Stream is unchanged, not stripped
Stream 'A' to Codec A
D
D
n
n-2
. . .
D
D
n-3
n-1
Stream A is "bit-stripped" on SDO0 and SDO1
Figure 10. Stripped Stream on Multiple SDOs
. . .
. . .
Stream 'X' Tag
Stream 'X' to Codec X
0s
Stream 'Y' Tag
Stream 'Y' to Codec Y
0s
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ALC268 Series
Datasheet
7.2.3. Inbound Frame – Single SDI
An Inbound Frame – Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 11).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 12).
SYNC
SDI
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Frame SYNC
Response Stream
Sample Block(s)Stream Tag
Block 1
Sample 1 Sample 2 ... Sample Z
Block 2
msb ... lsb
... Block Y
msb first in a sample
Figure 11. SDI Inbound Stream
Stream 'A'
Null Pad
For 48kHz rate, only Block1 is included
For 96kHz rate, Block{1, 2} includes {(N)
Z channels of PCM Sample
Stream 'X'
Null Field
Next FramePrevious Frame
0s
Padded at the end of Frame
(N+1)th} time of samples
th
BCLK
SDI
Stream Tag
B
B
8
9
Data Length in Bytes
B
B
B
B
B
B
B
7
5
6
3
4
1
2
n-Bit Sample Block
D
n-1
D
n-2
B
0
D
0
(Data Length in Bytes *8)-Bit
A Complete Stream
Figure 12. SDI Stream Tag and Data
Null Pad
00
Next Stream
00
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ALC268 Series
Datasheet
7.2.4. Inbound Frame – Multiple SDI
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
SDI
0
SDI
1
Codec drives SDI
Response Stream
Response Stream
and SDI
0
1
Tag A
Tag B Data B
Figure 13. Codec Transmits Data Over Multiple SDIs
Stream 'A'
Data A
Stream 'B'
Stream A, B, X, and Y are independent and have separate IDs
Stream 'X'
0s
Stream 'Y'
0s
7.2.5. Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 17, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 17, shows the delivery cadence
of variable rates based on 48kHz.
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ALC268 Series
Datasheet
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
“12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)”
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 9, page 18).
Table 7. Defined Sample Rate and Transmission Rate
(Sub) Multiple 48kHz Base 44.1kHz Base
1/6 8kHz (1 sample block every 6 frames)
1/4 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames)
1/3 16kHz (1 sample block every 3 frames)
1/2 22.05kHz (1 sample block every 2 frames)
2/3 32kHz (2 sample blocks every 3 frames)
1 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame)
2 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame)
4 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)
Table 8. 48kHz Variable Rate of Delivery Timing
Rate Delivery Cadence Description
8kHz YNNNNN (repeat) One sample block is transmitted in every 6 frames
12kHz YNNN (repeat) One sample block is transmitted in every 4 frames
16kHz YNN (repeat) One sample block is transmitted in every 3 frames
32kHz Y2NN (repeat) One sample block is transmitted in every 6 frames
48kHz Y (repeat) One sample block is transmitted in every 6 frames
96kHz Y2 (repeat) Two sample blocks are transmitted in each frame
192kHz Y4 (repeat) Four sample blocks are transmitted in each frame
N: No sample block in a frame
Y: One sample block in a frame
x
Y
: X sample blocks in a frame
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ALC268 Series
Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing
Rate Delivery Cadence
11.025kHz
22.05kHz
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.
88.2kHz 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.
176.4kHz 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.
2+2 Channel High Definition Audio Codec Track ID: JATR-1076-21 Rev. 1.0
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