Rainbow Electronics W25X64 User Manual
W25X16, W25X32, W25X64
16M-BIT, 32M-BIT, AND 64M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL OUTPUT SPI
Publication Release Date: June 28, 2006
- 1 - Preliminary - Revision B
W25X16, W25X32, W25X64
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 4
2. FEATURES................................................................................................................................. 4
3. PIN CONFIGURATION SOIC 208-MIL....................................................................................... 5
4. PIN CONFIGURATION WSON 6X5-MM.................................................................................... 5
5. PIN CONFIGURATION PDIP 300-MIL.......................................................................................6
6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL, AND WSON 6X5-MM............................... 6
7. PIN CONFIGURATION SOIC 300-MIL....................................................................................... 7
8. PIN DESCRIPTION SOIC 300-MIL ............................................................................................ 7
8.1 Package Types............................................................................................................... 8
8.2 Chip Select (/CS)............................................................................................................ 8
8.3 Serial Data Output (DO) ................................................................................................. 8
8.4 Write Protect (/WP)......................................................................................................... 8
8.5 HOLD (/HOLD) ............................................................................................................... 8
8.6 Serial Clock (CLK).......................................................................................................... 8
8.7 Serial Data Input / Output (DIO) ..................................................................................... 8
9. BLOCK DIAGRAM......................................................................................................................9
10. FUNCTIONAL DESCRIPTION ................................................................................................. 10
10.1 SPI OPERATIONS ....................................................................................................... 10
10.1.1 SPI Modes....................................................................................................................10
10.1.2 Dual Output SPI............................................................................................................10
10.1.3 Hold Function ...............................................................................................................10
10.2 WRITE PROTECTION.................................................................................................. 11
10.2.1 Write Protect Features..................................................................................................11
11. CONTROL AND STATUS REGISTERS................................................................................... 12
11.1 STATUS REGISTER....................................................................................................12
11.1.1 BUSY............................................................................................................................12
11.1.2 Write Enable Latch (WEL)............................................................................................12
11.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................12
11.1.4 Top/Bottom Block Protect (TB).....................................................................................12
11.1.5 Reserved Bits...............................................................................................................12
11.1.6 Status Register Protect (SRP)......................................................................................13
11.1.7 Status Register Memory Protection..............................................................................14
11.2 INSTRUCTIONS...........................................................................................................16
11.2.1 Manufacturer and Device Identification.........................................................................16
11.2.2 Instruction Set
11.2.3 Write Disable (04h).......................................................................................................18
(1)
...........................................................................................................17
- 2 -
W25X16, W25X32, W25X64
11.2.4 Write Enable (06h)........................................................................................................18
11.2.5 Read Status Register (05h)..........................................................................................19
11.2.6 Write Status Register (01h) ..........................................................................................20
11.2.7 Read Data (03h)...........................................................................................................21
11.2.8 Fast Read (0Bh)...........................................................................................................22
11.2.9 Fast Read Dual Output (3Bh).......................................................................................23
11.2.10 Page Program (02h)...................................................................................................24
11.2.11 Sector Erase (20h) .....................................................................................................25
11.2.12 Block Erase (D8h) ......................................................................................................26
11.2.13 Chip Erase (C7h)........................................................................................................27
11.2.14 Power-down (B9h)......................................................................................................28
11.2.15 Release Power-down / Device ID (ABh).....................................................................29
11.2.16 Read Manufacturer / Device ID (90h).........................................................................31
11.2.17 JEDEC ID (9Fh)..........................................................................................................32
12. ELECTRICAL CHARACTERISTICS (PRELIMINARY)
12.1 Absolute Maximum Ratings
(1)
.................................................................................... 33
12.2 Operating Ranges......................................................................................................... 33
12.3 Endurance and Data Retention....................................................................................34
12.4 Power-up Timing and Write Inhibit Threshold.............................................................. 34
12.5 DC Electrical Characteristics........................................................................................ 35
12.6 AC Measurement Conditions........................................................................................ 36
12.7 AC Electrical Characteristics ........................................................................................ 37
12.8 AC Electrical Characteristics (cont’d)...........................................................................38
12.9 Serial Output Timing..................................................................................................... 39
12.10 Input Timing................................................................................................................. 39
12.11 Hold Timing ................................................................................................................. 39
13. PACKAGE SPECIFICATION.................................................................................................... 40
13.1 8-Pin SOIC 208-mil (Package Code SS)......................................................................40
13.2 8-Pin PDIP 300-mil (Package Code DA)...................................................................... 41
13.3 8-contact 6x5 WSON.................................................................................................... 42
13.4 8-contact 6x5 WSON Cont’d. ....................................................................................... 43
13.5 16-Pin SOIC 300-mil (Winbond Package Code SF)..................................................... 44
14. ORDERING INFORMATION
(1)
................................................................................................. 45
(4)
....................................................... 33
15. REVISION HISTORY................................................................................................................46
Publication Release Date: June 28, 2006
- 3 - Preliminary - Revision B
W25X16, W25X32, W25X64
1. GENERAL DESCRIPTION
The W25X16 (16M-bit), W25X32 (32M-bit), and W25X64 (64M-bit) Serial Flash memories provide a
storage solution for systems with limited space, pins and power. The 25X series offers flexibility and
performance well beyond ordinary Serial Flash devices. They are ideal for code download applications
as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply
with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in
space-saving packages.
The W25X16/32/64 array is organized into 8,192/16,384/32,768 programmable pages of 256-bytes
each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can
be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase).
The W25X16/32/64 has 512/1024/2048 erasable sectors and 32/64/128 erasable blocks respectively.
The small 4KB sectors allow for greater flexibility in applications that require data and parameter
storage. (See figure 2.)
The W25X16/32/64 supports the standard Serial Peripheral Interface (SPI), and a high performance
dual output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI
clock frequencies of up to 75MHz are supported allowing equivalent clock rates of 150MHz when
using the Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and
16-bit Parallel Flash memories.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control
features, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification.
2. FEATURES
• Family of Serial Flash Memories
– W25X16: 16M-bit / 2M -byte (2,097,152)
– W25X32: 32M-bit / 4M-byte (4,194,304)
– W25X64: 64M-bit / 8M-byte (8,388,608)
– 256-bytes per programmable page
– Uniform 4K-byte Sectors / 64K-byte Blocks
• SPI with Single or Dual Outputs
– Clock, Chip Select, Data I/O, Data Out
– Optional Hold function for SPI flexibility
• Data Transfer up to 150M-bits / second
– Clock operation to 75MHz
– Fast Read Dual Output instruction
– Auto-increment Read capability
• Flexible Architecture with 4KB sectors
– Sector Erase (4K-bytes)
– Block Erase (64K-byte)
– Page program up to 256 bytes <2ms
– Up to 100,000 erase/write cycles
– 20-year retention
• Low Power Consumption, Wide
Temperature Range
– Single 2.7 to 3.6V supply
– 5mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
• Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
• Space Efficient Packaging
– 8-pin SOIC 208-mil (W25X16)
– 8-pin PDIP 300-mil (W25X16)
– 8-pin WSON 6x5-mm (W25X16)
– 16-pin SOIC 300-mil (W25X16, W25X32 &
W25X64)
- 4 -
3. PIN CONFIGURATION SOIC 208-MIL
Figure 1a。W25X16 Pin Assignments, 8-pin SOIC (Package Code SS)
4. PIN CONFIGURATION WSON 6X5-MM
W25X16, W25X32, W25X64
Figure 1b。W25X16 Pin Assignments, 8-pin WSON (Package Code ZP)
Publication Release Date: June 28, 2006
- 5 - Preliminary - Revision B
W25X16, W25X32, W25X64
5. PIN CONFIGURATION PDIP 300-MIL
Figure 1c。W25X16 Pin Assignments, 8-pin PDIP (Package Code DA)
6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL, AND WSON 6X5-MM
PAD NO. PAD NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO O Data Output
3 /WP I Write Protect Input
4 GND Ground
5 DIO I/O Data Input / Output
6 CLK I Serial Clock Input
7 /HOLD I Hold Input
8 VCC Power Supply
- 6 -
7. PIN CONFIGURATION SOIC 300-MIL
W25X16, W25X32, W25X64
Figure 1d. W25X16, W25X32 and W25X64 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
8. PIN DESCRIPTION SOIC 300-MIL
PAD NO. PAD NAME I/O FUNCTION
1 /HOLD I Hold Input
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO O Data Output
9 /WP I Write Protect Input
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DIO I Data Input / Output
16 CLK I Serial Clock Input
Publication Release Date: June 28, 2006
- 7 - Preliminary - Revision B
W25X16, W25X32, W25X64
8.1 Package Types
At the time this datasheet was published not all package types had been finalized. Contact Winbond
to confirm availability of these packages before designing to this specification. W25X16 is offered in
an 8-pin plastic 208-mil width SOIC (package code SS), 6x5-mm WSON (package code ZP) and 300mil DIP (package code DA) as shown in figure 1a, 1b, and 1c, respectively. The W25X16, W25X32
and W25X64 are offered in an 16-pin plastic 300-mil width SOIC (package code SF) as shown in
figure 1d. Package diagrams and dimensions are illustrated at the end of this datasheet.
8.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle
is in progress. When /CS is brought low the device will be selected, power consumption will increase
to active levels and instructions can be written to and data read from the device. After power-up, /CS
must transition from high to low before a new instruction will be accepted. The /CS input must track
the VCC supply level at power-up (see “Write Protection” and figure 20). If needed a pull-up resister
on /CS can be used to accomplish this.
8.3 Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
8.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
8.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought
low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will
be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD
function can be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
8.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI "Operations")
8.7 Serial Data Input / Output (DIO)
The SPI Serial Data Input/Output (DIO) pin provides a means for instructions, addresses and data to
be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock
(CLK) input pin. The DIO pin is also used as an output when the Fast Read Dual Output instruction is
executed.
- 8 -
9. BLOCK DIAGRAM
W25X16, W25X32, W25X64
Figure 2. W25X16, W25X32 and W25X64 Block Diagram
Publication Release Date: June 28, 2006
- 9 - Preliminary - Revision B
W25X16, W25X32, W25X64
10. FUNCTIONAL DESCRIPTION
10.1 SPI OPERATIONS
10.1.1 SPI Modes
The W25X16/32/64 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI bus
operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK
signal is normally high. In either case data input on the DIO pin is sampled on the rising edge of the
CLK. Data on the DO and DIO pins are clocked out on the falling edge of CLK.
10.1.2 Dual Output SPI
The W25X16/32/64 supports Dual output operation when using the "Fast Read with Dual Output" (3B
hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice the
rate possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash
to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for
execution. The Dual output feature simply allows the SPI input pin to also serve as an output during
this instruction. All other operations use the standard SPI interface with single output signal.
10.1.3 Hold Function
The /HOLD signal allows the W25X16/32/64 operation to be paused while it is actively selected (when
/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are
shared with other devices. For example, consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will
activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition
will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not
already low the /HOLD condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept
active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the
device.
- 10 -
W25X16, W25X32, W25X64
10.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern the
W25X16/32/64 provides several means to protect data from inadvertent writes.
10.2.1 Write Protect Features
• Device resets when VCC is below threshold.
• Time delay write disable after Power-up.
• Write enable/disable instructions.
• Automatic write disable after program and erase.
• Software write protection using Status Register.
• Hardware write protection using Status Register and /WP pin.
• Write Protection using Power-down instruction.
Upon power-up or at power-down the W25X16/32/64 will maintain a reset condition while VCC is
below the threshold value of V
reset, all operations are disabled and no instructions are recognized. During power-up and after the
VCC voltage exceeds V
delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase
and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC
supply level at power-up until the VCC-min level and t
resister on /CS can be used to accomplish this.
WI, all program and erase related instructions are further disabled for a time
WI, (See Power-up Timing and Voltage Levels and Figure 20). While
VSL time delay is reached. If needed a pull-up
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After
completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status
Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction
with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under
hardware control. See Status Register for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
Publication Release Date: June 28, 2006
- 11 - Preliminary - Revision B
W25X16, W25X32, W25X64
11. CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the devices write protection features. See Figure 3.
11.1 STATUS REGISTER
11.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During
this time the device will ignore further instructions except for the Read Status Register instruction (see
t
W, tPP, tSE, TBE, and tCE in AC Characteristics). When the program, erase or write status register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
11.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing
a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A
write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
11.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction (see t
array can be protected from Program and Erase instructions (see Status Register Memory Protection
table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The
Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write
Protect (/WP) pin is low.
W in AC characteristics). All, none or a portion of the memory
11.1.4 Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The TB bit is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write
Status Register Instruction provided that the Write Enable instruction has been issued. The TB bit can
not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is
low.
11.1.5 Reserved Bits
Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit
location. It is recommended to mask out the reserved bit when testing the Status Register. Doing this
will ensure compatibility with future devices.
- 12 -
W25X16, W25X32, W25X64
11.1.6 Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be
used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP
bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP
pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the
/WP pin is high the Write Status Register instruction is allowed.
Figure 3. Status Register Bit Locations
Publication Release Date: June 28, 2006
- 13 - Preliminary - Revision B
W25X16, W25X32, W25X64
11.1.7 Status Register Memory Protection
STATUS REGISTER
TB BP2 BP1 BP0 BLOCK(S) ADDRESSES
x 0 0 0 NONE NONE NONE NONE
0 0 0 1 126 and 127 7E0000h - 7FFFFFh 1M -bit Upper 1/64
0 0 1 0 124 and 127 3C0000h - 7FFFFFh 2M-bit Upper 1/32
0 0 1 1 120 thru 127 780000h - 7FFFFFh 4M-bit Upper 1/16
0 1 0 0 112 thru 127 700000h - 7FFFFFh 8M-bit Upper 1/8
0 1 0 1 96 thru 127 600000h - 7FFFFFh 16M-bit Upper 1/4
0 1 1 0 64 thru 127 500000h - 7FFFFFh 32M-bit Upper 1/2
1 0 0 1 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/64
1 0 1 0 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/32
1 0 1 1 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/16
1 1 0 0 0 thru 15 000000h – 0FFFFFh 8M-bit Lower 1/8
1 1 0 1 0 thru 31 000000h – 1FFFFFh 16M-bit Lower 1/4
1 1 1 0 0 thru 63 000000h – 3FFFFFh 16M-bit Lower 1/4
x 1 1 1 0 thru 127 000000h - 7FFFFFh 64M-bit ALL
STATUS REGISTER
TB BP2 BP1 BP0 BLOCK(S) ADDRESSES
x 0 0 0 NONE NONE NONE NONE
0 0 0 1 63 3F0000h - 3FFFFFh 512K-bit Upper 1/64
0 0 1 0 62 and 63 3E0000h - 3FFFFFh 1M-bit Upper 1/32
0 0 1 1 60 thru 63 3C0000h - 3FFFFFh 2M-bit Upper 1/16
0 1 0 0 56 thru 63 380000h - 3FFFFFh 4M-bit Upper 1/8
0 1 0 1 48 thru 63 300000h - 3FFFFFh 8M-bit Upper 1/4
0 1 1 0 32 thru 63 200000h - 3FFFFFh 16M-bit Upper 1/2
1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/64
1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/32
1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/16
1 1 0 0 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/8
1 1 0 1 0 thru 15 000000h – 0FFFFFh 8M-bit Lower 1/4
1 1 1 0 0 thru 31 000000h – 1FFFFFh 16M-bit Lower 1/2
x 1 1 1 0 thru 63 000000h - 3FFFFFh 32M-bit ALL
(1)
W25X64 (64M-BIT) MEMORY PROTECTION
DENSITY
(KB)
(1)
W25X32 (32M-BIT) MEMORY PROTECTION
DENSITY
(KB)
PORTION
PORTION
- 14 -
W25X16, W25X32, W25X64
STATUS REGISTER
TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY (KB) PORTION
x 0 0 0 NONE NONE NONE NONE
0 0 0 1 31 1F0000h - 1FFFFFh 512K-bit Upper 1/32
0 0 1 0 30 and 31 1E0000h - 1FFFFFh 1M-bit Upper 1/16
0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 2M-bit Upper 1/8
0 1 0 0 24 thru 31 180000h - 1FFFFFh 4M-bit Upper 1/4
0 1 0 1 16 thru 31 100000h - 1FFFFFh 8M-bit Upper 1/2
1 0 0 1 0 000000h - 00FFFFh 512K-bit Lower 1/32
1 0 1 0 0 and 1 000000h - 01FFFFh 1M-bit Lower 1/16
1 0 1 1 0 thru 3 000000h - 03FFFFh 2M-bit Lower 1/8
1 1 0 0 0 thru 7 000000h - 07FFFFh 4M-bit Lower 1/4
1 1 0 1 0 thru 15 000000h - 0FFFFFh 8M-bit Lower 1/2
x 1 1 x 0 thru 31 000000h - 1FFFFFh 16M-bit ALL
Note:
1. x = don’t care
(1)
W25X16 (16M-BIT) MEMORY PROTECTION
Publication Release Date: June 28, 2006
- 15 - Preliminary - Revision B
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