Rainbow Electronics T5761 User Manual

Features

•Frequency Receiving Range of

f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz

•30 dB Image Rejection

•Receiving Bandwidth BIF = 600 kHz for Low Cost 90-ppm Crystals

•Fully Integrated LC-VCO and PLL Loop Filter

•Very High Sensitivity with Power Matched LNA

•High System IIP3 (-16 dBm), System 1-dB Compression Point (-25 dBm)

•High Large-signal Capability at GSM Band

(Blocking -30 dBm at +20 MHz, IIP3 = -12 dBm at +20 MHz)

•5 V to 20 V Automotive Compatible Data Interface

•Data Clock Available for Manchesterand Bi-phase-coded Signals

•Programmable Digital Noise Suppression

•Low Power Consumption Due to Configurable Polling

•Temperature Range -40°C to +105°C

•ESD Protection 2 kV HBM, All Pins

•Communication to Microcontroller Possible Via a Single Bi-directional Data Line

•Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements

Description

The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF transmitter T5750. Its main applications are in the areas of telemetering, security technology and keylessentry systems. It can be used in the frequency receiving range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz for ASK or FSK data transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz applications.

Figure 1. System Block Diagram
UHF ASK/FSK			UHF ASK/FSK
Remote control transmitter			Remote control receiver
T5750		T5760/
		T5761	Demod.	Control	1...5	µC
XTO	PLL
	Antenna	Antenna	IF Amp
	VCO		PLL	XTO
	Power	LNA	VCO
	amp.

UHF ASK/FSK

Receiver

T5760/T5761

Preliminary

Rev. 4561B–RKE–10/02

1

Figure 2. Block Diagram

	FSK/ASK-	Dem_out	Data -
CDEM	demodulator		interface	DATA
	and data filter

	Rssi	Limiter out
SENS		RSSI IF						POLLING/_ON
		Amp.	Sensitivity-
						Polling circuit
				reduction
AVCC						and		DATA_CLK
						control logic
AGND	4. Order
DGND	f0 = 950 kHz/
		1 MHz				FE	CLK
DVCC								IC_ACTIVE
		LPF
	fg = 2.2 MHz					Standby logic
		IF
		Amp.				Loop-
						filter
	Poly-LPF
	fg = 7 MHz				LC-VCO		XTO	XTAL
LNAREF		f				f
LNA_IN	LNA
			:2			:256
LNAGND

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T5760/T5761

Pin Configuration

Figure 3. Pinning SO20

SENS	1			20	DATA
IC_ACTIVE	2			19	POLLING/_ON
CDEM	3			18	DGND
AVCC	4			17	DATA_CLK
TEST 1	5			16	TEST 4
			T5760/
AGND	6		T5761	15	DVCC
n.c.	7			14	XTAL
LNAREF	8			13	n.c.
LNA_IN	9			12	TEST 3
LNAGND	10			11	TEST 2

Pin Description

Pin	Symbol	Function
1	SENS	Sensitivity-control resistor
2	IC_ACTIVE	IC condition indicator: Low = sleep mode, High = active mode
3	CDEM	Lower cut-off frequency data filter
4	AVCC	Analog power supply
5	TEST 1	Test pin, during operation at GND
6	AGND	Analog ground
7	n.c.	Not connected, connect to GND
8	LNAREF	High-frequency reference node LNA and mixer
9	LNA_IN	RF input
10	LNAGND	DC ground LNA and mixer
11	TEST 2	Do not connect during operating
12	TEST 3	Test pin, during operation at GND
13	n.c.	Not connected, connect to GND
14	XTAL	Crystal oscillator XTAL connection
15	DVCC	Digital power supply
16	TEST 4	Test pin, during operation at DVCC
17	DATA_CLK	Bit clock of data stream
18	DGND	Digital ground
19	POLLING/_ON	Selects polling or receiving mode; Low: receiving mode, High: polling mode
20	DATA	Data output/configuration input

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RF Front End

The RF front end of the receiver is a low-IF heterodyne configuration that converts the input signal into a 950 kHz/1 MHz IF signal with an image rejection of typical 30 dB. According to Figure 3 the front end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier.

The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency fXTO. The integrated LCVCO generates two times the mixer drive frequency fVCO. The I/Q signals for the mixer

are generated with a divide by two circuit (fLO = fVCO/2). fVCO is divided by a factor of 256 and feeds into a phase frequency detector and compared with fXTO. The output of the

phase frequency detector is fed into an integrated loop filter and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using the following formula:

fXTO = fLO/128

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at Pin XTAL. According to Figure 4, the crystal should be connected to GND with a series capacitor CL. The value of that capacitor is recommended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of CL is normally necessary.

The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO (the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor) and hereby of fLO. When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.

If a crystal with ±30 ppm adjustment tolerance at 25 C, ±50 ppm over temperature -40 C to +105 C, ±10 ppm of total aging and a CM (motional capacitance) of 7 fF is used, an additional XTO pulling of ±30 ppm has to be added.

The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of ±120 ppm.

Figure 4. XTO Peripherals

VS

DVCC

CL

XTAL

n.c.

TEST 3

TEST 2

The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula (low side injection):

fLO = fRF - fIF

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T5760/T5761

To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO.

fIF = fLO/915

The relation is designed to achieve the nominal IF frequency of fIF = 950 kHz for the 868.3 MHz version. For the 915 MHz version an IF frequency of fIF = 1.0 MHz results.

The RF input either from an antenna or from an RF generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well as to 50 or an antenna easier.

Figure 33 shows a typical input matching network for fRF = 868.3 MHz to 50 . Figure 34 illustrates an according input matching for 868.3 MHz to an SAW. The input matching network shown in Figure 33 is the reference network for the parameters given in the electrical characteristics.

Analog Signal Processing

IF Filter

Limiting RSSI Amplifier

The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 950 kHz for applications where fRF = 868.3 MHz and fIF =1.0 MHz for fRF = 915 MHz. The nominal bandwidth is 600 kHz.

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK

mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage

VTh_red. VTh_red is determined by the value of the external resistor RSens. RSens is connected between Pin SENS and GND or VS. The output of the comparator is fed into the

digital control logic. By this means it is possible to operate the receiver at a lower sensitivity.

If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the Pin SENS directly to GND to get the maximum sensitivity.

If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSens, the maximum sensitivity by the signal-to- noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier.

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FSK/ASK Demodulator

and Data Filter

Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 33 and exhibits the best possible sensitivity and at the same time power matching at RF_IN.

RSens can be connected to VS or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling

mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 5 is issued at Pin DATA to indicate that the receiver is still active (see Figure 32).

Figure 5. Steady L State Limited DATA Output Pattern

DATA	t DATA_min	t DATA_L_max

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter.

The FSK demodulator is intended to be used for an FSK deviation of 10 kHz f 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal.

The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1st- order high pass and a 2nd-order lowpass filter.

The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula:

	1
fcu_DF =	2--------------------30--------k--------------CDEM----------------

In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics.

The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to chapter ‘Configuration of the Receiver’). The BR_Range must be set in accordance to the used baud-rate.

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T5760/T5761

Receiving

Characteristics

The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.

The RF receiver T5760/T5761 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in Figure 6 and Figure 7. This example relates to ASK mode. FSK mode exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be considered, but the overall selectivity is much better.

When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation of the T5760/T5761. Low-cost crystals are specified to be within ±90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm worst case for a crystal with CM = 7 fF. If a crystal of ±90 ppm is used, the total deviation is ±120 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.

Figure 6. Narrow Band Receiving Frequency Response

	0.0
	-10.0
	-20.0
dP (dB)	-30.0
	-40.0
	-50.0
	-60.0
	-4.0	-3.0	-2.0	-1.0	0.0	1.0	2.0	3.0	4.0

df (MHz)

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Figure 7. Wide Band Receiving Frequency Response

	0.0
	-10.0
	-20.0
	-30.0
	-40.0
(dB)	-50.0
dP	-60.0
	-70.0
	-80.0
	-90.0
	-100.0
	-12.0	-9.0	-6.0	-3.0	0.0	3.0	6.0	9.0	12.0

df (MHz)

Polling Circuit and

Control Logic

Basic Clock Cycle of

the Digital Circuitry

The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports.

The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divide by 14 circuit. According to chapter ‘RF Front End’, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). The basic clock cycle is TClk = 14/fXTO giving TClk = 2.066 µs for fRF = 868.3 MHz and TClk = 1.961 µs for fRF = 915 MHz.

TClk controls the following application-relevant parameters:

•Timing of the polling circuit including bit check

•Timing of the analog and digital signal processing

•Timing of the register programming

•Frequency of the reset marker

•IF filter center frequency (fIF0)

Most applications are dominated by two transmission frequencies: fTransmit = 915 MHz is mainly used in USA, fTransmit = 868.3 MHz in Europe. In order to ease the usage of all TClk-dependent parameters on this electrical characteristics display three conditions for

each parameter.

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T5760/T5761

Polling Mode

Sleep Mode

•Application USA (fXTO = 7.14063 MHz, TClk = 1.961 µs)

•Application Europe (fXTO = 6.77617 MHz, TClk = 2.066 µs)

•Other applications The electrical characteristic is given as a function of TClk.

The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference:

BR_Range = BR_Range0:	TXClk = 8 TClk
BR_Range1:	TXClk = 4 TClk
BR_Range2:	TXClk = 2 TClk
BR_Range3:	TXClk = 1 TClk

According to Figure 11, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time

period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode,

the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no

valid signal is present, the receiver is set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for

TBit-check is given in the electrical characteristics. During TStartup and TBit-check the current consumption is IS = ISon. The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the

active mode and can be calculated as:

	ISpoll	=	ISoff TSleep + ISon TStartup + TBit-check
			--------------------T----Sleep-------------+-----T----Startup-----------------+-----T----Bit--------check------------------------------

During TSleep and TStartup the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the telegram with

an adequate preburst. The required length of the preburst depends on the polling

parameters TSleep, TStartup, TBit-check and the start-up time of a connected microcontroller (TStart_microcontroller). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested.

The following formula indicates how to calculate the preburst length.

TPreburst TSleep + TStartup + TBit-check + TStart_microcontroller

The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to Table 8), and the basic clock cycle TClk. It is

calculated to be:

TSleep = Sleep XSleep 1024 TClk

In USand European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be

extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to’1’.

According to Table 7, the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling – via Pin POLLING/_ON, the receiver can be switched on and off.

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Figure 8. Polling Mode Flow Chart

Sleep mode:

All circuits for signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on Pin IC_ACTIVE => low

IS = ISoff

TSleep = Sleep x XSleep x 1024 x TClk

Start-up mode:

The signal processing circuits are

enabled. After the start-up time (TStartup) all circuits are in stable

condition and ready to receive.

Output level on Pin IC_ACTIVE => high

IS = ISon

TStartup

Bit-check mode:

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode.

Output level on Pin IC_ACTIVE => high

IS = ISon

TBit-check

	Bit check
NO	OK ?

YES

Receiving mode:

The receiver is turned on permanently and passes the data stream to the connected microcontroller.

It can be set to Sleep mode through an

OFF command via Pin DATA or

POLLING/_ON.

Output level on Pin IC_ACTIVE => high

IS = ISon

OFF command

Sleep:	5-bit word defined by Sleep0 to
	Sleep4 in OPMODE register
XSleep:	Extension factor defined by
	XSleepStd
	according to Table 9
TClk:	Basic clock cycle defined by fXTO
	and Pin MODE
TStartup:	Is defined by the selected baud rate
	range and TClk. The baud-rate range
	is defined by Baud0 and Baud1 in
	the OPMODE register.

TBit-check : Depends on the result of the bit check

If the bit check is ok, TBit-check depends on the number of bits to be

checked (NBit-check) and on the utilized data rate.

If the bit check fails, the average time period for that check depends on the selected baud-rate range and

on TClk. The baud-rate range is defined by Baud0 and Baud1 in the

OPMODE register.

Figure 9. Timing Diagram for Complete Successful Bit Check

( Number of checked Bits: 3 )		Bit check ok
IC_ACTIVE
Bit check	1/2 Bit	1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit	1/2 Bit
Dem_out
Data_out (DATA)	TStart-up	TBit-check
	Start-up mode	Bit-check mode	Receiving mode

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T5760/T5761

Bit-check Mode

Configuring the Bit

Check

In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable.

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the

variable NBit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBit-check is set to a higher value, the receiver is less likely to

switch to receiving mode due to noise. In the presence of a valid transmitter signal, the

bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 9 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA.

According to Figure 10, the time window for the bit check is defined by two separate

time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check will be continued. If tee is smaller than

TLim_min or tee exceeds TLim_max, the bit check will be terminated and the receiver switches to sleep mode.

Figure 10. Valid Time Window for Bit Check

		1/fSig
	Dem_out	tee
		TLim_min
		TLim_max

For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ± 30% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the bitcheck limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below.

TLim_min = Lim_min TXClk

TLim_max = (Lim_max -1) TXClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.

Using above formulas, Lim_min and Lim_max can be determined according to the

required TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the chapter ‘Receiving Mode’. The lower limit should be set to Lim_min 10. The max-

imum value of the upper limit is Lim_max = 63.

If the calculated value for Lim_min is <19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving mode due to noise.

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