Rainbow Electronics T89C51CC02 User Manual

838.72 Kb
Loading...

T89C51CC02

8-bit MCU with CAN controller and Flash

1. Description

Part of the CANaryTM family of microcontrollers dedicated to CAN network applications, the T89C51CC02 is a low pin count 8-bit Flash microcontroller.

While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

2. Features

80C51 core architecture:

256 bytes of on-chip RAM

256 bytes of on-chip ERAM

16 Kbytes of on-chip Flash memory

Read/Write cycle : 10k

Data Retention 10 years at 85°C

2 Kbytes of on-chip Flash for Bootloader

2 Kbytes of on-chip EEPROM Read/Write cycle : 100k

14-source 4-level interrupt

Three 16-bit timer/counter

Full duplex UART compatible 80C51

maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)

three or four ports: 16 or 20 digital I/O lines

two-channel 16-bit PCA with:

-PWM (8-bit)

-High-speed output

-Timer and edge capture

Double Data Pointer

21-bit watchdog timer (including 7 programmable bits)

A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs

Separate power supply for analog

Full CAN controller:

Fully compliant with CAN standard rev 2.0 A and 2.0 B

Optimized structure for communication management (via SFR)

4 independent message objects:

-Each message object programmable on transmission or reception

Besides the full CAN controller T89C51CC02 provides 16 Kbytes of Flash memory including In-system Programming (ISP), 2-Kbyte Boot Flash Memory, 2- Kbyte EEPROM and 512 bytes RAM.

Special attention is payed to the reduction of the electromagnetic emission of T89C51CC02.

-individual tag and mask filters up to 29-bit identifier/message object

-8-byte cyclic data register (FIFO)/message object

-16-bit status & control register/message object

-16-bit Time-Stamping register/message object

-CAN specification 2.0 part A or 2.0 part B programmable message objects

-Access to message object control and data register via SFR

-Programmable reception buffer lenght up to 4 message objects

-Priority management of reception of hits on several message objects at the same time (Basic CAN Feature)

-Priority management for transmission

-message object overrun interrupt

Supports

-Time Triggered Communication.

-Autobaud and Listening mode

-Automatic reply mode programmable

1 Mbit/s maximum transfer rate at 8MHz* Crystal frequency in X2 mode.

Readable error counters

Programmable link to on-chip Timer for Time Stamping and Network synchronization

Independent baud rate prescaler

Data, Remote, Error and overload frame handling

Power saving modes:

Idle mode

Power down mode

Power supply: 5V +/- 10% ,3V +/- 10%

Temperature range: Industrial (-40° to +85°C)

Packages: PLCC28, SOIC28, (TSSOP28, SOIC24)**

Rev.A- May 17, 2001

1

Preliminary

T89C51CC02

*At BRP = 1 sampling point will be fixed.

**Ask for availability

3. Block Diagram

 

 

RxD

TxD

 

Vcc

Vss

ECI

PCA

T2EX

T2

RxDC

TxDC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UART

RAM

Flash

Boot

EE

ERAM

PCA

Timer2

CAN

256x8

16kx

loader

PROM

256x8

 

 

 

 

 

 

8

2kx8

2kx8

 

 

 

CONTROLLER

XTAL1

C51

 

XTAL2

CORE

IB-bus

CPU

 

 

 

 

 

 

 

 

Timer 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT

 

 

 

Parallel I/O Ports & Ext. Bus

 

 

Watch

 

10 bit

 

 

 

 

 

 

Timer 1

 

 

Ctrl

 

 

 

 

 

 

 

 

 

 

 

 

 

Dog

 

ADC

 

 

 

 

 

 

 

 

 

Port 1

Port 2

Port 3

Port 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1(1)

P2(2)

P3

P4(2)

 

 

 

 

 

 

 

RESET

 

T0

T1

 

INT0

 

INT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1): 8 analog Inputs / 8 Digital I/O (2): 2-Bit I/O Port

2

Rev.A - May 17, 2001

Preliminary

T89C51CC02

4. Pin Configuration

VAREF

1

 

28

P1.0/AN0/T2

VAGND

2

 

27

P1.1/AN1/T2EX

VAVCC

3

 

26

P1.2/AN2/ECI

P4.1/RxDC

4

 

25

P1.3/AN3/CEX0

P4.0/TxDC

5

 

24

P1.4/AN4/CEX1

P2.1

6

 

23

P1.5/AN5

 

P1.6/AN6

P3.7

7

SO28

22

P1.7/AN7

P3.6

8

 

21

P3.5/T1

9

 

20

P2.0

P3.4/T0

10

 

19

RESET

P3.3/INT1

11

 

18

VSS

P3.2/INT0

12

 

17

VCC

P3.1/TxD

13

 

16

XTAL1

P3.0/RxD

14

 

15

XTAL2

 

 

 

 

 

 

 

 

 

P4.1 / TxDC

 

 

VAVCC

 

VAGND

 

 

VAREF

 

P1.0 / AN 0 / T2

 

P1.1 / AN1 / T2EX

 

 

P1.2 / AN2 / ECI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

3

2

1

28

27

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.3 / AN3 / CEX0

P4.0/ TxDC

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P2.1

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

24

 

 

 

P1.4 / AN4 / CEX1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.7

7

 

 

 

 

 

 

PLCC-28

23

 

 

 

P1.5 / AN5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.6

8

 

 

 

 

 

 

22

 

 

 

P1.6 / AN6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.5 / T1

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

 

P1.7 / AN7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.4 / T0

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

 

 

 

P2.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.3 /

INT1

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

19

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

13

 

14

 

15

 

16

 

17

 

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.2 / INT0

 

P3.1 / TxD

 

P3.0 / RxD

XTAL2

 

XTAL1

 

VCC

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev.A - May 17, 2001

3

Preliminary

T89C51CC02

 

 

 

 

Table 1. Pin Description

 

 

 

 

 

Pin Name

Type

 

 

Description

 

 

 

 

 

VSS

GND

Circuit ground potential.

 

 

 

VCC

 

Supply voltage during normal, idle, and power-down operation.

 

 

 

VAREF

 

Reference Voltage for ADC

 

 

 

VAVCC

 

Supply Voltage for ADC

 

 

 

VAGND

 

Reference Ground for ADC / Analog Ground

 

 

 

 

 

Port 1:

 

 

is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output

 

 

or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them

 

 

are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port

 

 

1 pins that are being pulled low externally will be the source of current (IIL, on the datasheet) because

 

 

of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCF register.

 

 

As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA

 

 

external clock input and the PCA module I/O.

P1.0:7

I/O

P1.0 / AN0 / T2

Analog input channel 0,

 

 

 

 

External clock input for Timer/counter2.

 

 

P1.1 / AN1 / T2EX

 

 

Analog input channel 1,

 

 

Trigger input for Timer/counter2.

 

 

P1.2 / AN2 / ECI

 

 

Analog input channel 2,

 

 

PCA external clock input.

 

 

PIn the T89C51CC02 Port 1 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

 

 

 

 

 

Port 2:

 

 

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are

P2.0:1

I/O

pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that

are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal

 

 

 

 

pull-ups.

 

 

In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

 

 

 

 

 

Port 3:

 

 

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are

 

 

pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3

 

 

pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the

 

 

internal pull-ups.

 

 

The output latch corresponding to a secondary function must be programmed to one for that function to

 

 

operate. The secondary functions are assigned to the pins of port 3 as follows:

 

 

P3.0 / RxD:

 

 

Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

 

 

P3.1 / TxD:

 

 

Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.0:7

I/O

P3.2 /

 

 

INT0:

 

 

External interrupt 0 input / timer 0 gate control input

 

 

P3.3 /

 

 

 

 

INT1:

 

 

External interrupt 1 input / timer 1 gate control input

 

 

P3.4 / T0:

 

 

Timer 0 counter input

 

 

P3.5 / T1:

 

 

Timer 1 counter input

 

 

P3.6

 

 

P3.7

 

 

In the T89C51CC02 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

 

 

 

 

 

4

Rev.A - May 17, 2001

Preliminary

T89C51CC02

Pin Name

Type

Description

 

 

 

 

 

Port 4:

 

 

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are

 

 

pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are

 

 

being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-

 

 

up transistor.

 

 

The output latch corresponding to a secondary function RxDC must be programmed to one for that function

P4.0:1

I/O

to operate. The secondary functions are assigned to the two pins of port 4 as follows:

 

 

P4.0 / TxDC:

 

 

Transmitter output of CAN controller

 

 

P4.1 / RxDC:

 

 

Receiver input of CAN controller.

 

 

In the T89C51CC02 Port 4 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

 

 

 

 

 

Reset:

RESET

I/O

A high level on this pin during two machine cycles while the oscillator is running resets the device. An

 

 

internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.

 

 

 

 

 

XTAL1:

XTAL1

I

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.

To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left

 

 

 

 

unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

 

 

 

XTAL2

O

XTAL2:

Output from the inverting oscillator amplifier.

 

 

 

 

 

Rev.A - May 17, 2001

5

Preliminary

T89C51CC02

4.1. I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.

4.2. Port Structure

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either forgeneral-purpose I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=1,3 or 4). To use a pin for general purpose input, set the bit in the Px register. This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in "quasi-Bidirectional Port Operation" paragraph.

 

 

 

VCC

 

 

ALTERNATE

INTERNAL

 

 

OUTPUT

READ

 

FUNCTION

PULL-UP (1)

 

 

 

LATCH

 

 

Port.x

 

 

 

INTERNAL

D

Q

 

BUS

 

Port.X

 

 

 

 

 

WRITE

LATCH

 

 

TO

CL

 

 

LATCH

 

 

 

READ

 

 

 

PIN

 

ALTERNATE

 

 

 

INPUT

 

 

 

FUNCTION

 

NOTE:

1. The internal pull-up can be disabled on P1 when analog function is selected.

Figure 1. Port Structure

6

Rev.A - May 17, 2001

Preliminary

T89C51CC02

4.3. Read-Modify-Write Instructions

Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read-Modifiy-Write" instructions. Below is a complete list of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:

Table 2. Read-Modify-Write Instructions

Instruction

Description

Example

 

 

 

ANL

logical AND

ANL P1, A

 

 

 

ORL

logical OR

ORL P2, A

 

 

 

XRL

logical EX-OR

XRL P3, A

 

 

 

JBC

jump if bit = 1 and clear bit

JBC P1.1, LABEL

 

 

 

CPL

complement bit

CPL P3.0

 

 

 

INC

increment

INC P2

 

 

 

DEC

decrement

DEC P2

 

 

 

DJNZ

decrement and jump if not zero

DJNZ P3, LABEL

 

 

 

MOV Px.y, C

move carry bit to bit y of Port x

MOV P1.5, C

 

 

 

CLR Px.y

clear bit y of Port x

CLR P2.4

 

 

 

SET Px.y

set bit y of Port x

SET P3.3

 

 

 

It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read- Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic)levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attemps by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.

4.4. Quasi-Bidirectional Port Operation

Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input condions by a logical one written to the latch.

NOTE:

Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-Modify-Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition see Figure. This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3.

Rev.A - May 17, 2001

7

Preliminary

T89C51CC02

VCC

VCC

VCC

2 Osc. PERIODS

 

 

p1

p2

p3

P1.x

P2.x

P3.x

P4.x

OUTPUT DATA

n

INPUT DATA

READ PIN

Figure 2. Internal Pull-Up Configurations

8

Rev.A - May 17, 2001

Preliminary

T89C51CC02

5. SFR Mapping

The Special Function Registers (SFRs) of the T89C51CC02 fall into the following categories:

Table 3. C51 Core SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

ACC

E0h

Accumulator

 

 

 

 

 

 

 

 

B

F0h

B Register

 

 

 

 

 

 

 

 

PSW

D0h

Program Status Word

 

 

 

 

 

 

 

 

SP

81h

Stack Pointer

 

 

 

 

 

 

 

 

LSB of SPX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPL

82h

Data Pointer Low byte

 

 

 

 

 

 

 

 

LSB of DPTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DPH

83h

Data Pointer High byte

 

 

 

 

 

 

 

 

MSB of DPTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4. I/O Port SFRs

Mnemonic

Add

 

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

P1

90h

Port 1

 

 

 

 

 

 

 

 

 

P2

A0h

Port 2

(x2)

 

 

 

 

 

 

 

 

P3

B0h

Port 3

 

 

 

 

 

 

 

 

 

P4

C0h

Port 4

(x2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 5. Timers SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

TH0

8Ch

Timer/Counter 0 High byte

 

 

 

 

 

 

 

 

TL0

8Ah

Timer/Counter 0 Low byte

 

 

 

 

 

 

 

 

TH1

8Dh

Timer/Counter 1 High byte

 

 

 

 

 

 

 

 

TL1

8Bh

Timer/Counter 1 Low byte

 

 

 

 

 

 

 

 

TH2

CDh

Timer/Counter 2 High byte

 

 

 

 

 

 

 

 

TL2

CCh

Timer/Counter 2 Low byte

 

 

 

 

 

 

 

 

TCON

88h

Timer/Counter 0 and 1 control

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TMOD

89h

Timer/Counter 0 and 1 Modes

GATE1

C/T1#

M11

M01

GATE0

C/T0#

M10

M00

T2CON

C8h

Timer/Counter 2 control

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

T2MOD

C9h

Timer/Counter 2 Mode

-

-

-

-

-

-

T2OE

DCEN

RCAP2H

CBh

Timer/Counter

2

Reload/Capture

 

 

 

 

 

 

 

 

High byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RCAP2L

CAh

Timer/Counter

2

Reload/Capture

 

 

 

 

 

 

 

 

Low byte

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDTRST

A6h

WatchDog Timer Reset

 

 

 

 

 

 

 

 

WDTPRG

A7h

WatchDog Timer Program

-

-

-

-

-

S2

S1

S0

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 6. Serial I/O Port SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

SCON

98h

Serial Control

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SBUF

99h

Serial Data Buffer

 

 

 

 

 

 

 

 

SADEN

B9h

Slave Address Mask

 

 

 

 

 

 

 

 

SADDR

A9h

Slave Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev.A - May 17, 2001

9

Preliminary

T89C51CC02

Table 7. PCA SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

CCON

D8h

PCA Timer/Counter Control

CF

CR

-

CCF4

CCF3

CCF2

CCF1

CCF0

CMOD

D9h

PCA Timer/Counter Mode

CIDL

WDTE

-

-

-

CPS1

CPS0

ECF

CL

E9h

PCA Timer/Counter Low byte

 

 

 

 

 

 

 

 

CH

F9h

PCA Timer/Counter High byte

 

 

 

 

 

 

 

 

CCAPM0

DAh

PCA Timer/Counter Mode 0

-

ECOM0

CAPP0

CAP0

MAT0

TOG0

PWM0

ECCF0

CCAPM1

DBh

PCA Timer/Counter Mode 1

ECOM1

CAPP1

CAP1

MAT1

TOG1

PWM1

ECCF1

 

CCAP0H

FAh

PCA Compare Capture Module 0 H

CCAP0H7

CCAP0H6

CCAP0H5

CCAP0H4

CCAP0H3

CCAP0H2

CCAP0H1

CCAP0H0

CCAP1H

FBh

PCA Compare Capture Module 1 H

CCAP1H7

CCAP1H6

CCAP1H5

CCAP1H4

CCAP1H3

CCAP1H2

CCAP1H1

CCAP1H0

CCAP0L

EAh

PCA Compare Capture Module 0 L

CCAP0L7

CCAP0L6

CCAP0L5

CCAP0L4

CCAP0L3

CCAP0L2

CCAP0L1

CCAP0L0

CCAP1L

EBh

PCA Compare Capture Module 1 L

CCAP1L7

CCAP1L6

CCAP1L5

CCAP1L4

CCAP1L3

CCAP1L2

CCAP1L1

CCAP1L0

 

 

 

 

 

 

 

 

 

 

 

Table 8. Interrupt SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

IEN0

A8h

Interrupt Enable Control 0

EA

AC

ET2

ES

ET1

EX1

ET0

EX0

IEN1

E8h

Interrupt Enable Control 1

-

-

-

-

-

ETIM

EADC

ECAN

IPL0

B8h

Interrupt Priority Control Low 0

-

PPC

PT2

PS

PT1

PX1

PT0

PX0

IPH0

B7h

Interrupt Priority Control High 0

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

IPL1

F8h

Interrupt Priority Control Low 1

-

-

-

-

-

POVRL

PADCL

PCANL

IPH1

F7h

Interrupt Priority Control High1

-

-

-

-

-

POVRH

PADCH

PCANH

 

 

 

 

 

 

 

 

 

 

 

Table 9. ADC SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

ADCON

F3h

ADC Control

-

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

ADCF

F6h

ADC Configuration

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

ADCLK

F2h

ADC Clock

-

-

-

PRS4

PRS3

PRS2

PRS1

PRS0

ADDH

F5h

ADC Data High byte

ADAT9

ADAT8

ADAT7

ADAT6

ADAT5

ADAT4

ADAT3

ADAT2

ADDL

F4h

ADC Data Low byte

-

-

-

-

-

-

ADAT1

ADAT0

 

 

 

 

 

 

 

 

 

 

 

Table 10. CAN SFRs

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

CANGCON

ABh

CAN General Control

ABRQ

OVRQ

TTC

SYNCTTC

AUT-

TEST

ENA

GRES

BAUD

 

 

 

 

 

 

 

 

 

 

CANGSTA

AAh

CAN General Status

-

OVFG

-

TBSY

RBSY

ENFG

BOFF

ERRP

CANGIT

9Bh

CAN General Interrupt

CANIT

-

OVRTIM

OVRBUF

SERG

CERG

FERG

AERG

CANBT1

B4h

CAN Bit Timing 1

-

BRP5

BRP4

BRP3

BRP2

BRP1

BRP0

-

CANBT2

B5h

CAN Bit Timing 2

-

SJW1

SJW2

-

PRS2

PRS1

PRS0

-

CANBT3

B6h

CAN Bit Timing 3

-

PHS22

PHS21

PHS20

PHS12

PHS11

PHS10

SMP

CANEN

CFh

CAN Enable Channel byte

-

-

-

-

ENCH3

ENCH2

ENCH1

ENCH0

CANGIE

C1h

CAN General Interrupt Enable

-

-

ENRX

ENTX

ENER

ENBUF

-

-

CANIE

C3h

CAN Interrupt Enable Channel

-

-

-

-

IECH3

IECH2

IECH1

IECH0

byte

 

 

 

 

 

 

 

 

 

 

CANSIT

BBh

CAN Status Interrupt Channel byte

-

-

-

-

SIT3

SIT2

SIT1

SIT0

CANTCON

A1h

CAN Timer Control

TPRESC 7

TPRESC 6

TPRESC 5

TPRESC 4

TPRESC 3

TPRESC 2

TPRESC 1

TPRESC 0

CANTIMH

ADh

CAN Timer high

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

15

14

13

12

11

10

9

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 Rev.A - May 17, 2001

Preliminary

T89C51CC02

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

CANTIML

ACh

CAN Timer low

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

7

6

5

4

3

2

1

0

 

 

 

CANSTMH

AFh

CAN Timer Stamp high

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

15

14

13

12

11

10

9

8

 

 

 

CANSTML

AEh

CAN Timer Stamp low

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

7

6

5

4

3

2

1

0

 

 

 

CANTTCH

A5h

CAN Timer TTC high

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

15

14

13

12

11

10

9

8

 

 

 

CANTTCL

A4h

CAN Timer TTC low

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

7

6

5

4

3

2

1

0

 

 

 

CANTEC

9Ch

CAN Transmit Error Counter

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

CANREC

9Dh

CAN Receive Error Counter

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

CANPAGE

B1h

CAN Page

-

-

CHNB1

CHNB0

AINC

INDX2

INDX1

INDX0

CANSTCH

B2h

CAN Status Channel

DLCW

TXOK

RXOK

BERR

SERR

CERR

FERR

AERR

CANCONH

B3h

CAN Control Channel

CONCH1

CONCH0

RPLV

IDE

DLC3

DLC2

DLC1

DLC0

CANMSG

A3h

CAN Message Data

MSG7

MSG6

MSG5

MSG4

MSG3

MSG2

MSG1

MSG0

CANIDT1

BCh

CAN Identifier Tag byte 1(Part A)

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

IDT4

IDT3

CAN Identifier Tag byte 1(PartB)

IDT28

IDT27

IDT26

IDT25

IDT24

IDT23

IDT22

IDT21

 

 

CANIDT2

BDh

CAN Identifier Tag byte 2 (PartA)

IDT2

IDT1

IDT0

-

-

-

-

-

CAN Identifier Tag byte 2 (PartB)

IDT20

IDT19

IDT18

IDT17

IDT16

IDT15

IDT14

IDT13

 

 

CANIDT3

BEh

CAN Identifier Tag byte 3(PartA)

-

-

-

-

-

-

-

-

CAN Identifier Tag byte 3(PartB)

IDT12

IDT11

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

 

 

CANIDT4

BFh

CAN Identifier Tag byte 4(PartA)

-

-

-

-

-

RTRTAG

-

RB0TAF

CAN Identifier Tag byte 4(PartB)

IDT4

IDT3

IDT2

IDT1

IDT0

RB1TAG

 

 

 

 

CANIDM1

C4h

CAN Identifier Mask byte 1(PartA)

IDMSK10

IDMSK9

IDMSK8

IDMSK7

IDMSK6

IDMSK5

IDMSK4

IDMSK3

CAN Identifier Mask byte 1(PartB)

IDMSK28

IDMSK27

IDMSK26

IDMSK25

IDMSK24

IDMSK23

IDMSK22

IDMSK21

 

 

CANIDM2

C5h

CAN Identifier Mask byte 2(PartA)

IDMSK2

IDMSK1

IDMSK0

-

-

-

-

-

CAN Identifier Mask byte 2(PartB)

IDMSK20

IDMSK19

IDMSK18

IDMSK17

IDMSK16

IDMSK15

IDMSK14

IDMSK13

 

 

CANIDM3

C6h

CAN Identifier Mask byte 3(PartA)

-

-

-

-

-

-

-

-

CAN Identifier Mask byte 3(PartB)

IDMSK12

IDMSK11

IDMSK10

IDMSK9

IDMSK8

IDMSK7

IDMSK6

IDMSK5

 

 

CANIDM4

C7h

CAN Identifier Mask byte 4(PartA)

-

-

-

-

-

RTRMSK

-

IDEMSK

CAN Identifier Mask byte 4(PartB)

IDMSK4

IDMSK3

IDMSK2

IDMSK1

IDMSK0

 

 

 

 

 

 

 

 

Table 11. Other SFRs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

PCON

87hh

Power Control

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

AUXR1

A2h

Auxiliary Register 1

-

-

ENBOOT

-

GF3

-

-

DPS

CKCON

8Fh

Clock Control

CANX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

FCON

D1h

FLASH Control

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

EECON

D2h

EEPROM Contol

EEPL3

EEPL2

EEPL1

EEPL0

-

-

EEE

EEBUSY

 

 

 

 

 

 

 

 

 

 

 

Rev.A - May 17, 2001

11

Preliminary

T89C51CC02

Table 12. SFR’s mapping

0/8(1)

1/9

2/A

3/B

4/C

5/D

6/E

7/F

F8h

IPL1

CH

CCAP0H

CCAP1H

 

 

 

 

FFh

 

0000 0000

0000 0000

0000 0000

 

 

 

 

 

xxxx x000

 

 

 

 

 

F0h

B

 

ADCLK

ADCON

ADDL

ADDH

ADCF

IPH1

F7h

 

 

xx00 0000

x000 0000

0000 0000

0000 0000

0000 0000

xxxx x000

 

0000 0000

 

 

E8h

IEN1

CL

CCAP0L

CCAP1L

 

 

 

 

EFh

 

0000 0000

0000 0000

0000 0000

 

 

 

 

 

xxxx x000

 

 

 

 

 

E0h

ACC

 

 

 

 

 

 

 

E7h

 

 

 

 

 

 

 

 

 

0000 0000

 

 

 

 

 

 

 

 

D8h

CCON

CMOD

CCAPM0

CCAPM1

 

 

 

 

DFh

 

00xx x000

x000 0000

x000 0000

 

 

 

 

 

00xx xx00

 

 

 

 

 

D0h

PSW

FCON

EECON

 

 

 

 

 

D7h

 

0000 0000

xxxx xx00

 

 

 

 

 

 

0000 0000

 

 

 

 

 

 

C8h

T2CON

T2MOD

RCAP2L

RCAP2H

TL2

TH2

 

CANEN2

CFh

 

xxxx xx00

0000 0000

0000 0000

0000 0000

0000 0000

 

xxxx 0000

 

0000 0000

 

 

C0h

P4

CANGIE

 

CANIE2

CANIDM1

CANIDM2

CANIDM3

CANIDM4

C7h

 

0000 0000

 

xxx 0000

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

 

xxxx xx11

 

 

B8h

IPL0

SADEN

 

CANSIT2

CANIDT1

CANIDT2

CANIDT3

CANIDT4

BFh

 

0000 0000

 

xxxx 0000

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

 

x000 0000

 

 

B0h

P3

CANPAGE

CANSTCH

CANCONCH

CANBT1

CANBT2

CANBT3

IPH0

B7h

 

0000 0000

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

xxxx xxxx

x000 0000

 

1111 1111

 

A8h

IEN0

SADDR

CANGSTA

CANGCON

CANTIML

CANTIMH

CANSTMPL

CANSTMPH

AFh

 

0000 0000

x0x0 0000

0000 x000

0000 0000

0000 0000

0000 0000

0000 0000

 

0000 0000

 

A0h

P2

CANTCON

AUXR1

CANMSG

CANTTCL

CANTTCH

WDTRST

WDTPRG

A7h

 

0000 0000

0000 0000

xxxx xxxx

0000 0000

0000 0000

1111 1111

xxxx x000

 

xxxx xx11

 

98h

SCON

SBUF

 

CANGIT

CANTEC

CANREC

 

 

9Fh

 

0000 0000

 

0x00 0000

0000 0000

0000 0000

 

 

 

0000 0000

 

 

 

 

90h

P1

 

 

 

 

 

 

 

97h

 

 

 

 

 

 

 

 

 

1111 1111

 

 

 

 

 

 

 

 

88h

TCON

TMOD

TL0

TL1

TH0

TH1

 

CKCON

8Fh

 

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

 

0000 0000

 

0000 0000

 

 

80h

 

SP

DPL

DPH

 

 

 

PCON

87h

 

0000 0111

0000 0000

0000 0000

 

 

 

0000 0000

 

 

 

 

 

 

 

0/8(1)

1/9

2/A

3/B

4/C

5/D

6/E

7/F

 

Note:

2.These registers are bit-addressable.

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

12

Rev.A - May 17, 2001

Preliminary

T89C51CC02

6. Clock

6.1. Introduction

The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:

Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.

Saves power consumption while keeping the same CPU power (oscillator power saving).

Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.

Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software.

An extra feature is available for selected hardware in the X2 mode. This feature allows starting of the CPU in the X2 mode, without starting in the standard mode.

The hardware CPU X2 mode can be read and write via IAP (SetX2mode, ClearX2mode, ReadX2mode), see InSystem Programming section.

These IAPs are detailed in the "In-System Programming" section.

6.2. Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the

X2 to the STD mode. Figure 4 shows the mode switching waveforms.

Rev.A - May 17, 2001

13

Preliminary

T89C51CC02

 

X2

 

PCON.0

 

 

IDL

 

CKCON.0

 

 

 

 

 

X2B

 

 

 

Hardware byte

 

 

XTAL1

÷ 2

0

CPU Core

 

 

1

Clock

 

 

 

XTAL2

 

 

CPU

 

 

 

 

 

 

CLOCK

 

PD

 

CPU Core Clock Symbol

PCON.1

 

 

 

 

 

 

 

 

 

 

 

 

 

÷ 2

1

 

 

 

 

 

 

 

FT0 Clock

 

 

 

 

 

 

 

0

 

 

 

 

 

÷ 2

1

FT1 Clock

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

÷ 2

1

 

FT2 Clock

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

÷ 2

1

 

 

FUart Clock

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

÷ 2

1

 

 

 

FPca Clock

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

÷ 2

1

 

 

 

 

FWd Clock

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

÷ 2

1

 

 

 

 

 

FCan Clock

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

PERIPH

X2

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

CKCON.0

 

 

 

 

 

 

 

Peripheral Clock Symbol

CANX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

CKCON.7

CKCON.6

CKCON.5

CKCON.4

CKCON.3

CKCON.2

CKCON.1

Figure 3. Clock CPU Generation Diagram

14

Rev.A - May 17, 2001

Preliminary

T89C51CC02

XTAL1

XTAL2

X2 bit

CPU clock

STD Mode X2 Mode STD Mode

Figure 4. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 5) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.

Rev.A - May 17, 2001

15

Preliminary

T89C51CC02

6.3. Register

CKCON (S:8Fh)

Clock Control Register

7

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

CANX2

WDX2

PCAX2

 

SIX2

T2X2

T1X2

T0X2

X2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Mnemonic

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

CAN clock (1)

 

 

 

 

 

7

CANX2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

 

 

Watchdog clock (1)

 

 

 

 

 

6

WDX2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

Programmable Counter Array clock (1)

 

 

 

5

PCAX2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

Enhanced UART clock (MODE 0 and 2) (1)

 

 

 

4

SIX2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

 

 

Timer2 clock (1)

 

 

 

 

 

3

T2X2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

 

 

Timer1 clock (1)

 

 

 

 

 

2

T1X2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

 

 

Timer0 clock (1)

 

 

 

 

 

1

T0X2

Clear to select 6 clock periods per peripheral clock cycle.

 

 

 

 

Set to select 12 clock periods per peripheral clock cycle.

 

 

 

 

 

 

 

 

 

 

 

 

CPU clock

 

 

 

 

 

0

X2

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

 

 

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

 

 

 

 

 

 

 

 

 

NOTE:

1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.

Reset Value = 0000 0000b

Figure 5. CKCON Register

16

Rev.A - May 17, 2001

Preliminary

T89C51CC02

7. Program/Code Memory

7.1. Introduction

The T89C51CC02 implement 16 Kbytes of on-chip program/code memory. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the FLASH Memory can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.

3FFFh1

16 Kbytes

FLASH

0000h

T89C51CC02

Figure 6. Program/Code Memory Organization

Rev.A - May 17, 2001

17

Preliminary

T89C51CC02

7.2. FLASH Memory Architecture

T89C51CC02 features two on-chip flash memories:

Flash memory FM0:

containing 16 Kbytes of program memory (user space) organized into 128 byte pages,

Flash memory FM1:

2 Kbytes for boot loader and Application Programming Interfaces (API).

The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section.

All Read/Write access operations on FLASH Memory by user application are managed by a set of API described in the "In-System Programming" section.

Hardware Security (1 byte)

Extra Row (128 bytes)

Column Latches (128 bytes)

3FFFh

16 Kbytes

Flash memory user space

FM0

0000h

FFFFh

2 Kbytes

Flash memory boot space

FM1 F800h

FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register

Figure 7. Flash memory architecture

7.2.1. FM0 Memory Architecture

The flash memory is made up of 4 blocks (see Figure 7):

1.The memory array (user space) 16 Kbytes

2.The Extra Row

3.The Hardware security bits

4.The column latch registers

7.2.1.1. User Space

This space is composed of a 16 Kbytes FLASH memory organized in 128 pages of 128 bytes. It contains the user’s application code.

7.2.1.2. Extra Row (XRow)

This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage.

18

Rev.A - May 17, 2001

Preliminary

T89C51CC02

7.2.1.3. Hardware security space

The Hardware security space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode.

7.2.1.4. Column latches

The column latches, also part of FM0, have a size of full page (128 bytes).

The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte).

Rev.A - May 17, 2001

19

Preliminary

T89C51CC02

7.3. Overview of FM0 operations

The CPU interfaces to the flash memory through the FCON register and AUXR1 register.

These registers are used to:

Map the memory spaces in the adressable space

Launch the programming of the memory spaces

Get the status of the flash memory (busy/not busy)

Select the flash memory FM0/FM1.

7.3.1. Mapping of the memory space

By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting this bit takes precedence on the EXTRAM bit in AUXR register.

The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 13. A MOVC instruction is then used for reading these spaces.

Table 13. .FM0 blocks select bits

FMOD1

FMOD0

FM0 Adressable space

 

 

 

0

0

User (0000h-3FFFh)

 

 

 

0

1

Extra Row(FF80h-FFFFh)

 

 

 

1

0

Hardware Security (0000h)

 

 

 

1

1

reserved

 

 

 

7.3.2. Launching programming

FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A. Table 14 summarizes the memory spaces to program according to FMOD1:0 bits.

Table 14. Programming spaces

 

 

Write to FCON

 

Operation

 

 

 

 

 

 

FPL3:0

FPS

FMOD1

FMOD0

 

 

 

 

 

 

 

 

User

5

X

0

0

No action

 

 

 

 

 

A

X

0

0

Write the column latches in user space

 

Extra Row

5

X

0

1

No action

 

 

 

 

 

A

X

0

1

Write the column latches in extra row space

 

Security Space

5

X

1

0

No action

 

 

 

 

 

A

X

1

0

Write the fuse bits space

 

Reserved

5

X

1

1

No action

 

 

 

 

 

A

X

1

1

No action

 

 

 

 

 

 

 

20

Rev.A - May 17, 2001

Preliminary

T89C51CC02

The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is no more available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming.

Caution:

Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode.

7.3.3. Status of the flash memory

The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

7.3.4. Selecting FM1/FM1

The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h.

Rev.A - May 17, 2001

21

Preliminary

Column Latches
Loading
Column Latches Mapping

T89C51CC02

7.3.5. Loading the Column Latches

Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page.

When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page.

The following procedure is used to load the column latches and is summarized in Figure 8:

Map the column latch space by setting FPS bit.

Load the DPTR with the address to load.

Load Accumulator register with the data to load.

Execute the MOVX @DPTR, A instruction.

If needed loop the three last instructions until the page is completely loaded.

FPS= 1

Data Load

DPTR= Address

ACC= Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Data memory Mapping

FPS= 0

Figure 8. Column Latches Loading Procedure

22

Rev.A - May 17, 2001

Preliminary

T89C51CC02

7.3.6. Programming the FLASH Spaces

User

The following procedure is used to program the User space and is summarized in Figure 9:

Load data in the column latches from address 0000h to 3FFFh1.

Disable the interrupts.

Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared.

Enable the interrupts.

Note:

1. The last page address used when loading the column latch is the one used to select the page programming address.

Extra Row

The following procedure is used to program the Extra Row space and is summarized in Figure 9:

Load data in the column latches from address FF80h to FFFFh.

Disable the interrupts.

Launch the programming by writing the data sequence 52h followed by A2h in FCON register. The end of the programming indicated by the FBUSY flag cleared.

Enable the interrupts.

Rev.A - May 17, 2001

23

Preliminary

T89C51CC02

FLASH Spaces

Programming

Column Latches Loading

see Figure 8

Disable IT

EA= 0

Launch Programming

FCON= 5xh

FCON= Axh

FBusy

Cleared?

Erase Mode

FCON = 00h

End Programming

Enable IT

EA= 1

Figure 9. Flash and Extra row Programming Procedure

24

Rev.A - May 17, 2001

Preliminary

T89C51CC02

Hardware Security

The following procedure is used to program the Hardware Security space and is summarized in Figure 10:

Set FPS and map Harware byte (FCON = 0x0C)

Disable the interrupts.

Load DPTR at address 0000h.

Load Accumulator register with the data to load.

Execute the MOVX @DPTR, A instruction.

Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared.

Enable the interrupts.

FLASH Spaces

Programming

FCON = 0Ch

Data Load

DPTR= 00h

ACC= Data

Exec: MOVX @DPTR, A

Disable IT

EA= 0

Launch Programming

FCON= 54h

FCON= A4h

FBusy

Cleared?

Erase Mode

FCON = 00h

End Programming

Enable IT

EA= 1

Figure 10. Hardware Programming Procedure

Rev.A - May 17, 2001

25

Preliminary

T89C51CC02

7.3.7. Reading the FLASH Spaces

User

The following procedure is used to read the User space and is summarized in Figure 11:

Map the User space by writing 00h in FCON register.

Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to FFFFh.

Extra Row

The following procedure is used to read the Extra Row space and is summarized in Figure 11:

Map the Extra Row space by writing 02h in FCON register.

Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= FF80h to FFFFh.

Hardware Security

The following procedure is used to read the Hardware Security space and is summarized in Figure 11:

Map the Hardware Security space by writing 04h in FCON register.

Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h.

FLASH Spaces

Reading

FLASH Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

ACC= 0

Exec: MOVC A, @A+DPTR

Erase Mode

FCON = 00h

Figure 11. Reading Procedure

26

Rev.A - May 17, 2001

Preliminary

T89C51CC02

7.4. Registers

FCON (S:D1h)

FLASH Control Register

7

6

5

4

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

FPL3

FPL2

FPL1

FPL0

 

FPS

 

FMOD1

FMOD0

FBUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Mnemonic

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

7-4

FPL3:0

Programming Launch Command Bits

 

 

 

 

 

Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 14.)

 

 

 

 

 

 

 

 

 

 

 

 

FLASH Map Program Space

 

 

 

 

 

3

FPS

Set to map the column latch space in the data memory space.

 

 

 

 

Clear to re-map the data memory space.

 

 

 

 

 

 

 

 

 

 

 

 

 

2-1

FMOD1:0

FLASH Mode

 

 

 

 

 

 

 

See Table 13 or Table 14.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FLASH Busy

 

 

 

 

 

 

 

0

FBUSY

Set by hardware when programming is in progress.

 

 

 

Clear by hardware when programming is done.

 

 

 

 

 

 

 

 

 

 

Can not be cleared by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value= 0000 0000b

 

 

 

 

 

 

 

 

 

 

 

Figure 12. FCON Register

 

 

 

Rev.A - May 17, 2001

27

Preliminary

T89C51CC02

8. Data Memory

8.1. Introduction

The T89C51CC02 provides data memory access in two different spaces:

1.The internal space mapped in three separate segments:

the lower 128 bytes RAM segment.

the upper 128 bytes RAM segment.

the expanded 256 bytes RAM segment (ERAM).

A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 13 shows the internal data memory spaces organization.

FFh

 

FFh

Upper

FFh

Special

 

 

 

 

 

 

 

128 bytes

 

Function

 

 

 

Internal RAM

 

Registers

 

256 bytes

 

indirect addressing

 

direct addressing

 

80h

 

80h

 

 

Internal ERAM

 

 

 

7Fh

 

 

 

 

 

Lower

 

 

 

 

 

 

 

 

 

 

128 bytes

 

 

 

 

 

Internal RAM

 

 

 

 

 

direct or indirect

 

 

00h

 

00h

addressing

 

 

 

 

 

 

Figure 13. Internal Data Memory Organization

28

Rev.A - May 17, 2001

Preliminary

T89C51CC02

8.2. Internal Space

8.2.1. Lower 128 Bytes RAM

The lower 128 bytes of RAM (see Figure 13) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 16) select which bank is in use according to Table 15. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines.

Table 15. Register Bank Selection

RS1

RS0

 

Description

 

 

 

 

 

0

0

Register bank 0

from 00h

to 07h

 

 

 

 

 

0

1

Register bank 0

from 08h

to 0Fh

 

 

 

 

 

1

0

Register bank 0

from 10h

to 17h

 

 

 

 

 

1

1

Register bank 0

from 18h

to 1Fh

 

 

 

 

 

The next 16 bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.

7Fh

 

 

30h

 

 

2Fh

 

Bit-Addressable Space

 

 

20h

 

(Bit Addresses 0-7Fh)

 

 

1Fh

 

 

18h

 

 

17h

 

4 Banks of

10h

 

8 Registers

0Fh

 

 

R0-R7

08h

 

 

 

07h

 

 

00h

 

 

Figure 14. Lower 128 bytes Internal RAM Organization

8.2.2. Upper 128 Bytes RAM

The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode.

8.2.3. Expanded RAM

The on-chip 256 bytes of expanded RAM (ERAM) are accessible from address 0000h to FFh using indirect addressing mode through MOVX instructions.

Caution:

Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.

Rev.A - May 17, 2001

29

Preliminary

T89C51CC02

8.3. Dual Data Pointer

8.3.1. Description

The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses.

DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 17) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 15).

DPL0

0

 

DPL1

DPL

 

1

 

DPTR0

DPS AUXR1.0

DPTR

DPTR1

 

 

DPH0

0

 

DPH1

DPH

 

1

 

Figure 15. Dual Data Pointer Implementation

8.3.2. Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search …) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded in assembler. Latest C compiler take also advantage of this feature by providing enhanced algorithm libraries.

The INC instruction is a short (2 bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.

; ASCII block move using

dual

data

pointers

 

 

 

 

 

 

 

; Modifies

DPTR0,

DPTR1,

A and

PSW

 

 

 

 

 

 

 

 

; Ends when encountering

NULL

character

 

 

 

 

 

 

 

; Note: DPS exits opposite of

entry

state unless

an

extra

INC

AUXR1 is added

AUXR1

EQU

0A2h

 

 

 

 

 

 

 

 

 

 

move:

mov

DPTR,#SOURCE

 

; address

of

 

SOURCE

 

 

inc

AUXR1

 

 

; switch

data

pointers

 

mov

DPTR,#DEST

 

; address

of

 

DEST

 

 

 

mv_loop:

inc

AUXR1

 

 

; switch

data

pointers

 

movx

A,@DPTR

 

 

; get a

byte

from

SOURCE

 

inc

DPTR

 

 

; increment

SOURCE

address

 

inc

AUXR1

 

 

; switch

data

pointers

 

movx

@DPTR,A

 

 

; write

the

byte

 

to

DEST

 

inc

DPTR

 

 

; increment

DEST

address

 

jnz

mv_loop

 

 

; check

for

NULL

 

terminator

end_move:

 

 

 

 

 

 

 

 

 

 

 

 

30

Rev.A - May 17, 2001

Preliminary

T89C51CC02

8.4. Registers

PSW (S:8Eh)

Program Status Word Register.

7

6

5

 

4

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

CY

AC

F0

 

RS1

RS0

 

OV

F1

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Mnemonic

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

7

CY

Carry Flag

 

 

 

 

 

 

Carry out from bit 1 of ALU operands.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

AC

Auxiliary Carry Flag

 

 

 

 

 

 

Carry out from bit 1 of addition operands.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

F0

User Definable Flag 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

4-3

RS1:0

Register Bank Select Bits

 

 

 

 

 

Refer to Table 15 for bits description.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

OV

Overflow Flag

 

 

 

 

 

 

Overflow set by arithmetic operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

F1

User Definable Flag 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parity Bit

 

 

 

 

 

 

0

P

Set when ACC contains an odd number of 1’s.

 

 

 

 

 

Cleared when ACC contains an even number of 1’s.

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value= 0000 0000b

Figure 16. PSW Register

AUXR1 (S:A2h)

Auxiliary Control Register 1.

7

6

5

 

4

 

3

 

2

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

ENBOOT

 

-

 

GF3

 

0

 

-

 

DPS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Mnemonic

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7-6

-

Reserved

 

 

 

 

 

 

 

 

 

The value read from these bits is indeterminate. Do not set these bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable Boot Flash

 

 

 

 

 

 

 

 

 

5

ENBOOT

Set this bit for map the boot flash between F800h -FFFFh

 

 

 

 

 

Clear this bit for disable boot flash.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

-

Reserved

 

 

 

 

 

 

 

 

 

The value read from this bit is indeterminate. Do not set this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

GF3

General Purpose Flag 3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

0

Always Zero

 

 

 

 

 

 

 

 

 

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

-

Reserved for Data Pointer Extension.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Pointer Select Bit

 

 

 

 

 

 

 

 

 

0

DPS

Set to select second dual data pointer: DPTR1.

 

 

 

 

 

 

 

Clear to select first dual data pointer: DPTR0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value= XXXX 00X0b

Figure 17. AUXR1 Register

Rev.A - May 17, 2001

31

Preliminary

T89C51CC02

9. EEPROM data memory

9.1. General description

The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the ERAM memory space and is selected by setting control bits in the EECON register.

A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 to 128 bytes (the page size). When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row.

9.2. Write Data in the column latches

Data is written by byte to the column latches as for an ERAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must no be changed.

The following procedure is used to write to the column latches:

Set bit EEE of EECON register

Stretch the MOVX to accommodate the slow access time of the column latch

Load DPTR with the address to write

Store A register with the data to be written

Execute a MOVX @DPTR, A

If needed loop the three last instructions until the end of a 128 bytes page

9.3. Programming

The EEPROM programming consists on the following actions:

writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded.

launching programming by writing the control sequence (54h followed by A4h) to the EECON register.

EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.

The end of programming is indicated by a hardware clear of the EEBUSY flag.

32

Rev.A - May 17, 2001

Preliminary

T89C51CC02

9.4. Read Data

The following procedure is used to read the data stored in the EEPROM memory:

Set bit EEE of EECON register

Stretch the MOVX to accommodate the slow access time of the column latch

Load DPTR with the address to read

Execute a MOVX A, @DPTR

Rev.A - May 17, 2001

33

Preliminary

T89C51CC02

9.5. Registers

EECON (S:0D2h)

EEPROM Control Register

7

6

 

5

4

 

3

 

2

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

EEPL3

EEPL2

 

EEPL1

EEPL0

 

-

 

-

 

EEE

EEBUSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit Number

Bit Mnemonic

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7-4

EEPL3-0

Programming Launch command bits

 

 

 

 

 

 

Write 5Xh followed by AXh to EEPL to launch the programming.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

-

 

Reserved

 

 

 

 

 

 

 

 

 

The value read from this bit is indeterminate. Do not set this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

-

 

Reserved

 

 

 

 

 

 

 

 

 

The value read from this bit is indeterminate. Do not set this bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable EEPROM Space bit

 

 

 

 

 

 

1

EEE

Set to map the EEPROM space during MOVX instructions (Write in the column latches)

 

 

 

Clear to map the ERAM space during MOVX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Programming Busy flag

 

 

 

 

 

 

0

EEBUSY

Set by hardware when programming is in progress.

 

 

 

 

Cleared by hardware when programming is done.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Can not be set or cleared by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value= XXXX XX00b

Not bit addressable

Figure 18. EECON Register

34

Rev.A - May 17, 2001

Preliminary

T89C51CC02

10. In-System-Programming (ISP)

10.1. Introduction

With the implementation of the User ROM and the Boot ROM in Flash technology the T89C51CC02 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer programming on all stages of a product’s life:

During the final production phase, the 1st personalization of the product by parallel or serial charging of the code in the User ROM and if wanted also a customized Boot loader in the Boot memory (Atmel will provide also a standard Boot loader by default).

After assembling of the product in its final, embedded position by serial mode via the CAN bus.

This In-System-Programming (ISP) allows code modification over the total lifetime of the product.

Besides the default Boot loader Atmel will provide to the customer also all the needed Application-Programming- Interfaces (API) which are needed for the ISP. The API will be located also in the Boot memory.

This will allow the customer to have a full use of the 16 Kbyte user memory.

Two blocks flash memories are implemented (see Figure 19):

Flash memory FM0:

containing 16 Kbytes of program memory organized in page of 128 bytes,

Flash memory FM1:

2 Kbytes for default boot loader and Application Programming Interfaces (API).

The FM0 supports both, hardware (parallel) and software programming whereas FM1 supports only hardware programming.

The ISP functions are assumed by:

∙ FCON register & bit ENBOOT in AUXR1 register,

∙ Software Boot Vector (SBV), which can be read and modified by using an API or the parallel programming mode (see Figure 22)

The SBV is stored in XROW.

The Fuse bit Boot Loader Jump Bit (BLJB) can be read and modified using an API or the parallel programming mode.

The BLJB is located in the Hardware security byte (see Figure 24).

The Extra Byte (EB) and Boot Status Byte (BSB) can be modified only by using API (see Figure 24). EB is stored in XROW

The bit ENBOOT in AUXR1 register allows to map FM1 between address F800h and FFFFh of FM0.

The FM0 can be programed by:

-The Atmel boot loader, located by default in FM1.

-The user boot loader located in FM0

-The user boot loader located in FM1 in place of Atmel boot loader.

API contained in FM1 can be called by the user boot loader located in FM0 at the address [SBV]00h.

The user program simply calls the common entry point with appropriate parameters in FM1 to accomplish the desired operation (all these methods will describe in Application Notes on api-description).

Boot Flash operations include: erase block, program byte or page, verify byte or page, program security lock bit, etc. Indeed, Atmel provides the binary code of the default Flash boot loader.

Rev.A - May 17, 2001

35

Preliminary

T89C51CC02

10.2. Flash Programming and Erasure

There are three methods of programming the Flash memory:

The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1) to program FM0 will be used. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by user’s bootloader located in FM0 at [SBV]00h.

A further method exist in activating the Atmel boot loader by hardware activation.

The FM0 can be programed also by the parallel mode using a programmer.

3FFFh

Custom

Boot Loader

[SBV]00h

FFFFh

2 Kbytes IAP

bootloader

F800h FM1

FM1 mapped between FFFF and F800 when API called

16 Kbytes

Flash memory

FM0

0000h

Figure 19. Flash Memory Mapping

36

Rev.A - May 17, 2001

Preliminary

T89C51CC02

10.2.1. Flash Parallel Programming

The three lock bits in Hardware byte are programmed according to Table, will provide different level of protection for the on-chip code and data located in FM0 and FM1.

The only way for write this bits are the parallel mode.

Table 16. Program Lock bit

 

Program Lock Bits

 

 

 

 

 

 

 

Protection description

Security

LB0

LB1

LB2

 

level

 

 

 

 

 

 

 

1

 

U

U

U

No program lock features enabled. MOVC instruction executed from external program

 

memory returns non encrypted data.

 

 

 

 

 

 

 

 

 

 

 

2

 

P

U

U

MOVC instruction executed from external program memory are disabled from fetching

 

code bytes from internal memory.

 

 

 

 

 

 

 

 

 

 

 

3

 

U

P

U

Same as 2, also verify through parallel programming interface is disabled.

 

 

 

 

 

 

4

 

U

U

P

Same as 3, also external execution is disabled.

 

 

 

 

 

 

Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after Flash and Core verification. Program Lock bits

These security bits protect the code access through the parallel programming interface. They are set by default to level 4.

Rev.A - May 17, 2001

37

Preliminary

T89C51CC02

10.3 Boot Process

10.3.1. Software boot process example

Many algorithms can be used for the software boot process. Before describing them, some explanations are needed for the utility of different flags and bytes available.

Boot Loader Jump Bit (BLJB):

-This bit indicates if on RESET the user wants jump on his application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1.

-BLJB = 0 on parts delivered with bootloader programmed.

-To read or modified this bit, the APIs are used.

Boot Vector Address (SBV):

-This byte contains the msb of the user boot loader address in FM0.

-The default value of SBV is FFh (no user boot loader in FM0).

-To read or modified this byte, the APIs are used.

Extra Byte (EB) & Boot Status Byte (BSB):

-These bytes are reserved for customer use.

-To read or modified this byte, the APIs are used.

Example of software boot process in FM1 (see Figure 21)

In this example the Extra Byte (EB) is a configuration bit which forces the user boot loader execution even on the hardware condition.

10.3.2. Hardware boot process

At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the value of Boot Loader Jump Bit (BLJB).

FCON register is initialized with the value 00h and the program in FM1 can be executed.

Check of the BLJB value.

If bit BLJB is cleared (BLJB = 1):

User application in FM0 will be started at @0000h (standard reset).

If bit BLJB is set (BLJB = 0):

Boot loader will be started at @F800h in FM1.

38

Rev.A - May 17, 2001

Preliminary

T89C51CC02

Hardware

Software

ENBOOT = 0

PC = 0000h

USER APPLICATION

RESET

bit ENBOOT in AUXR1 register

is initialized with BLJB.

 

FCON = F0h

BLJB == 0

?

ENBOOT = 1

PC = F800h

Boot Loader

in FM1

Figure 20. Hardware Boot Process Algorithm

Rev.A - May 17, 2001

39

Preliminary

T89C51CC02

Hardware boot process

Software boot process

40

RESET

bit ENBOOT in AUXR1 register

is initialized with BLJB (Fuse bit).

 

 

FCON = F0h

 

 

 

 

 

 

 

 

 

BLJB == 0

 

?

USER APPLICATION

ENBOOT = 1

 

PC = F800h

FCON == 00h

?

EB == 0

?

SBV == FFh

?

USER BOOT LOADER

DEFAULT BOOT LOADER

Figure 21. Example of Software Boot process

Rev.A - May 17, 2001

Preliminary

T89C51CC02

10.4. 2 Application-Programming-Interface

Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of FLASH pages. All calls are made by functions.

All these APIs will be described in an application note.

API CALL

Description

 

 

PROGRAM DATA BYTE

Write a byte in flash memory

 

 

PROGRAM DATA PAGE

Write a page (128 bytes) in flash memory

 

 

PROGRAM EEPROM BYTE

Write a byte in Eeprom memory

 

 

ERASE BLOCK

Erase all flash memory

 

 

ERASE BOOT VECTOR (SBV)

Erase the boot vector

 

 

PROGRAM BOOT VECTOR (SBV)

Write the boot vector

 

 

PROGRAM EXTRA BYTE (EB)

Write the extra byte

 

 

READ DATA BYTE

 

 

 

READ EEPROM BYTE

 

 

 

READ FAMILY CODE

 

 

 

READ MANUFACTURER CODE

 

 

 

READ PRODUCT NAME

 

 

 

READ REVISION NUMBER

 

 

 

READ STATUS BIT (BSB)

Read the status bit

 

 

READ BOOT VECTOR (SBV)

Read the boot vector

 

 

READ EXTRA BYTE (EB)

Read the extra byte

 

 

PROGRAM X2

Write the hardware flag for X2 mode

 

 

READ X2

Read the hardware flag for X2 mode

 

 

PROGRAM BLJB

Write the hardware flag BLJB

 

 

READ BLJB

Read the hardware flag BLJB

 

 

Rev.A - May 17, 2001

41

Preliminary

T89C51CC02

10.5. Application remarks

After loading a new program using by the boot loader, the BLJB bit must be set to allow user application to start at RESET.

A user bootloader can be mapped at address [SBV]00h. The byte SBV contains the high byte of the boot address, and can be read and written by API.

The API can be called during user application, without disabling interrupt. The interrupts are disabled by some APIs, for complex operations.

42

Rev.A - May 17, 2001

Preliminary

+ 95 hidden pages