W25Q80, W25Q16, W25Q32
Advanced Information
8M-BIT, 16M-BIT AND 32M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: June 20, 2007
- 1 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
Table of Contents
1. GENERAL DESCRIPTION .........................................................................................................5
2. FEATURES................................................................................................................................. 5
3. PIN CONFIGURATION SOIC 208-MIL....................................................................................... 6
4. PIN CONFIGURATION WSON 6X5-MM....................................................................................6
5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM........................................................ 6
6. PIN CONFIGURATION SOIC 300-MIL....................................................................................... 7
7. PIN DESCRIPTION SOIC 300-MIL ............................................................................................ 7
7.1 Package Types............................................................................................................... 8
7.2 Chip Select (/CS)............................................................................................................ 8
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .............................. 8
7.4 Write Protect (/WP).........................................................................................................8
7.5 HOLD (/HOLD) ............................................................................................................... 8
7.6 Serial Clock (CLK)..........................................................................................................8
8. BLOCK DIAGRAM......................................................................................................................9
9. FUNCTIONAL DESCRIPTION ................................................................................................. 10
9.1 SPI OPERATIONS ....................................................................................................... 10
9.1.1 Standard SPI Instructions ...............................................................................................10
9.1.2 Dual SPI Instructions......................................................................................................10
9.1.3 Quad SPI Instructions.....................................................................................................10
9.1.4 Hold Function.................................................................................................................10
9.2 WRITE PROTECTION.................................................................................................. 11
9.2.1 Write Protect Features....................................................................................................11
10. CONTROL AND STATUS REGISTERS................................................................................... 12
10.1 STATUS REGISTER....................................................................................................12
10.1.1 BUSY............................................................................................................................12
10.1.2 Write Enable Latch (WEL)............................................................................................12
10.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................12
10.1.4 Top/Bottom Block Protect (TB).....................................................................................12
10.1.5 Sector/Block Protect (SEC)..........................................................................................12
10.1.6 Status Register Protect (SRP1, SRP0)......................................................................... 13
10.1.7 Quad Enable (QE)........................................................................................................13
10.1.8 Status Register Memory Protection..............................................................................15
10.2 INSTRUCTIONS...........................................................................................................18
10.2.1 Manufacturer and Device Identification ........................................................................18
10.2.2 Instruction Set Table 1..................................................................................................19
10.2.3 Instruction Set Table 2 (Read Instructions) ..................................................................20
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W25Q80, W25Q16, W25Q32
10.2.4 Write Enable (06h)........................................................................................................21
10.2.5 Write Disable (04h).......................................................................................................21
10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h).................................22
10.2.7 Write Status Register (01h)..........................................................................................23
10.2.8 Read Data (03h)...........................................................................................................24
10.2.9 Fast Read (0Bh)...........................................................................................................25
10.2.10 Fast Read Dual Output (3Bh).....................................................................................26
10.2.11 Fast Read Quad Output (6Bh)....................................................................................27
10.2.12 Fast Read Dual I/O (BBh)...........................................................................................28
10.2.13 Fast Read Quad I/O (EBh).........................................................................................30
10.2.14 Page Program (02h)...................................................................................................32
10.2.15 Quad Input Page Program (32h) ................................................................................33
10.2.16 Sector Erase (20h) .....................................................................................................34
10.2.17 32KB Block Erase (52h).............................................................................................35
10.2.18 64KB Block Erase (D8h).............................................................................................36
10.2.19 Chip Erase (C7h / 60h)...............................................................................................37
10.2.20 Erase Suspend (75h)..................................................................................................38
10.2.21 Erase Resume (7Ah)..................................................................................................38
10.2.22 Power-down (B9h)......................................................................................................39
10.2.23 High Performance Mode (A3h)...................................................................................40
10.2.24 Release Power-down or High Performance Mode / Device ID (ABh).........................40
10.2.25 Read Manufacturer / Device ID (90h).........................................................................42
10.2.26 Read Unique ID Number ............................................................................................43
10.2.27 JEDEC ID (9Fh) .........................................................................................................44
10.2.28 Mode Bit Reset (FFh).................................................................................................45
11. ELECTRICAL CHARACTERISTICS (PRELIMINARY)............................................................. 46
11.1 Absolute Maximum Ratings.......................................................................................... 46
11.2 Operating Ranges......................................................................................................... 46
11.3 Endurance and Data Retention....................................................................................47
11.4 Power-up Timing and Write Inhibit Threshold ..............................................................47
11.5 DC Electrical Characteristics........................................................................................ 48
11.6 AC Measurement Conditions........................................................................................ 49
11.7 AC Electrical Characteristics ........................................................................................ 50
11.8 AC Electrical Characteristics (cont’d)...........................................................................51
11.9 Serial Output Timing..................................................................................................... 52
11.10 Input Timing................................................................................................................. 52
11.11 Hold Timing .................................................................................................................52
12. PACKAGE SPECIFICATION.................................................................................................... 53
12.1 8-Pin SOIC 208-mil (Package Code SS)...................................................................... 53
Publication Release Date: June 20, 2007
- 3 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
12.2 8-Pin PDIP 300-mil (Package Code DA)...................................................................... 54
12.3 8-contact 6x5 WSON.................................................................................................... 55
12.4 8-contact 6x5 WSON Cont’d. ....................................................................................... 56
12.5 16-Pin SOIC 300-mil (Winbond Package Code SF)..................................................... 57
13. ORDERING INFORMATION .................................................................................................... 58
14. REVISION HISTORY................................................................................................................ 59
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W25Q80, W25Q16, W25Q32
1. GENERAL DESCRIPTION
The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a
storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and
performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM,
executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices
operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and
1µA for power-down. All devices are offered in space-saving packages.
The W25Q80/16/32 array is organized into 4,096/8,192/16,384 programmable pages of 256-bytes
each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can
be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB
block erase) or the entire chip (chip erase). The W25Q80/16/32 has 256/512/1024 erasable sectors
and 16/32/64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q80/16/32 supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI using SPI pins: Serial Clock, Chip Select, Serial Data
I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are
supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output
when using the Fast Read Dual/Quad Output instructions. These transfer rates are comparable to
those of 8 and 16-bit Parallel Flash memories.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification with a 64-bit Unique Serial Number.
2. FEATURES
• Family of SpiFlash Memories
– W25Q80: 8M-bit / 1M -byte (1,048,576)
– W25Q16: 16M-bit / 2M-byte (2,097,152)
– W25Q32: 32M-bit / 4M-byte (4,194,304)
– 256-bytes per programmable page
• Standard, Dual or Quad SPI
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO
– Quad SPI: CLK, /CS, IO
• Highest Performance Serial Flash
– Up to 6X that of ordinary Serial Flash
– 80MHz clock operation
– 160MHz equivalent Dual SPI
– 320MHz equivalent Quad SPI
– 40MB/S continuous data transfer rate
– 30MB/S random access (32-byte fetch)
– Comparable to X16 Parallel Flash
, IO1, /WP, /Hold
0
, IO1, IO2, IO3
0
• Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Block Erase (32K and 64K-bytes)
– Program one to 256 bytes
– Up to 100,000 erase/write cycles
– 20-year data retention
• Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, <1µA Power-down (typ.)
– -40°C to +85°C operating range
• Advanced Security Features
– Software and Hardware Write-Protect
– Top or Bottom, Sector or Block selection
– Lock-Down and OTP protection
– 64-Bit Unique ID for each device
• Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 6x5-mm (W25Q80 & W25Q16)
–16-pin SOIC 300-mil (W25Q16 & W25Q32)
Publication Release Date: June 20, 2007
- 5 - Advanced - Revision A5
3. PIN CONFIGURATION SOIC 208-MIL
Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS)
4. PAD CONFIGURATION WSON 6X5-MM
W25Q80, W25Q16, W25Q32
Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP)
5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM
PIN NO. PIN NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)*1
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)*1
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
8 VCC Power Supply
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0 – IO3 are used for Quad instructions
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6. PIN CONFIGURATION SOIC 300-MIL
Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
W25Q80, W25Q16, W25Q32
7. PIN DESCRIPTION SOIC 300-MIL
PAD NO. PAD NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)*1
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)*1
16 CLK I Serial Clock Input
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0 – IO3 are used for Quad instructions
- 7 - Advanced - Revision A5
Publication Release Date: June 20, 2007
W25Q80, W25Q16, W25Q32
7.1 Package Types
W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON
(package code ZP). W25Q16 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and
6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a
16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and
dimensions are illustrated at the end of this datasheet.
7.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program
or status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 30). If
needed a pull-up resister on /CS can be used to accomplish this.
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q80/16/32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be
set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3.
7.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (SEC. TB. BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP
pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write
Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, and 1c for the pin
configuration of Quad I/O operation.
7.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since
this pin is used for IO3. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation.
7.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Operations")
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8. BLOCK DIAGRAM
W25Q80, W25Q16, W25Q32
Figure 2. W25Q80, W25Q16 and W25Q32 Block Diagram
Publication Release Date: June 20, 2007
- 9 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
9. FUNCTIONAL DESCRIPTION
9.1 SPI OPERATIONS
9.1.1 Standard SPI Instructions
The W25Q80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the
falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising
edges of /CS.
9.1.2 Dual SPI Instructions
The W25Q80/16/32 supports Dual SPI operation when using the "Fast Read Dual Output and Dual I/O"
(3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at
two to three times the rate of ordinary Serial Flash devices. The Dual Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become
bidirectional I/0 pins; IO0 and IO1.
9.1.3 Quad SPI Instructions
The W25Q80/16/32 supports Quad SPI operation when using the "Fast Read Quad Output and Fast
Read Quad I/O" (6B and EB hex respectively). These instructions allow data to be transferred to or from
the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a
significant improvement in continuous and random access transfer rates allowing fast code-shadowing
to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO
pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set..
9.1.4 Hold Function
The /HOLD signal allows the W25Q80/16/32 operation to be paused while it is actively selected (when
/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are
shared with other devices. For example, consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not
during Quad SPI.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on
the rising edge of the /HOLD signal if the CLK signal is already lo w. If the CLK is not already low the
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W25Q80, W25Q16, W25Q32
/HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial
Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored.
The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to
avoid resetting the internal logic state of the device.
9.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
W25Q80/16/32 provides several means to protect data from inadvertent writes.
9.2.1 Write Protect Features
• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automatic write disable after program and erase
• Software and Hardware (/WP pin) write protection using Status Register
• Write Protection using Power-down instruction
• Lock Down write protection until next power-up
• One Time Program (OTP) write protection
Upon power-up or at power-down the W25Q80/16/32 will maintain a reset condition while VCC is below
the threshold value of V
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds V
This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write
Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at
power-up until the VCC-min level and t
be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,
Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the
Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information. Additionally, the Power-down instruction offers an
extra level of write protection as all instructions are ignored except for the Release Power-down
instruction.
WI, all program and erase related instructions are further disabled for a time delay of tPUW.
WI, (See Power-up Timing and Voltage Levels and Figure 29). While reset, all
VSL time delay is reached. If needed a pull-up resister on /CS can
Publication Release Date: June 20, 2007
- 11 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10. CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the
devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by
the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and
in some cases the /WP pin.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this
time the device will ignore further instructions except for the Read Status Register and Erase Suspend
instruction (see t
register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is
ready for further instructions.
W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see t
be protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
W in AC characteristics). All, none or a portion of the memory array can
10.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
10.1.5 Sector/Block Protect (SEC)
The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB
Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as
shown in the Status Register Memory Protection table. The default setting is SEC=0.
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W25Q80, W25Q16, W25Q32
10.1.6 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0 /WP
0 0 X
0 1 0
0 1 1
1 0 X
1 1 X
Note:
1. When SRP1, SRP0 = (1,0), a power-down, power-up cycle will change SRP1, SRP0 to (0,0) state.
Status
Register
Software
Protection
Hardware
Protected
Hardware
Unprotected
Power Supply
Lock-Down
One Time
Program
Description
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When /WP pin is low the Status Register locked and can not
be written to.
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.
Status Register is permanently protected and can not be
written to.
(1)
10.1.7 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad
operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When
the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the
/WP or /HOLD pins are tied directly to the power supply or ground.
Publication Release Date: June 20, 2007
- 13 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
Figure 3a. Status Register-1
Figure 3b. Status Register-2
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W25Q80, W25Q16, W25Q32
10.1.8 Status Register Memory Protection
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 63 3F0000h - 3FFFFFh 64KB Upper 1/64
0 0 0 1 0 62 and 63 3E0000h - 3FFFFFh 128KB Upper 1/32
0 0 0 1 1 60 thru 63 3C0000h - 3FFFFFh 256KB Upper 1/16
0 0 1 0 0 56 thru 63 380000h - 3FFFFFh 512KB Upper 1/8
0 0 1 0 1 48 thru 63 300000h - 3FFFFFh 1MB Upper 1/4
0 0 1 1 0 32 thru 63 200000h - 3FFFFFh 2MB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/64
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/32
(1)
W25Q32 (32M-BIT) MEMORY PROTECTION
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/16
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/8
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/4
0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2
X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4MB ALL
1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB Top Block
1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB Top Block
1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB Top Block
1 0 1 X X 63 3F8000h – 3FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
Publication Release Date: June 20, 2007
- 15 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 31 1F0000h - 1FFFFFh 64KB Upper 1/32
0 0 0 1 0 30 and 31 1E0000h - 1FFFFFh 128KB Upper 1/16
0 0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 256KB Upper 1/8
0 0 1 0 0 24 thru 31 180000h - 1FFFFFh 512KB Upper 1/4
0 0 1 0 1 16 thru 31 100000h - 1FFFFFh 1MB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/32
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/16
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/8
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/4
(1)
W25Q16 (16M-BIT) MEMORY PROTECTION
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2
X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2MB ALL
1 0 0 0 1 31 1FF000h – 1FFFFFh 4KB Top Block
1 0 0 1 0 31 1FE000h – 1FFFFFh 8KB Top Block
1 0 0 1 1 31 1FC000h – 1FFFFFh 16KB Top Block
1 0 1 X X 31 1F8000h – 1FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
- 16 -
W25Q80, W25Q16, W25Q32
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 15 0F0000h - 0FFFFFh 64KB Upper 1/16
0 0 0 1 0 14 and 15 0E0000h - 0FFFFFh 128KB Upper 1/8
0 0 0 1 1 12 thru 15 0C0000h - 0FFFFFh 256KB Upper 1/4
0 0 1 0 0 8 thru 15 080000h - 0FFFFFh 512KB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/16
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/8
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/4
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/2
(1)
W25Q80 (8M-BIT) MEMORY PROTECTION
X X 1 1 X 0 thru 15 000000h – 0FFFFFh 1MB ALL
1 0 0 0 1 15 0FF000h – 0FFFFFh 4KB Top Block
1 0 0 1 0 15 0FE000h – 0FFFFFh 8KB Top Block
1 0 0 1 1 15 0FC000h – 0FFFFFh 16KB Top Block
1 0 1 X X 15 0F8000h – 0FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
Note:
1. x = don’t care
Publication Release Date: June 20, 2007
- 17 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2 INSTRUCTIONS
The instruction set of the W25Q80/16/32 consists of fifteen basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 19. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full
8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the
device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when
the Status Register is being written, all instructions except for Read Status Register will be ignored until
the program or erase cycle has completed.
10.2.1 Manufacturer and Device Identification
MANUFACTURER ID (M7-M0)
Winbond Serial Flash
Device ID (ID7-ID0)
Instruction ABh, 90h
W25Q80 13h
W25Q16 14h
W25Q32 15h
EFh
(ID15-ID0)
9Fh
4014h
4015h
4016h
- 18 -
10.2.2 Instruction Set Table 1
(1)
W25Q80, W25Q16, W25Q32
INSTRUCTION
NAME
Write Enable 06h
Write Disable 04h
Read Status Register-1 05h (S7–S0) 2
Read Status Register-2 35h (S15-S8) 2
Write Status Register 01h (S7–S0) (S15-S8)
Page Program 02h A23–A16 A15–A8 A7–A0 (D7–D0)
Quad Page Program 32h A23–A16 A15–A8 A7–A0 (D7–D0, …)
Block Erase (64KB) D8h A23–A16 A15–A8 A7–A0
Block Erase (32KB) 52h A23–A16 A15–A8 A7–A0
Sector Erase (4KB) 20h A23–A16 A15–A8 A7–A0
Chip Erase C7h/60h
Erase Suspend 75h
Erase Resume 7Ah
Power-down B9h
High Performance Mode A3h dummy dummy dummy
Mode Bit Reset
(4)
FFh
BYTE 1
(CODE)
BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
3
Release Power down or
HPM / Device ID
Manufacturer/
Device ID
Read Unique ID 4Bh dummy dummy dummy Dummy (ID63-ID0)
JEDEC ID 9Fh
(6)
ABh dummy dummy dummy (ID7-ID0)
90h dummy dummy 00h (M7-M0) (ID7-ID0)
(M7-M0)
Manufacturer
(ID15-ID8)
Memory Type
(ID7-ID0)
Capacity
5
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being
read from the device on the DO pin.
2. The Status Register contents will repeat continuously until /CS terminates the instruction.
3. Quad Page Program Input Data
IO0 = (D4, D0, ……)
IO1 = (D5, D1, ……)
IO2 = (D6, D2, ……)
IO3 = (D7, D3, ……)
4. This instruction is recommended when using the Dual or Quad Mode bit feature. See section 10.2.28 for more
information.
5. The Device ID will repeat continuously until /CS terminates the instruction.
6. See Manufacturer and Device Identification table for Device ID information.
Publication Release Date: June 20, 2007
- 19 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.3 Instruction Set Table 2 (Read Instructions)
INSTRUCTION
NAME
Read Data 03h A23–A16 A15–A8 A7–A0 (D7–D0)
Fast Read 0Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0)
Fast Read Dual Output 3Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …)
Fast Read Dual I/O BBh A23-A8 2 A7-A0, M7-M0
Fast Read Quad Output 6Bh A23–A16 A15–A8 A7–A0 dummy (D7–D0, …)
Fast Read Quad I/O EBh A23-A0, M7-M0 4(x,x,x,x, D7–D0, …) 5(D7-D0, …)
BYTE 1
(CODE)
BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
2
(D7–D0, …)
1
3
1
3
Notes:
1: Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2: Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3: Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4: Quad Input Address
IO0 = A20, A16, A12, A8 , A4, A0, M4, M0
IO1 = A21, A17, A13, A9 , A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5: Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0, …..)
IO1 = (x, x, x, x, D5, D1, …..)
IO2 = (x, x, x, x, D6, D2, …..)
IO3 = (x, x, x, x, D7, D3, …..)
- 20 -
W25Q80, W25Q16, W25Q32
10.2.4 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and
Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the
instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
Figure 4. Write Enable Instruction Sequence Diagram
10.2.5 Write Disable (04h)
The Write Disable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into
the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and
upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip
Erase instructions.
Figure 5. Write Disable Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 21 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 and “35h” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 6. The
Status Register bits are shown in figure 3a and 3b and include the BUSY, WEL, BP2-BP0, TB, SEC,
SRP0, SRP1 and QE bits (see description of the Status Register earlier in this datasheet).
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 6. The instruction is completed by driving /CS high.
Figure 6. Read Status Register Instruction Sequence Diagram
- 22 -
W25Q80, W25Q16, W25Q32
10.2.7 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction
(Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS
low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in
figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status
Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to. All other Status Register
bit locations are read-only and will not be affected by the Write Status Register instruction.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not
done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth
clock (compatible with the 25X series) the QE and SRP1 bits will be cleared to 0. After /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of t
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions
again. After the Write Register cycle has finished the Write Enable Latch (WEL) bit in the Status
Register will be cleared to 0.
W (See AC
The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0) to be
set for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table and description). The Write
Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to be set. Those
bits are used in conjunction with the Write Protect (/WP) pin, Lock out or OTP features to disable writes
to the status register. Please refer to 10.1.16 for detailed descriptions regarding Status Register
protection methods. Factory default for all status Register bits are 0.
Figure 7. Write Status Register Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 23 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.8 Read Data (03h)
The Read Data instruction allows one more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by
a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of
the CLK pin. After the address is received, the data byte of the addressed memory location will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single instruction
as long as the clock continues. The instruction is completed by driving /CS high. The Read Data
instruction sequence is shown in figure 8. If a Read Data instruction is issued while an Erase, Program
or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the
current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of f
Electrical Characteristics).
R (see AC
Figure 8. Read Data Instruction Sequence Diagram
- 24 -
W25Q80, W25Q16, W25Q32
10.2.9 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of F
eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the
devices internal circuits additional time for setting up the initial address. During the dummy clocks the
data value on the DO pin is a “don’t care”.
R (see AC Electrical Characteristics). This is accomplished by adding
Figure 9. Fast Read Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 25 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.10 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins; IO
W25Q80/16/32 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal
for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the IO
out clock.
pin should be high-impedance prior to the falling edge of the first data
0
and IO1. This allows data to be transferred from the
0
Figure 10. Fast Read Dual Output Instruction Sequence Diagram
- 26 -
W25Q80, W25Q16, W25Q32
10.2.11 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO
be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit
QE must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the
W25Q80/16/32 at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit
address as shown in figure 11. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
, IO1, IO2, and IO3. A Quad enable of Status Register-2 must
0
Figure 11. Fast Read Quad Output Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 27 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.12 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications. To ensure optimum performance the
High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the Fast Read Dual
I/O Instruction.
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the Mode
bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The upper nibble of the Mode
(M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“x”). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the Mode bits (M7-0) equals “Ax” hex, then the next Fast Read Dual I/O instruction (after /CS is raised
and then lowered) does not require the BBh instruction code, as shown in figure 12b.. This reduces the
instruction sequence by eight clocks and allows the address to be immediately entered after /CS is
asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the next instruction (after /CS is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal instructions
(See 10.2.28 for detailed descriptions).
and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
0
Figure 12a. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)
- 28 -
W25Q80, W25Q16, W25Q32
Figure 12b. Fast Read Dual Input/Output Instruction Sequence Diagram (M7-0 = Axh)
Publication Release Date: June 20, 2007
- 29 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.13 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO
clock are required prior to the data output
The Quad I/O dramatically reduces instruction overhead
.
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable
bit (QE) of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. To ensure
optimum performance the High Performance Mode (HPM) instruction (A3h) must be executed once,
prior to the Fast Read Quad I/O Instruction.
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode
bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The upper nibble of the Mode
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the Mode (M3-0) are don’t care (“x”). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the Mode bits (M7-0) equals “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in figure 13b. This
reduces the instruction sequence by eight clocks and allows the address to be immediately entered
after /CS is asserted low. If the Mode bits (M7-0) are any value other than “Ax” hex, the next instruction
(after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal
operation. A Mode Bit Reset instruction can be used to reset Mode Bits (M7-0) before issuing normal
instructions (See 10.2.28 for detailed descriptions).
, IO1, IO2 and IO3 and four Dummy
0
Figure 13a. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = 0xh or NOT Axh)
- 30 -
W25Q80, W25Q16, W25Q32
Figure 13b. Fast Read Quad Input/Output Instruction Sequence Diagram (M7-0 = Axh)
Publication Release Date: June 20, 2007
- 31 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.14 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the
device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated
by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0)
and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the
instruction while data is being sent to the device. The Page Program instruction sequence is shown in
figure 14.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than
256 bytes (a partial page) can be programmed without having any effect on other bytes within the same
page. One condition to perform a partial page program is that the number of clocks can not exceed the
remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the
beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is
protected by the Block Protect (BP2, BP1, and BP0) bits.
Figure 14. Page Program Instruction Sequence Diagram
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W25Q80, W25Q16, W25Q32
10.2.15 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction
since the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction
code “32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS
pin must be held low for the entire length of the instruction while data is being sent to the device. All
other functions of Quad Page Program are identical to standard Page Program. The Quad Page
Program instruction sequence is shown in figure 15.
, IO1, IO2, and IO3. The Quad Page Program can
0
Figure 15. Quad Input Page Program Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 33 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.16 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The
Sector Erase instruction sequence is shown in figure 16.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of t
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
SE (See AC Characteristics). While the Sector Erase
Figure 16. Sector Erase Instruction Sequence Diagram
- 34 -
W25Q80, W25Q16, W25Q32
10.2.17 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2). The
Block Erase instruction sequence is shown in figure 17.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of t
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
BE1 (See AC Characteristics). While the Block Erase
Figure 17. 32KB Block Erase Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 35 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.18 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2). The
Block Erase instruction sequence is shown in figure 18.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of t
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
BE (See AC Characteristics). While the Block Erase
Figure 18. 64KB Block Erase Instruction Sequence Diagram
- 36 -
W25Q80, W25Q16, W25Q32
10.2.19 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 19.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of t
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit.
The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory
Protection table).
CE (See AC Characteristics). While the Chip Erase cycle is in
Figure 19. Chip Erase Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 37 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.20 Erase Suspend (75h)
The Erase Suspend instruction “75h”, allows the system to interrupt a sector or block erase operation
and then read from or program data to, any other sector or block. The Write Status Register instruction
(01h) and Erase instructions (20h, 52h, D8, C7h, 60h ) are not allowed during suspend. Erase Suspend
is valid only during the sector or block erase operation. If written during the chip erase or program
operation, the Erase Suspend instruction is ignored. A maximum of time of “tsus” (See AC
Characteristics) is required to suspend the erase operation. The BUSY bit in the Status register will
clear to 0 after Erase Suspend.
Figure 20. Erase Suspend Instruction Sequence
10.2.21 Erase Resume (7Ah)
The Erase Resume instruction must be written to resume the sector or block erase operation after an
Erase Suspend. After issued the BUSY bit in the status register will be set to a 1 and the sector or block
will complete the erase operation. Resume instructions will be ignored unless an Erase Suspend
operation is active.
Figure 21. Erase Resume Instruction Sequence
- 38 -
W25Q80, W25Q16, W25Q32
10.2.22 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in figure 22.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Powerdown instruction will not be executed. After /CS is driven high, the power-down state will entered within
the time duration of t
Power-down / Device ID instruction, which restores the device to normal operation, will be recognized.
All other instructions are ignored. This includes the Read Status Register instruction, which is always
available during normal operation. Ignoring all but one instruction makes the Power Down state a useful
condition for securing maximum write protection. The device always powers-up in the normal operation
with the standby current of ICC1.
DP (See AC Characteristics). While in the power-down state only the Release from
Figure 22. Deep Power-down Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 39 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.23 High Performance Mode (A3h)
The High Performance Mode (HPM) instruction must be executed prior to Dual or Quad I/O instructions
when operating at high frequencies (see FR and FR1 in AC Electrical Characteristics). This instruction
allows pre-charging of internal charge pumps so the voltages required for accessing the Flash memory
array are readily available. The instruction sequence includes the A3h instruction code followed by
three dummy clocks not shown in Fig. 23. (Contact Winbond for the latest 25Q data sheet with updated
HPM diagram). After the HPM instruction is executed, the device will maintain a slightly higher standby
current (Icc3) than standard SPI operation. The Release from Power-down or HPM instruction (ABh)
can be used to return to standard SPI standby current (Icc1).
Figure 23. High Performance Mode Instruction Sequence
10.2.24 Release Power-down or High Performance Mode / Device ID (ABh)
The Release from Power-down or High performance Mode / Device ID instruction is a multi-purpose
instruction. It can be used to release the device from the power-down state or High Performance Mode,
or obtain the devices electronic identification (ID) number.
To release the device from the power-down state or High Performance Mode, the instruction is issued
by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 24.
Release from power-down will take the time duration of t
device will resume normal operation and other instructions are accepted. The /CS pin must remain high
during the t
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
figure 25. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in Manufacturer and
Device Identification table. The Device ID can be read continuously. The instruction is completed by
driving /CS high.
RES1 time duration.
RES1 (See AC Characteristics) before the
- 40 -
W25Q80, W25Q16, W25Q32
When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in figure 25, except that after /CS is driven high it must
remain high for a time duration of t
resume normal operation and other instructions will be accepted. If the Release from Power-down /
Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY
equals 1) the instruction is ignored and will not have any effects on the current cycle
RES2 (See AC Characteristics). After this time duration the device will
Figure 24. Release Power-down/High Performance Mode Instruction Sequence
Figure 25. Release Power-down / Device ID Instruction Sequence Diagram
Publication Release Date: June 20, 2007
- 41 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.25 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device
ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device
ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code
“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond
(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in figure 26. The Device ID values for the W25Q80, W25Q16, and W25Q32 are listed in
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device
ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be
read continuously, alternating from one to the other. The instruction is completed by driving /CS high.
Figure 26. Read Manufacturer / Device ID Diagram
- 42 -
W25Q80, W25Q16, W25Q32
10.2.26 Read Unique ID Number
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique
to each W25Q80, W25Q16 or W25Q64 device. The ID number can be used in conjunction with user
software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is
initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of
dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 27.
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 101 102 103
Figure 27. Read Unique ID Number Instruction Sequence
Publication Release Date: June 20, 2007
- 43 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10.2.27 JEDEC ID (9Fh)
For compatibility reasons, the W25Q80/16/32 provides several instructions to electronically determine
the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for
SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS
pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond
(EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on
the falling edge of CLK with most significant bit (MSB) first as shown in figure 28. For memory type and
capacity values refer to Manufacturer and Device Identification table.
Figure 28. Read JEDEC ID
- 44 -
W25Q80, W25Q16, W25Q32
10.2.28 Mode Bit Reset (FFh)
For Fast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to further reduce
instruction overhead. By setting the Mode Bits (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O
operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and 10.2.13
Fast Read Quad I/O for detail descriptions).
If the system controller is Reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the 25Q16/32/80. However, as with most SPI Serial Flash
memories, the 25Q80/16/32 does not have a hardware Reset pin, so if Mode bits are set to “Ax”
hex, the 25Q80/16/32 will not recognize any standard SPI instructions. To address this possibility, it is
recommended to issue a Mode Bit Reset instruction “FFh” as the first instruction after a system Reset.
Doing so will release the Mode Bits for the “Ax” hex state and allow Standard SPI instructions to be
recognized. The Mode Bits Reset instruction is shown in figure 29.
/CS
CLK
IO0
IO1
IO2
IO3
Instruction (FFh)
Don’t Care
Don’t Care
Don’t Care
Figure 29. Mode Bit Reset for Fast Read Dual/Quad I/O
Publication Release Date: June 20, 2007
- 45 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
11. ELECTRICAL CHARACTERISTICS (PRELIMINARY)
11.1 Absolute Maximum Ratings
PARAMETERS SYMBOL CONDITIONS RANGE UNIT
(1)
(4)
Supply Voltage VCC –0.6 to +4.0 V
Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC +0.4 V
Transient Voltage on any Pin VIOT
Storage Temperature TSTG –65 to +150
Lead Temperature TLEAD See Note
Electrostatic Discharge Voltage VESD Human Body Model
<20nS Transient
Relative to Ground
–2.0V to VCC+2.0V V
(2)
(3)
–2000 to +2000 V
°C
°C
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation
outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device
reliability. Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and
the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
4. See preliminary designation at the end of this datasheet.
11.2 Operating Ranges
PARAMETER SYMBOL CONDITIONS
= 80MHz, F
F
Supply Voltage
Ambient Temperature,
Operating
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of the programming
(erase/write) voltage.
(1)
VCC
A
T
R
= 70MHz
F
R1
Commercial
Industrial
& fR = 50MHz,
R1
- 46 -
SPEC
MIN MAX
2.7
3.0
0
–40
3.6
3.6
+70
+85
UNIT
V
°C
W25Q80, W25Q16, W25Q32
11.3 Endurance and Data Retention
PARAMETER CONDITIONS MIN MAX UNIT
Erase/Program Cycles 4KB sector, 32/64KB block or full chip. 100,000 cycles
Data Retention Full Temperature Range 20 years
11.4 Power-up Timing and Write Inhibit Threshold
PARAMETER SYMBOL
VCC (min) to /CS Low tVSL
Time Delay Before Write Instruction tPUW
Write Inhibit Threshold Voltage VWI
Note:
1. These parameters are characterized only.
(1)
10 µs
(1)
1 10 ms
(1)
1 2 V
SPEC
MIN MAX
UNIT
Figure 30. Power-up Timing and Voltage Levels
Publication Release Date: June 20, 2007
- 47 - Advanced - Revision A5
11.5 DC Electrical Characteristics
W25Q80, W25Q16, W25Q32
PARAMETER SYMBOL CONDITIONS
SPEC
MIN TYP MAX
Input Capacitance CIN
Output Capacitance Cout
Input Leakage ILI
I/O Leakage ILO
Standby Current ICC1
Power-down Current ICC2
High performance
current
Current Read Data /
Dual /Quad 1MHz
Current Read Data /
Dual /Quad 33MHz
Current Read Data /
Dual /Quad 50MHz
Current Read Data /
Dual Output Read/Quad
Output Read 80MHz
Current Write Status
Register
Current Page Program ICC7 /CS = VCC
Current Sector/Block
Erase
Current Chip Erase ICC9 /CS = VCC
Input Low Voltage VIL
Input High Voltage VIH
Output Low Voltage VOL IOL = 1.6 mA
Output High Voltage VOH IOH = –100 µA
Notes:
1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.
2. Checker Board Pattern.
(2)
(2)
(2)
(2)
(1)
VIN = 0V
(1)
VOUT = 0V
/CS = VCC,
VIN = GND or VCC
/CS = VCC,
VIN = GND or VCC
I
CC3
I
CC4
I
CC4
I
CC4
CC4
I
I
CC6 /CS = VCC
I
CC8 /CS = VCC
After enable High
Performance mode
C = 0.1 VCC / 0.9 VCC
DO = Open
C = 0.1 VCC / 0.9 VCC
DO = Open
C = 0.1 VCC / 0.9 VCC
DO = Open
C = 0.1 VCC / 0.9 VCC
DO = Open
(2)
(2)
6 Pf
8 Pf
±2 µA
±2 µA
25 50 µA
1 5 µA
50 100 µA
4/5/6 6/7.5/9 mA
6/7/8 9/10.5/12 mA
7/8/9 10/12/13.5 mA
10/11/12 15/16.5/18 mA
8 12 mA
20 25 mA
20 25 mA
20 25 mA
–0.5 VCC x 0.3 V
VCC x0.7 VCC +0.4 V
0.4 V
VCC –0.2 V
UNIT
- 48 -
11.6 AC Measurement Conditions
W25Q80, W25Q16, W25Q32
PARAMETER SYMBOL
MIN MAX
SPEC
UNIT
Load Capacitance CL 30 pF
Input Rise and Fall Times TR, TF 5 ns
Input Pulse Voltages VIN 0.2 VCC to 0.8 VCC V
Input Timing Reference Voltages IN 0.3 VCC to 0.7 VCC V
Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 31. AC Measurement I/O Waveform
Publication Release Date: June 20, 2007
- 49 - Advanced - Revision A5
11.7 AC Electrical Characteristics
W25Q80, W25Q16, W25Q32
DESCRIPTION SYMBOL ALT
MIN TYP MAX
SPEC
UNIT
Clock frequency
for all instructions, except Read Data (03h)
f
F
R
C
D.C. 80 MHz
2.7V-3.6V VCC & Industrial Temperature
Clock freq. Read Data instruction (03h) fR D.C. 50 MHz
Clock High, Low Time except Read Data (03h) tCLH,
t
CLL
Clock High, Low Time for Read Data (03h)
instruction
tCRLH,
CRLL
t
Clock Rise Time peak to peak tCLCH
Clock Fall Time peak to peak tCHCL
(1)
(1)
(2)
(2)
6/7 ns
8 ns
0.1 V/ns
0.1 V/ns
/CS Active Setup Time relative to CLK tSLCH tCSS 5 ns
/CS Not Active Hold Time relative to CLK tCHSL 5 ns
Data In Setup Time tDVCH tDSU 2 ns
Data In Hold Time tCHDX tDH 5 ns
/CS Active Hold Time relative to CLK tCHSH 5 ns
/CS Not Active Setup Time relative to CLK tSHCH 5 ns
/CS Deselect Time ( for Read instructions / Write,
tSHSL tCSH 10/50 ns
Erase and Program instructions)
Output Disable Time tSHQZ
Clock Low to Output Valid
2.7V-3.6V / 3.0V-3.6V
(2)
tDIS 7 ns
CLQV tV 7 / 6 ns
t
Output Hold Time tCLQX tHO 0 ns
/HOLD Active Setup Time relative to CLK tHLCH 5 ns
Continued – next page
- 50 -
11.8 AC Electrical Characteristics (cont’d)
W25Q80, W25Q16, W25Q32
DESCRIPTION SYMBOL ALT
UNIT
MIN TYP MAX
/HOLD Active Hold Time relative to CLK tCHHH 5 ns
/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns
/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns
SPEC
/HOLD to Output Low-Z tHHQX
/HOLD to Output High-Z tHLQZ
Write Protect Setup Time Before /CS Low t WHSL
Write Protect Hold Time After /CS High tSHWL
/CS High to Power-down Mode tDP
/CS High to Standby Mode without Electronic
(2)
tLZ 7 ns
(2)
tHZ 12 ns
(3)
20 ns
(3)
100 ns
(2)
3 µs
(2)
tRES1
3 µs
Signature Read
/CS High to Standby Mode with Electronic Signature
tRES2
(2)
1.8 µs
Read
/CS High to next Instruction after Suspend tSUS
(2)
20 µs
Write Status Register Time tW 10 15 ms
Byte Program Time (First Byte)
Additional Byte Program Time (After First Byte)
(5)
t
(5)
t
100 150 µs
BP1
6 12 µs
BP2
Page Program Time tPP 1.5 3 ms
Sector Erase Time (4KB) tSE 120 200 ms
Block Erase Time (32KB) tBE1 0.5 1 s
Block Erase Time (64KB) tBE2 0.75 1.5 s
Chip Erase Time W25Q80
Chip Erase Time W25Q16
Chip Erase Time W25Q32
Notes:
1. Clock high + Clock low must be less than or equal to 1/f
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4. Commercial temperature only applies to Fast Read (F
5. For multiple bytes after first byte within a page,
number of bytes programmed.
t
BPN
R0
= t
CE 12
t
25
50
C.
& FR1). Industrial temperature applies to all other parameters.
BP1 + tBP2 * N
(typical) and t
BPN
= t
BP1 + tBP2 * N
25
40
80
(max), where N =
s
s
s
Publication Release Date: June 20, 2007
- 51 - Advanced - Revision A5
11.9 Serial Output Timing
11.10 Input Timing
W25Q80, W25Q16, W25Q32
11.11 Hold Timing
- 52 -
12. PACKAGE SPECIFICATION
12.1 8-Pin SOIC 208-mil (Package Code SS)
W25Q80, W25Q16, W25Q32
SYMBOL
MILLIMETERS INCHES
MIN MAX MIN MAX
A 1.75 2.16 0.069 0.085
A1 0.05 0.25 0.002 0.010
A2 1.70 1.91 0.067 0.075
b 0.35 0.48 0.014 0.019
C 0.19 0.25 0.007 0.010
D
5.18 5.38 0.204 0.212
E 7.70 8.10 0.303 0.319
E1 5.18 5.38 0.204 0.212
e 1.27 BSC 0.050 BSC
L 0.50 0.80 0.020 0.031
θ
o
0
8
o
0
o
8
o
y --- 0.10 --- 0.004
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within .0004 inches at the seating plane.
Publication Release Date: June 20, 2007
- 53 - Advanced - Revision A5
12.2 8-Pin PDIP 300-mil (Package Code DA)
D
8
1
E
5
W25Q80, W25Q16, W25Q32
1
4
B
B
1
S
E
c
2
A
A
L
e
1
Symbol
A
A
A
B
B
c
D
E
E
e
L
α
e
S
Dimension in inch Dimension in mm
Nom
Min
0.010
1
0.130
0.125
2
0.016
0.018
1
1
1
A
0.060 1.52
0.010
0.008
0.360 0.380
0.3000.290
0.245
0.250
0.120
0.130
015
0.335 8.51
0.355
Base Plane
1
A
Seating Plane
Max Max
Min
0.175
0.25
0.135
3.18
0.41
0.022
0.0640.058
0.20
0.014
0.310
0.255
0.110
0.140
7.37
6.22
2.29 2.54 2.790.090 0.100
3.05
0.375
0.045
Nom
3.30
0.46
0.25
9.14
7.62
3.30
9.02
4.45
3.43
0.56
1.631.47
0.36
9.65
7.87
6.486.35
3.56
150
9.53
1.14
α
e
A
- 54 -
12.3 8-contact 6x5 WSON
W25Q80, W25Q16, W25Q32
Publication Release Date: June 20, 2007
- 55 - Advanced - Revision A5
12.4 8-contact 6x5 WSON Cont’d.
W25Q80, W25Q16, W25Q32
- 56 -
W25Q80, W25Q16, W25Q32
12.5 16-Pin SOIC 300-mil (Winbond Package Code SF)
SYMBOL
MILLIMETERS INCHES
MIN MAX MIN MAX
A 2.36 2.64 0.093 0.104
A1 0.10 0.30 0.004 0.012
b 0.33 0.51 0.013 0.020
C 0.18 0.28 0.007 0.011
(3)
D
10.08 10.49 0.397 0.413
E 10.01 10.64 0.394 0.419
(3)
E1
7.39 7.59 0.291 0.299
(2)
e
1.27 BSC 0.050 BSC
L 0.39 1.27 0.015 0.050
θ
o
0
8
o
0
o
8
o
y --- 0.076 --- 0.003
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
Publication Release Date: June 20, 2007
- 57 - Advanced - Revision A5
13. ORDERING INFORMATION
(1)
W25Q80, W25Q16, W25Q32
Notes:
1a. Only the 2nd letter is used for the part marking.
1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel
(shape T), when placing orders.
1c. The “W” prefix is not included on the part marking.
- 58 -
W25Q80, W25Q16, W25Q32
14. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A 10/20/06 New Create Advanced
Figures 2, 3A-B, 13A–14C, 16, 24, 25
A1 11/9/06 Various
A2 11/15/06 49
A3 2/22/07 20, 45, 49 & 57
A4 4/20/07 19, 28, 30 & 45
A5 6/20/07 13, 15-17 & 23
Table 10.2.2: Write Status Reg 1 and 2
Erase Suspend 10.2.21
tCHSH, tSHCH = 5nS
tSHSL = 10ns for Read & 50ns for Write,
Erase and Program instructions
Removed Burst Read Quad I/O Instruction.
Updated ordering Information.
Added transient voltage specification.
Added Mode Bit Reset instruction and
description.
Added note for SRP1,0 status during Power
Lock-Down protection.
Updated Status Register memory protection
tables.
Advanced Designation
The “Advanced” designation on a Winbond SpiFlash memory datasheet indicates the product
specification is subject to functional and electrical changes, and is not g
authorized sales representative should be consulted for the latest specification before designing with
this specification
uaranteed. Winbond or an
Preliminary Designation
The “Preliminary” designation on a Winbond SpiFlash memory datasheet indicates that the product is
not fully characterized. The specifications are subject to change and are not g
authorized sales representative should be consulted for current information before using this product.
uaranteed. Winbond or an
Trademarks
Winbond and spiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Publication Release Date: June 20, 2007
- 59 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 60 -
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