Rainbow Electronics W25Q32 User Manual
W25Q80, W25Q16, W25Q32
Advanced Information
8M-BIT, 16M-BIT AND 32M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: June 20, 2007
- 1 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
Table of Contents
1. GENERAL DESCRIPTION .........................................................................................................5
2. FEATURES................................................................................................................................. 5
3. PIN CONFIGURATION SOIC 208-MIL....................................................................................... 6
4. PIN CONFIGURATION WSON 6X5-MM....................................................................................6
5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM........................................................ 6
6. PIN CONFIGURATION SOIC 300-MIL....................................................................................... 7
7. PIN DESCRIPTION SOIC 300-MIL ............................................................................................ 7
7.1 Package Types............................................................................................................... 8
7.2 Chip Select (/CS)............................................................................................................ 8
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .............................. 8
7.4 Write Protect (/WP).........................................................................................................8
7.5 HOLD (/HOLD) ............................................................................................................... 8
7.6 Serial Clock (CLK)..........................................................................................................8
8. BLOCK DIAGRAM......................................................................................................................9
9. FUNCTIONAL DESCRIPTION ................................................................................................. 10
9.1 SPI OPERATIONS ....................................................................................................... 10
9.1.1 Standard SPI Instructions ...............................................................................................10
9.1.2 Dual SPI Instructions......................................................................................................10
9.1.3 Quad SPI Instructions.....................................................................................................10
9.1.4 Hold Function.................................................................................................................10
9.2 WRITE PROTECTION.................................................................................................. 11
9.2.1 Write Protect Features....................................................................................................11
10. CONTROL AND STATUS REGISTERS................................................................................... 12
10.1 STATUS REGISTER....................................................................................................12
10.1.1 BUSY............................................................................................................................12
10.1.2 Write Enable Latch (WEL)............................................................................................12
10.1.3 Block Protect Bits (BP2, BP1, BP0)..............................................................................12
10.1.4 Top/Bottom Block Protect (TB).....................................................................................12
10.1.5 Sector/Block Protect (SEC)..........................................................................................12
10.1.6 Status Register Protect (SRP1, SRP0)......................................................................... 13
10.1.7 Quad Enable (QE)........................................................................................................13
10.1.8 Status Register Memory Protection..............................................................................15
10.2 INSTRUCTIONS...........................................................................................................18
10.2.1 Manufacturer and Device Identification ........................................................................18
10.2.2 Instruction Set Table 1..................................................................................................19
10.2.3 Instruction Set Table 2 (Read Instructions) ..................................................................20
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W25Q80, W25Q16, W25Q32
10.2.4 Write Enable (06h)........................................................................................................21
10.2.5 Write Disable (04h).......................................................................................................21
10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h).................................22
10.2.7 Write Status Register (01h)..........................................................................................23
10.2.8 Read Data (03h)...........................................................................................................24
10.2.9 Fast Read (0Bh)...........................................................................................................25
10.2.10 Fast Read Dual Output (3Bh).....................................................................................26
10.2.11 Fast Read Quad Output (6Bh)....................................................................................27
10.2.12 Fast Read Dual I/O (BBh)...........................................................................................28
10.2.13 Fast Read Quad I/O (EBh).........................................................................................30
10.2.14 Page Program (02h)...................................................................................................32
10.2.15 Quad Input Page Program (32h) ................................................................................33
10.2.16 Sector Erase (20h) .....................................................................................................34
10.2.17 32KB Block Erase (52h).............................................................................................35
10.2.18 64KB Block Erase (D8h).............................................................................................36
10.2.19 Chip Erase (C7h / 60h)...............................................................................................37
10.2.20 Erase Suspend (75h)..................................................................................................38
10.2.21 Erase Resume (7Ah)..................................................................................................38
10.2.22 Power-down (B9h)......................................................................................................39
10.2.23 High Performance Mode (A3h)...................................................................................40
10.2.24 Release Power-down or High Performance Mode / Device ID (ABh).........................40
10.2.25 Read Manufacturer / Device ID (90h).........................................................................42
10.2.26 Read Unique ID Number ............................................................................................43
10.2.27 JEDEC ID (9Fh) .........................................................................................................44
10.2.28 Mode Bit Reset (FFh).................................................................................................45
11. ELECTRICAL CHARACTERISTICS (PRELIMINARY)............................................................. 46
11.1 Absolute Maximum Ratings.......................................................................................... 46
11.2 Operating Ranges......................................................................................................... 46
11.3 Endurance and Data Retention....................................................................................47
11.4 Power-up Timing and Write Inhibit Threshold ..............................................................47
11.5 DC Electrical Characteristics........................................................................................ 48
11.6 AC Measurement Conditions........................................................................................ 49
11.7 AC Electrical Characteristics ........................................................................................ 50
11.8 AC Electrical Characteristics (cont’d)...........................................................................51
11.9 Serial Output Timing..................................................................................................... 52
11.10 Input Timing................................................................................................................. 52
11.11 Hold Timing .................................................................................................................52
12. PACKAGE SPECIFICATION.................................................................................................... 53
12.1 8-Pin SOIC 208-mil (Package Code SS)...................................................................... 53
Publication Release Date: June 20, 2007
- 3 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
12.2 8-Pin PDIP 300-mil (Package Code DA)...................................................................... 54
12.3 8-contact 6x5 WSON.................................................................................................... 55
12.4 8-contact 6x5 WSON Cont’d. ....................................................................................... 56
12.5 16-Pin SOIC 300-mil (Winbond Package Code SF)..................................................... 57
13. ORDERING INFORMATION .................................................................................................... 58
14. REVISION HISTORY................................................................................................................ 59
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W25Q80, W25Q16, W25Q32
1. GENERAL DESCRIPTION
The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a
storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and
performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM,
executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices
operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and
1µA for power-down. All devices are offered in space-saving packages.
The W25Q80/16/32 array is organized into 4,096/8,192/16,384 programmable pages of 256-bytes
each. Up to 256 bytes can be programmed at a time using the Page Program instructions. Pages can
be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB
block erase) or the entire chip (chip erase). The W25Q80/16/32 has 256/512/1024 erasable sectors
and 16/32/64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q80/16/32 supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI using SPI pins: Serial Clock, Chip Select, Serial Data
I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 80MHz are
supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output
when using the Fast Read Dual/Quad Output instructions. These transfer rates are comparable to
those of 8 and 16-bit Parallel Flash memories.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification with a 64-bit Unique Serial Number.
2. FEATURES
• Family of SpiFlash Memories
– W25Q80: 8M-bit / 1M -byte (1,048,576)
– W25Q16: 16M-bit / 2M-byte (2,097,152)
– W25Q32: 32M-bit / 4M-byte (4,194,304)
– 256-bytes per programmable page
• Standard, Dual or Quad SPI
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO
– Quad SPI: CLK, /CS, IO
• Highest Performance Serial Flash
– Up to 6X that of ordinary Serial Flash
– 80MHz clock operation
– 160MHz equivalent Dual SPI
– 320MHz equivalent Quad SPI
– 40MB/S continuous data transfer rate
– 30MB/S random access (32-byte fetch)
– Comparable to X16 Parallel Flash
, IO1, /WP, /Hold
0
, IO1, IO2, IO3
0
• Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Block Erase (32K and 64K-bytes)
– Program one to 256 bytes
– Up to 100,000 erase/write cycles
– 20-year data retention
• Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, <1µA Power-down (typ.)
– -40°C to +85°C operating range
• Advanced Security Features
– Software and Hardware Write-Protect
– Top or Bottom, Sector or Block selection
– Lock-Down and OTP protection
– 64-Bit Unique ID for each device
• Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 6x5-mm (W25Q80 & W25Q16)
–16-pin SOIC 300-mil (W25Q16 & W25Q32)
Publication Release Date: June 20, 2007
- 5 - Advanced - Revision A5
3. PIN CONFIGURATION SOIC 208-MIL
Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS)
4. PAD CONFIGURATION WSON 6X5-MM
W25Q80, W25Q16, W25Q32
Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP)
5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM
PIN NO. PIN NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)*1
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)*1
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
8 VCC Power Supply
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0 – IO3 are used for Quad instructions
- 6 -
6. PIN CONFIGURATION SOIC 300-MIL
Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
W25Q80, W25Q16, W25Q32
7. PIN DESCRIPTION SOIC 300-MIL
PAD NO. PAD NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)*1
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)*1
16 CLK I Serial Clock Input
*1 IO0 and IO1 are used for Dual and Quad instructions
*2 IO0 – IO3 are used for Quad instructions
- 7 - Advanced - Revision A5
Publication Release Date: June 20, 2007
W25Q80, W25Q16, W25Q32
7.1 Package Types
W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON
(package code ZP). W25Q16 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and
6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a
16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and
dimensions are illustrated at the end of this datasheet.
7.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program
or status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up (see “Write Protection” and figure 30). If
needed a pull-up resister on /CS can be used to accomplish this.
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q80/16/32 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge CLK.
Dual and Quad SPI instruction use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be
set. When QE=1 the /WP pin becomes IO2 and /HOLD pin becomes IO3.
7.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (SEC. TB. BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP
pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin (Hardware Write
Protect) function is not available since this pin is used for IO2. See figure 1a, 1b, and 1c for the pin
configuration of Quad I/O operation.
7.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function
can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low.
When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since
this pin is used for IO3. See figure 1a, 1b, and 1c for the pin configuration of Quad I/O operation.
7.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Operations")
- 8 -
8. BLOCK DIAGRAM
W25Q80, W25Q16, W25Q32
Figure 2. W25Q80, W25Q16 and W25Q32 Block Diagram
Publication Release Date: June 20, 2007
- 9 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
9. FUNCTIONAL DESCRIPTION
9.1 SPI OPERATIONS
9.1.1 Standard SPI Instructions
The W25Q80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the
falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising
edges of /CS.
9.1.2 Dual SPI Instructions
The W25Q80/16/32 supports Dual SPI operation when using the "Fast Read Dual Output and Dual I/O"
(3B and BB hex) instructions. These instructions allow data to be transferred to or from the device at
two to three times the rate of ordinary Serial Flash devices. The Dual Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions the DI and DO pins become
bidirectional I/0 pins; IO0 and IO1.
9.1.3 Quad SPI Instructions
The W25Q80/16/32 supports Quad SPI operation when using the "Fast Read Quad Output and Fast
Read Quad I/O" (6B and EB hex respectively). These instructions allow data to be transferred to or from
the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a
significant improvement in continuous and random access transfer rates allowing fast code-shadowing
to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO
pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set..
9.1.4 Hold Function
The /HOLD signal allows the W25Q80/16/32 operation to be paused while it is actively selected (when
/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are
shared with other devices. For example, consider if the page buffer was only partially written when a
priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the
instruction and the data in the buffer so programming can resume where it left off once the bus is
available again. The /HOLD function is only available for standard SPI and Dual SPI operation, not
during Quad SPI.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on
the rising edge of the /HOLD signal if the CLK signal is already lo w. If the CLK is not already low the
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W25Q80, W25Q16, W25Q32
/HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial
Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored.
The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to
avoid resetting the internal logic state of the device.
9.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
W25Q80/16/32 provides several means to protect data from inadvertent writes.
9.2.1 Write Protect Features
• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automatic write disable after program and erase
• Software and Hardware (/WP pin) write protection using Status Register
• Write Protection using Power-down instruction
• Lock Down write protection until next power-up
• One Time Program (OTP) write protection
Upon power-up or at power-down the W25Q80/16/32 will maintain a reset condition while VCC is below
the threshold value of V
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds V
This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write
Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at
power-up until the VCC-min level and t
be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,
Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the
Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information. Additionally, the Power-down instruction offers an
extra level of write protection as all instructions are ignored except for the Release Power-down
instruction.
WI, all program and erase related instructions are further disabled for a time delay of tPUW.
WI, (See Power-up Timing and Voltage Levels and Figure 29). While reset, all
VSL time delay is reached. If needed a pull-up resister on /CS can
Publication Release Date: June 20, 2007
- 11 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
10. CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the
devices write protection features and Quad SPI setting. Write access to the Status Register is controlled by
the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and
in some cases the /WP pin.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this
time the device will ignore further instructions except for the Read Status Register and Erase Suspend
instruction (see t
register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is
ready for further instructions.
W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see t
be protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
W in AC characteristics). All, none or a portion of the memory array can
10.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
10.1.5 Sector/Block Protect (SEC)
The non-volatile Sector protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect 4KB
Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as
shown in the Status Register Memory Protection table. The default setting is SEC=0.
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W25Q80, W25Q16, W25Q32
10.1.6 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0 /WP
0 0 X
0 1 0
0 1 1
1 0 X
1 1 X
Note:
1. When SRP1, SRP0 = (1,0), a power-down, power-up cycle will change SRP1, SRP0 to (0,0) state.
Status
Register
Software
Protection
Hardware
Protected
Hardware
Unprotected
Power Supply
Lock-Down
One Time
Program
Description
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When /WP pin is low the Status Register locked and can not
be written to.
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.
Status Register is permanently protected and can not be
written to.
(1)
10.1.7 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad
operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When
the QE pin is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the
/WP or /HOLD pins are tied directly to the power supply or ground.
Publication Release Date: June 20, 2007
- 13 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
Figure 3a. Status Register-1
Figure 3b. Status Register-2
- 14 -
W25Q80, W25Q16, W25Q32
10.1.8 Status Register Memory Protection
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 63 3F0000h - 3FFFFFh 64KB Upper 1/64
0 0 0 1 0 62 and 63 3E0000h - 3FFFFFh 128KB Upper 1/32
0 0 0 1 1 60 thru 63 3C0000h - 3FFFFFh 256KB Upper 1/16
0 0 1 0 0 56 thru 63 380000h - 3FFFFFh 512KB Upper 1/8
0 0 1 0 1 48 thru 63 300000h - 3FFFFFh 1MB Upper 1/4
0 0 1 1 0 32 thru 63 200000h - 3FFFFFh 2MB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/64
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/32
(1)
W25Q32 (32M-BIT) MEMORY PROTECTION
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/16
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/8
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/4
0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2
X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4MB ALL
1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB Top Block
1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB Top Block
1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB Top Block
1 0 1 X X 63 3F8000h – 3FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
Publication Release Date: June 20, 2007
- 15 - Advanced - Revision A5
W25Q80, W25Q16, W25Q32
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 31 1F0000h - 1FFFFFh 64KB Upper 1/32
0 0 0 1 0 30 and 31 1E0000h - 1FFFFFh 128KB Upper 1/16
0 0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 256KB Upper 1/8
0 0 1 0 0 24 thru 31 180000h - 1FFFFFh 512KB Upper 1/4
0 0 1 0 1 16 thru 31 100000h - 1FFFFFh 1MB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/32
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/16
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/8
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/4
(1)
W25Q16 (16M-BIT) MEMORY PROTECTION
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/2
X X 1 1 X 0 thru 31 000000h – 1FFFFFh 2MB ALL
1 0 0 0 1 31 1FF000h – 1FFFFFh 4KB Top Block
1 0 0 1 0 31 1FE000h – 1FFFFFh 8KB Top Block
1 0 0 1 1 31 1FC000h – 1FFFFFh 16KB Top Block
1 0 1 X X 31 1F8000h – 1FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
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W25Q80, W25Q16, W25Q32
STATUS REGISTER
SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 15 0F0000h - 0FFFFFh 64KB Upper 1/16
0 0 0 1 0 14 and 15 0E0000h - 0FFFFFh 128KB Upper 1/8
0 0 0 1 1 12 thru 15 0C0000h - 0FFFFFh 256KB Upper 1/4
0 0 1 0 0 8 thru 15 080000h - 0FFFFFh 512KB Upper 1/2
0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/16
0 1 0 1 0 0 and 1 000000h - 01FFFFh 128KB Lower 1/8
0 1 0 1 1 0 thru 3 000000h - 03FFFFh 256KB Lower 1/4
0 1 1 0 0 0 thru 7 000000h - 07FFFFh 512KB Lower 1/2
(1)
W25Q80 (8M-BIT) MEMORY PROTECTION
X X 1 1 X 0 thru 15 000000h – 0FFFFFh 1MB ALL
1 0 0 0 1 15 0FF000h – 0FFFFFh 4KB Top Block
1 0 0 1 0 15 0FE000h – 0FFFFFh 8KB Top Block
1 0 0 1 1 15 0FC000h – 0FFFFFh 16KB Top Block
1 0 1 X X 15 0F8000h – 0FFFFFh 32KB Top Block
1 1 0 0 1 0 000000h – 000FFFh 4KB Bottom Block
1 1 0 1 0 0 000000h – 001FFFh 8KB Bottom Block
1 1 0 1 1 0 000000h – 003FFFh 16KB Bottom Block
1 1 1 X X 0 000000h – 007FFFh 32KB Bottom Block
Note:
1. x = don’t care
Publication Release Date: June 20, 2007
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W25Q80, W25Q16, W25Q32
10.2 INSTRUCTIONS
The instruction set of the W25Q80/16/32 consists of fifteen basic instructions that are fully controlled
through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip
Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the
DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 19. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full
8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the
device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when
the Status Register is being written, all instructions except for Read Status Register will be ignored until
the program or erase cycle has completed.
10.2.1 Manufacturer and Device Identification
MANUFACTURER ID (M7-M0)
Winbond Serial Flash
Device ID (ID7-ID0)
Instruction ABh, 90h
W25Q80 13h
W25Q16 14h
W25Q32 15h
EFh
(ID15-ID0)
9Fh
4014h
4015h
4016h
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