Rainbow Electronics W24L257 User Manual

Preliminary W24L257

R

32K × 8 CMOS STATIC RAM

GENERAL DESCRIPTION

The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 × 8 bits that
operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using
Winbond's high performance CMOS technology.

FEATURES

•

Low power consumption:

−

Active: 126 mW (max.)

•

Access time: 70 nS

•

Single 3.3V power supply

•

Fully static operation

•

All inputs and outputs directly TTL compatible

PIN CONFIGURATIONS BLOCK DIAGRAM

VCC

28-pin

TSOP

28

27

WE

26

A13

25

A8

A9

24

A11

23

OE

22

A10

21

20

CS

I/O 8

19

I/O 7

18

I/O 6

17

16

I/O 5

15

I/O 4

28

A10

27

CS

26

I/O8

25

I/O7

24

I/O6

23

I/O5

22

I/O4

21

V

SS

20

I/O3

19

I/O2

18

I/O1

17

A0

16

A1

15

A2

1

A14

2

A12

3

A7

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

11

I/O 1

12

I/O 2

13

I/O 3

V

SS

14

OE

A11

2

A9

3

A8

4

A13

5

WE

6

V

DD

7

A14

8

A12

9

A7

10

A6

11
12

A5

13

A4

14

A3

•

Three-state outputs

•

Battery back-up operation capability

•

Data retention voltage: 2V (min.)

•

Packaged in 450 mil SOP, standard type one
TSOP (8 mm × 20 mm) ,

CLK GEN. PRECHARGE CKT.

A12

A14

A2

A3

A4

A5

A6

A7

A13

I/O1

I/O8

WE

CS

OE

R
O

CORE CELL ARRAY

W

512 ROWS

D
E

32 X 8 COLUMNS

C
O
D
E

DATA

:

CNTRL

CLK
GEN.

I/O CKT.

COLUMN DECODER

A10

A11

A8A1A0

A9

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0−A14

I/O1−I/O8

CS

WE

OE

VDD Power Supply
VSS Ground

NC No Connection

Address Inputs
Data Inputs/Outputs
Chip Select Input

Write Enable Input

Output Enable Input

Publication Release Date: May 2000

- 1 - Revision A1

Preliminary W24L257

OE WE

TRUTH TABLE

V

CS

MODE

I/O1

−

I/O8

H X X Not Selected High Z ISB, I

L H H Output Disable High Z IDD

L L H Read Data Out IDD

L X L Write Data In IDD

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Supply Voltage to VSS Potential -0.5 to +4.6 V

Input/Output to V

Allowable Power Dissipation 1.0 W

Storage Temperature -65 to +150

Operating Temperature LL 0 to 70

LE -20 to 85

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

SS

Potential -0.5 to VDD +0.5 V

DD CURRENT

SB1

°

C

°

C

Operating Characteristics

(VDD = 3.0V to 3.6V; VSS = 0V; TA (°C) = 0 to 70 for LL, -20 to 85 for LE)

PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT

I

IL

IH

LI

LO

OL

OH

DD

- -0.5 +0.6 V

- +2.0 VDD +0.5 V

VIN = VSS to VDD -1 +1

VI/O = VSS to VDD,

CS

OE = V

WE

IH

(min.) or

= V

IH

(min.) or

= VIL (max.)

-1

IOL = +2.1 mA - 0.4 V

IOH = -1.0 mA 2.2 - V

CS

= VIL (max.) and

I/O = 0 mA,

-

Cycle = min. Duty = 100%

- 2 -

Input Low Voltage V

Input High Voltage V

Input Leakage Current I

Output Leakage Current I

Output Low Voltage V

Output High Voltage V

Operating Power Supply
Current

+1

35

µ

A

µ

A

mA

Preliminary W24L257

Operating Characteristics, continued

PARAMETER SYM. TEST CONDITIONS MIN. MAX. UNIT

Standby Power Supply
Current

I

Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 3.3V

CAPACITANCE

(VDD = 3.3V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN V

Input/Output Capacitance C

Note: These parameters are sampled but not 100% tested.

AC Characteristics

AC Test Conditions

Input Pulse Levels 0V to 3.0V

Input Rise and Fall Times 5 nS

Input and Output Timing Reference Level 1.5V

Output Load See the drawing below

PARAMETER CONDITIONS

SB

I

CS

= V

IH

(min.) or

Cycle = min. Duty = 100%

SB1

CS

≥ VDD -0.2V

I/O

V

IN

= 0V 6 pF

OUT

= 0V 8 pF

-

1

- 15 µ

mA

A

AC Test Loads and Waveform

OUTPUT

1 TTL

100 pF
Including
Jig and
Scope

3.0 V

0 V

5 nS

OUTPUT

(For T T T T T T )

CLZ, OLZ,

90%

10%

CHZ,

90%

10%

5 nS

1 TTL

5 pF
Including
Jig and
Scope

OHZ, WHZ, OW

Publication Release Date: May 2000

- 3 - Revision A1

Preliminary W24L257

AC Characteristics, continued

(V

DD = 3.0V to 3.6 V; VSS = 0V; TA (

Read Cycle

PARAMETER SYMBOL W24L257-70LL/LE UNIT

Read Cycle Time TRC 70 - nS

Address Access Time TAA - 70 nS

Chip Select Access Time T

Output Enable to Output Valid T

Chip Selection to Output in Low Z T

Output Enable to Output in Low Z T

Chip Deselection to Output in High Z T

Output Disable to Output in High Z T

Output Hold from Address Change TOH 10 - nS

These parameters are sampled but not 100% tested

∗

Write Cycle

C) = 0 to 70 for LL, -20 to 85 for LE)

°

MIN. MAX.

ACS

- 70 nS

AOE

- 35 nS

CLZ

* 10 - nS

OLZ

* 5 - nS

CHZ

* - 30 nS

OHZ

* - 30 nS

PARAMETER SYMBOL W24L257-70LL/LE UNIT

MIN. MAX.

Write Cycle Time TWC 70 - nS

Chip Selection to End of Write TCW 55 - nS

Address Valid to End of Write TAW 55 - nS

Address Setup Time TAS 0 - nS

Write Pulse Width TWP 40 - nS

WR

Write Recovery Time

CS

WE

,

T

0 - nS

Data Valid to End of Write TDW 35 - nS

Data Hold from End of Write TDH 0 - nS

Write to Output in High Z T

Output Disable to Output in High Z T

WHZ

* - 25 nS

OHZ

* - 25 nS

Output Active from End of Write TOW 5 - nS

These parameters are sampled but not 100% tested

∗

- 4 -

TIMING WAVEFORMS

Read Cycle 1

(Address Controlled)

Address

DOUT

Read Cycle 2

(Chip Select Controlled)

CS1

D

OUT

Preliminary W24L257

T

RC

AA

T

TOH

T

ACS

T

CLZ

T

OH

T

CHZ

Read Cycle 3

(Output Enable Controlled)

T

RC

Address

T

AA

OE

T

AOE

T

CS

D

OUT

OLZ

T

ACS

T

CLZ

- 5 - Revision A1

T

OH

T

OHZ

T

CHZ

Publication Release Date: May 2000

Timing Waveforms, continued

Write Cycle 1

Address

OE

CS

WE

D

OUT

D

IN

Preliminary W24L257

T

WC

T

WR

T

CW

T

AW

T

T

AS

T

OHZ

(1, 4)

WP

T

T

DW

DH

Write Cycle 2

(OE = VIL Fixed)

T

WC

Address

T

CW

CS

T

AW

WE

D

OUT

D

IN

T

AS

T

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from D

OUT

3. D

provides the read data for the next address.

OUT are the same as the data written to DIN during the write cycle.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

T

WR

WP

T

WHZ

(1, 4)

T

DW

T

OH

T

OW

T

DH

(2) (3)

- 6 -

Preliminary W24L257

DATA RETENTION CHARACTERISTICS

(TA (°C) = 0 to 70 for LL, -20 to 85 for LE)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT

VDD for Data Retention VDR

Data Retention Current I

Chip Deselect to Data

DDDR

CDR

T

CS

≥ VDD -0.2V

CS

≥ VDD -0.2V, VDD = 3V

See data retention waveform 0 - - nS

Retention Time

Operation Recovery Time TR TRC* - - nS

Read Cycle Time

*

DATA RETENTION WAVEFORM

V

DD

CS

0.9

T

V

CDR

DD

CS

V

>

2V

DR

=

>

V

-

DD

=

0.9

0.2V

2.0 - - V

- - 15

V

DD

T

R

µ

A

ORDERING INFORMATION

PART NO. ACCESS

TIME

(nS)

OPERATING

VOLTAGE

(V)

OPERATING

TEMPERATURE

(

°

C)

STANDBY

CURRENT

MAX.(

µ

A)

W24L257S70LL 70 3.0V to 3.6V 0 to 70 15 450 mil SOP

W24L257S70LE 70 3.0V to 3.6V 0 to 70 15 450 mil SOP

W24L257Q70LL 70 3.0V to 3.6V 0 to 70 15 Small TSOP

W24L257Q70LE 70 3.0V to 3.6V 0 to 70 15 Small TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

Publication Release Date: May 2000

- 7 - Revision A1

PACKAGE

Preliminary W24L257

BONDING PAD DIAGRAM

6

4

3

529

A7

A5

A6

A4

7

A3

8

A2

9A110 20

11 12

I/O0 I/O1

A0

30

1

2

A14

DD

V

15 16 17 18

14

V

SS

V

V

SS

A12

Y

13

I/O2

X

DD

27

28

A13

WEB

I/O4 I/O5

A8

AC5394

19

I/O6

242526

A11A9

23

OEB

22

A10

21

I/O7I/O3

CSB

Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.

PAD NO. X Y

1 -232.25 1445.22
2 -351.70 1445.22
3 -471.15 1445.22
4 -590.60 1445.22
5 -710.05 1445.22
6 -829.50 1445.22
7 -992.79 1362.24
8 -992.79 -1306.11

9 -857.86 -1452.79
10 -738.41 -1452.79
11 -594.84 -1414.13
12 -451.06 -1414.13
13 -310.67 -1414.13
14 -171.78 -1405.28
15 24.45 -1405.28
16 151.80 -1414.13
17 298.07 -1414.13
18 443.28 -1414.13
19 588.20 -1414.13
20 732.84 -1414.13
21 871.11 -1452.79
22 992.75 -1312.15
23 992.75 1373.67
24 810.09 1445.22
25 690.64 1445.22
26 571.19 1445.22
27 451.74 1445.22
28 332.29 1445.22
29 120.25 1444.65
30 -93.23 1444.65

- 8 -

PACKAGE DIMENSIONS

28-pin SOP Wide Body

Preliminary W24L257

28

S

Seating Plane

1

D

e

15

14

b

y

28-pin Standard Type One TSOP

H

D

D

1

e

b

θ

L

L

1

EH

A

2

1

A

Dimension in Inches

Symbol

1e

E

θ

L

Detail F

Notes:

1. Dimensions D Max. & S include mold flash

1

e

A

See Detail F

c

E

L

c

E

A

2

A

A

1

Y

or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

Dimension In Inches

Symbol

A
A

1

2

A
b
c
D
E

D

H
e
L
L

1

Y

θ

Controlling dimension: Millimeters

Nom.

Min.

A

0.004

1

A

0.098

0.093

2

A

0.014

0.016

b

0.0100.008

c

0.713

D
E

e

E

H

0.028

0.036

L

0.059

0.067

E

L
S
y

0 10

θ

Min.

Nom. Max. Min. Nom.

0.002

0.040

0.035

0.007 0.008 0.011

0.004

0.006

0.461 0.465 0.469

0.311 0.315 0.319

0.520 0.528 0.536

0.022

0.020

0.024 0.028

0.010

0.000

3

0

Dimension in mm

Max. Max.

Min.

0.112

0.10

0.103

2.36

0.36

0.020

0.014 0.36

0.733

8.28

0.3360.3310.326

1.12 1.27 1.420.044 0.050 0.056

0.4770.4650.453 12.1211.8111.51

0.044

0.71

0.075 1.50

0.047

0.004

0

.

Dimension In mm

0.047

0.05

0.006

0.041

0.17

0.10

0.008

11.70

7.90

13.20

0.50

0.004

0.00

5

0

Nom.

2.85

2.49

2.62

0.41

0.51

0.250.20

18.62

18.11

8.53

8.41

0.91 1.12

1.70

1.91

1.19

0.10

10

Max.

1.20

0.15

1.000.95

1.05

0.20 0.27

0.15 0.21

11.90

11.80

8.00 8.10

13.60

13.40

0.55

0.70

0.60

0.25

0.10

35

Publication Release Date: May 2000

- 9 - Revision A1

Preliminary W24L257

Winbond Electronics North America Corp.

Winbond Electronics North America Corp.

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 May 2000 - Initial Issued

Headquarters

Headquarters

No. 4, Creation Rd. III,

No. 4, Creation Rd. III,
Science-Based Industrial Park,

Science-Based Industrial Park,
Hsinchu, Taiwan

Hsinchu, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]
http://www.winbond.com.tw/

http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan

Taipei, Taiwan
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

Note: All data and specifications are subject to change withou t notice.

Note: All data and specifications are subject to change withou t notice.

Winbond Electronics (H.K.) Ltd.

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;

No. 378 Kwun Tong Rd;
Kowloon, Hong Kong

Kowloon, Hong Kong
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]

- 10 -

Winbond Memory Lab.

Winbond Memory Lab.
Winbond Microelectronics Corp.

Winbond Microelectronics Corp.
Winbond Systems Lab.

Winbond Systems Lab.

2727 N. First Street, San Jose,

2727 N. First Street, San Jose,
CA 95134, U.S.A.

CA 95134, U.S.A.
TEL: [phone]

TEL: [phone]
FAX: [phone]

FAX: [phone]