W2465
CS1
WE
OE
8K × 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W2465 is a slow-speed, low-power CMOS static RAM organized as 8192 × 8 bits that operates
on a single 5-volt power supply. This device is manufactured using Winbond's high performance
CMOS technology.
FEATURES
• Low power consumption:
− Active: 250 mW (max.)
− Standby: 100 µW (max.)(LL-version)
250 µW (max.)(L-version)
• Access time: 70/100 nS (max.)
• Single +5V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 2V (min.)
• Available packages: 28-pin 600 mil DIP,
330 mil SOP and 300 mil skinny DIP
PIN CONFIGURATION
1
2
A12
3
A7
4
A6
A5
5
A4
6
A3
7
A2
8
A1
9 20
A0
10
11
I/O1
12
I/O2
I/O3
13 16
V
SS
14 15
BLOCK DIAGRAM
V
DD
V
SS
V
WE
CS
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
DD
A0
A12
CS2
CS1
OE
WE
.
.
DECODER
CONTROL
CORE
ARRAY
DATA I/O
I/O1
I/O8
.
.
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A12
I/O1−I/O8
, CS2
VDD Power Supply
VSS Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
28NC
27
26
25
24
23
22
21
19
18
17
Publication Release Date: April 1997
- 1 - Revision A8
W2465
CS1
WE
CS1
CS1
CS1
≥
TRUTH TABLE
CS1 CS2 OE WE MODE
I/O1−I/O8
H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to +70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
VDD CURRENT
°C
°C
Operating Characteristics
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.2 - VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -2 - +2
Output Leakage
Current
Output Low Voltage VOL IOL = +4.0 mA - - 0.4 V
Output High Voltage VOH IOH = -1.0 mA 2.4 - - V
Operating Power
Supply Current
Standby Power Supply
Current
Note: Typical characteristics are at VDD = 5 V, TA = 25° C.
ILO VI/O = VSS to VDD
= VIH (min.) or CS2
= VIL (max.) or OE = VIH
IDD
(min.) or
= VIL (max.),
= VIL (max.)
CS2 = VIH (min.)
I/O = 0 mA,
Cycle = min.
Duty = 100%
ISB
= VIH (min.) or CS2
= VIL (max.), Cycle = min.
Duty = 100%
ISB1
VDD -0.2V
or CS2 ≤ 0.2V
-2 - +2
70 - - 70 mA
100 - - 60 mA
- - 3 mA
LL - - 20
L - - 50
µA
µA
µA
µA
- 2 -
W2465
CAPACITANCE
(VDD = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0.6V to 2.4V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 100 pF, IOH/IOL = -1 mA/4 mA
AC Test Loads and Waveform
R1 1000 ohm
5V
OUTPUT
100 pF
Including
Jig and
Scope
R2
660 ohm
2.4V
0.6V
5 nS
(For T
90% 90%
10%
10%
R1 1000 ohm
5V
OUTPUT
5 pF
Including
Jig and
Scope
CLZ1,
T T T T T T T
CLZ2,
5 nS
OLZ,
CHZ1,
CHZ2,
OHZ,
WHZ,
R2
660 ohm
)
OW
Publication Release Date: April 1997
- 3 - Revision A8
W2465
CS1
CS1
CS1
CS1
CS1,WE
AC Characteristics, continued
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
Read Cycle
PARAMETER SYM. W2465-70 W2465-10 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time TRC 70 - 100 - nS
Address Access Time TAA - 70 - 100 nS
Chip Select Access Time
CS2 TACS2 - 70 - 100 nS
Output Enable to Output Valid TAOE - 35 - 50 nS
Chip Selection to Output in Low Z
CS2 TCLZ2* 5 - 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - 5 - nS
Chip Deselection to Output in High Z
CS2 TCHZ2* - 30 - 35 nS
Output Disable to Output in High Z TOHZ* - 30 - 35 nS
Output Hold from Address Change TOH 10 - 10 - nS
* These parameters are sampled but not 100% tested.
TACS1 - 70 - 100 nS
TCLZ1* 5 - 10 - nS
TCHZ1* - 30 - 35 nS
Write Cycle
PARAMETER SYM. W2465-70 W2465-10 UNIT
MIN. MAX. MIN. MAX.
Write Cycle Time TWC 70 - 100 - nS
Chip Selection to End of Write
CS2 TCW2 60 - 80 - nS
Address Valid to End of Write TAW 60 - 80 - nS
Address Setup Time TAS 0 - 0 - nS
Write Pulse Width TWP 45 - 60 - nS
Write Recovery Time
TCW1 60 - 80 - nS
TWR1 0 - 0 - nS
CS2 TWR2 0 - 0 - nS
Data Valid to End of Write TDW 30 - 40 - nS
Data Hold from End of Write TDH 0 - 0 - nS
Write to Output in High Z TWHZ* - 30 - 30 nS
Output Disable to Output in High Z TOHZ* - 30 - 30 nS
Output Active from End of Write TOW 0 - 0 - nS
* These parameters are sampled but not 100% tested.
- 4 -
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
D
OUT
W2465
T
RC
T
AA
T
OH
T
ACS1
T
ACS2
T
CLZ1
T
CLZ2
T
OH
T
CHZ1
T
CHZ2
Read Cycle 3
(Output Enable Controlled)
Address
OE
CS1
CS2
D
OUT
T
T
RC
T
AA
T
CHZ2
T
CHZ1
T
OH
T
OHZ
CLZ1
T
CLZ2
T
T
T
ACS1
ACS2
OLZ
T
AOE
Publication Release Date: April 1997
- 5 - Revision A8
Timing Waveforms, continued
Write Cycle 1
Address
OE
CS1
W2465
T
WC
T
WR1
T
CW1
CS2
WE
D
OUT
D
IN
Write Cycle 2
(OE = VIL Fixed)
Address
CS1
CS2
WE
D
OUT
D
IN
T
CW2
T
AW
T
T
AS
T
OHZ
(1, 4)
T
AW
T
AS
WP
T
WC
T
CW1
T
CW2
T
WP
T
WHZ(1, 4)
T
WR2
T
DW
T
DW
T
T
WR1
WR2
T
DH
T
OH
T
OW
T
DH
(2)
(3)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
- 6 -
W2465
CS1
CS1
DATA RETENTION CHARACTERISTICS
(TA = 0 to 70° C)
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
VDD for Data Retention VDR
≥ VDD -0.2V, or
CS2 ≤ 0.2V
Data Retention Current IDDDR
≥ VDD -0.2V, or
LL - - 10
CS2 ≤ 0.2V
VDD = 3V L - - 20
Chip Deselect to Data
Retention Time
TCDR See data retention
waveforms
Operation Recovery Time TR TRC* - - nS
TRC* = Read Cycle Time
DATA RETENTION WAVEFORMS
DATA RETENTION MODE
V
DD
CS1
4.5V
T
CDR
IH
V
>
V
DR
2V
=
>
V
DD
=
4.5V
TR
0.2VCS1
-
2.0 - - V
0 - - nS
VIH
µA
µA
V
CS2
VIL
CS2<0.2V
=
IL
ORDERING INFORMATION
ACCESS TIME
PART NO.
(nS)
W2465-70LL 70 70 20 600 mil DIP
W2465-10L 100 60 50 600 mil DIP
W2465S-70LL 70 70 20 330 mil SOP
W2465S-10L 100 60 50 330 mil SOP
W2465K-70LL 70 70 20 300 mil Skinny
W2465K-10L 100 60 50 300 mil Skinny
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (µA)
PACKAGE
Publication Release Date: April 1997
- 7 - Revision A8
BONDING PAD DIAGRAM
W2465
PAD NO.
4
3
5
A4
6
A3
2
A7
A6A5
A12
27S-127S-2
1
CS2
V
DD
WE
V
DD
23242526
22
A8
A9
A11
21
OE
1 -226.95 1526.15
2 -350.95 1526.15
3 -484.10 1526.15
4 -608.10 1526.15
X
Y
5 -739.75 1526.15
6 -741.75 1315.10
7 -741.75 -1231.85
Y
8 -741.75 -1456.30
9 -610.60 -1456.30
10 -481.50 -1466.30
X
11 -343.80 -1466.30
12 -206.10 -1466.30
13S-1 -73.00 -1401.10
13S-2 -8.35 -1212.80
14 60.10 -1466.30
15 193.30 -1466.30
16 332.40 -1466.30
17 465.60 -1466.30
18
603.30 -1466.30
13S-1
12
V
O2
13S-2
V
SS
14 15 16 17
SS
03
O4
O5 O6
20
A10
18
19
O7
CS1
7
A2
9
10
A0 O0
11
O1
8
A1
19 738.15 -1456.30
20 740.15 -1221.45
21 740.15 1310.80
22 738.15 1526.15
23 606.50 1526.15
24 482.50 1526.15
25 349.35 1526.15
26 225.35 1526.15
27S-1 94.20 1526.15
27S-2 -50.40 1456.10
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
- 8 -
PACKAGE DIMENSIONS
28-pin P-DIP
28
E
1
1
S
A
2A
L
D
B
e
1
B
1
W2465
Dimension in Inches Dimension in mm
Symbol
Min. Nom. Max. Max.Nom.Min.
A
0.010
1
A
0.150
2
A
0.016
B
1
B
0.008
c
D
15
14
A
1
Base Plane
Seating Plane
E
e
a
A
c
E
0.540
1
E
0.090
1
e
0.120
L
a
A
e
S
Notes:
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
0.210
0.155
0.160
0.018
0.022
0.060 1.52
0.0640.058
0.010
0.014
1.460 1.470
0.610
0.6000.590
0.5500.545
0.110
0.100
0.140
0.130
0 15
0.670
0.6500.630 16.00 16.51
0.090
14.99
13.72 13.9713.84
5.33
0.25
3.81
3.94
4.06
0.41
0.46
0.56
2.29
0.25
37.08
15.24
2.54 2.79
3.30
1.631.47
0.36
37.34
15.49
3.56
17.02
2.29
150
0.20
3.05
28-pin P-DIP Skinny
28
1E
1 14
S
A
A
2
L
Dimension in Inches Dimension in mm
Symbol
A
A
A
D
15
B
B
c
D
E
E
e
L
a
e
S
Notes:
1. Dimension D Max. & S include mold flash or
E
Base Plane
A
1
B
B
e
1
1
Mounting Plane
e
A
a
c
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
Min.
0.010
1
0.125
2
0.016
1
0.008
1
1
0.120
°
0
A
Nom.
Max. Max.
Min.
0.175
0.135
0.022
0.0640.058
0.014
0.293
0.110
0.140
0.370
0.055
0.25
3.18
0.41
0.20
7.62
7.19
2.29 2.54 2.790.090 0.100
3.05
°
°
15
0
0.130
0.018
0.060 1.52
0.010
1.388 1.400
0.3100.300 0.320
0.2880.283
0.130
0.3500.330 8.38 8.89
Nom.
4.45
3.30
3.43
0.46
0.56
1.631.47
0.36
0.25
35.26 35.56
8.13
7.87
7.447.32
3.30
3.56
15
9.40
1.40
°
Publication Release Date: April 1997
- 9 - Revision A8
Package Dimensions, continued
28-pin SO Wide Body
W2465
28
1
S
Seating Plane
Dimension in Inches
Symbol
A
A
15
E H
E
14
b
D
A
A
2
e
y
A
1
L
e
1
See Detail F
e
Detail F
1
c
L
E
A
b
c
D
E
H
L
L
S
y
θ
Notes:
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and determined at the mold parting line.
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
Nom.
Min.
0.004
1
0.098
0.093
2
0.014
0.016
0.0100.008
0.713
e
E
0.028
0.036
0.059
0.067
E
0
Dimension in mm
Nom.
Max. Max.
Min.
0.10
2.36
2.49
0.36
0.41
0.250.20
18.62
18.11
8.28
8.41
1.12 1.27 1.420.044 0.050 0.056
0.71 0.91 1.12
1.70
0
2.85
2.62
0.51
1.91
0.112
0.103
0.020
0.014 0.36
0.733
0.3360.3310.326
0.4770.4650.453 12.1211.8111.51
0.044
0.075 1.50
0.047
0.004
10
.
8.53
1.19
0.10
10
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792647
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 10 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
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