Page 1
W24512A
2
3
5
6
789
V
DD
CS1
WE
OE
64K × 8 HIGH SPEED CMOS STATIC RAM
GENERAL DESCRIPTION
The W24512A is a high speed, low power CMOS static RAM organized as 65536 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
• High speed access time: 15/20/25/35 nS
(max.)
• Low power consumption:
− Active: 500 mW (typ.)
• Single +5V power supply
• Fully static operation
PIN CONFIGURATIONS
V
TSOP
32
DD
31
A15
30
CS2
29
WE
A13
28
A8
27
A9
26
A11
25
OE
24
A10
23
22
CS1
21
I/O8
20
I/O7
I/O6
19
I/O5
18
17
I/O4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CS2
1
NC
2
NC
A14
3
4
A12
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
V
SS
16
A11
A9
A8
A13
4
WE
A15
NC
NC
10
A14
11
A12
12
A7
13
A6
14
A5
15
16
A4
32-pin
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
V
I/O3
I/O2
I/O1
A0
A1
A2
A3
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Available packages: 32-pin 300 mil SOJ,
skinny DIP, 450 mil SOP, and standard type
one TSOP
BLOCK DIAGRAM
V
DD
V
SS
A0
.
A15
.
DECODER
CORE
C ORE
ARRAY
CS2
CS1
OE
WE
CONTROL
DATA I/O
I/O1
I/O8
.
.
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0−A15
I/O1−I/O8
, CS2
SS
VDD Power Supply
VSS Ground
NC No Connection
Address Inputs
Data Inputs/Outputs
Chip Select Inputs
Write Enable Input
Output Enable Input
Publication Release Date: March 1999
- 1 - Revision A7
Page 2
TRUTH TABLE
CS
1
OE
WE
CS1
OE
CS1
CS1
CS1
W24512A
CS2
H X X X Not Selected High Z ISB, ISB1
X L X X Not Selected High Z ISB, ISB1
L H H H Output Disable High Z IDD
L H L H Read Data Out IDD
L H X L Write Data In IDD
MODE
I/O1−I/O8
VDD CURRENT
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to +70
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
°C
°C
PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.2 - VDD +0.5 V
Input Leakage Current ILI VIN = VSS to VDD -10 - +10
Output Leakage
Current
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Power IDD
Supply Current I/O = 0mA, Cycle = min. 20 160
Standby Power
Supply Current
Note: Typical characteristics are at VDD = 5V, TA = 25° C.
ILO VI/O = VSS to VDD
= VIH or CS2 = VIL or
= VIH or WE = VIL
= VIL, CS2 = VIH
Duty = 100% 25 160
ISB
ISB1
= VIH or CS2 = VIL
Cycle = min., Duty = 100%
≥ VDD -0.2V or
CS2 ≤ 0.2V
- 2 -
-10 - +10
15 - - 200 mA
35 - - 140
- - 30 mA
- - 10 mA
µA
µA
Page 3
W24512A
CAPACITANCE
(VDD = 5V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 8 pF
Input/Output Capacitance CI/O VOUT = 0V 10 pF
Note: These parameters are sampled but not 100% tested.
THERMAL RESISTANCE
PARAMETER SYM. CONDITIONS MAX. UNIT
Junction to Case Thermal Resistance
Junction to Ambient Thermal
θJC
θJA
A. F. R. = 1m/sec, TA = 25° C
A. F. R. = 1m/sec, TA = 25° C
Resistance
Note: These parameters are only applied to "TSOP" and "SOJ" package types.
AC CHARACTERISTICS
AC Test Conditions
20
60
°C/W
°C/W
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA
AC Test Loads and Waveform
R1 480 ohm
5V
OUTPUT
R1 480 ohm
30 pF
Including
Jig and
Scope
R2
255 ohm
3.0V
0V
5 nS
(For T CLZ1,
90% 90%
10%
10%
OUTPUT
T
CLZ2,
5 nS
5V
5 pF
Including
Jig and
Scope
T T
T
OLZ, CHZ1, CHZ2, OHZ,
T
T T
WHZ,
R2
255 ohm
)
OW
Publication Release Date: March 1999
- 3 - Revision A7
Page 4
W24512A
AC Characteristics, continued
(VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C)
Read Cycle
PARAMETER SYM.
Read Cycle Time TRC 15 - 20 - 25 - 35 - nS
Address Access Time TAA - 15 - 20 - 25 - 35 nS
Chip Select Access Time
Output Enable to Output Valid TAOE - 7 - 10 - 12 - 17 nS
Chip Selection to Output in Low Z
Output Enable to Output in Low Z TOLZ* 0 - 0 - 0 - 0 - nS
Chip Deselection to Output in
High Z CS2 TCHZ2* - 7 - 10 - 12 - 17 nS
Output Disable to Output in High Z TOHZ* - 7 - 1 - 12 - 17 nS
Output Hold from Address Change TOH 3 - 3 - 3 - 3 - nS
TACS1 - 15 - 20 - 25 - 35 nS
CS1
CS2 TACS2 - 15 - 20 - 25 - 35 nS
TCLZ1* 3 - 3 - 3 - 3 - nS
CS1
CS2 TCLZ2* 3 - 3 - 3 - 3 - nS
TCHZ1* - 7 - 10 - 12 - 17 nS
CS1
W24512A-15 W24512A-25 W24512A-25 W24512A-35
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
* These parameters are sampled but not 100% tested.
Write Cycle
PARAMETER SYM.
Write Cycle Time TWC 15 - 20 - 25 - 35 - nS
Chip Selection to End of Write
Address Valid to End of Write TAW 13 - 17 - 18 - 20 - nS
Address Setup Time TAS 0 - 0 - 0 - 0 - nS
Write Pulse Width TWP 10 - 12 - 15 - 18 - nS
Write Recovery Time
Data Valid to End of Write TDW 9 - 10 - 12 - 15 - nS
Data Hold from End of Write TDH 0 - 0 - 0 - 0 - nS
Write to Output in High Z TWHZ* - 8 - 10 - 12 - 15 nS
Output Disable to Output in High Z TOHZ* - 8 - 10 - 12 - 15 nS
Output Active from End of Write TOW 0 - 0 - 0 - 0 - nS
CS1
CS2 TCW2 13 - 17 - 18 - 20 - nS
, WE
CS1
CS2 TWR2 0 - 0 - 0 - 0 - nS
TCW1 13 - 17 - 18 - 20 - nS
TWR1 0 - 0 - 0 - 0 - nS
* These parameters are sampled but not 100% tested.
W24512A-15 W24512A-25 W24512A-25 W24512A-35
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
- 4 -
Page 5
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS1
W24512A
T
RC
T
AA
T
OH
OH
T
CS2
D
OUT
Read Cycle 3
(Output Enable Controlled)
Address
OE
CS1
CS2
D
OUT
T
T
CLZ1
CLZ2
T
T
T
T
CLZ1
CLZ2
ACS1
ACS2
T
T
ACS1
ACS2
T
CHZ1
T
CHZ2
T
RC
T
AA
T
AOE
T
OLZ
T
CHZ2
T
CHZ1
T
OH
T
OHZ
Publication Release Date: March 1999
- 5 - Revision A7
Page 6
Timing Waveforms, continued
D
IN
Write Cycle 1
(OE Clock)
Address
OE
CS1
W24512A
T
WC
TWR1
T
CW1
CS2
WE
D
OUT
Write Cycle 2
(OE = VIL Fixed)
Address
CS1
CS2
WE
D
OUT
D
IN
T
CW2
T
AW
T
T
AS
T
OHZ
(1, 4)
T
AW
T
AS
WP
T
WC
CW1
T
T
CW2
WP
T
T
WHZ (1, 4)
WR2
T
T
T
DW
DH
T
WR1
T
WR2
T
OH
T
OW
T
T
DW
DH
(2) (3)
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
- 6 -
Page 7
ORDERING INFORMATION
W24512A
PART NO. ACCESS
TIME (nS)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
W24512AK-15 15 200 10 300 mil skinny DIP
W24512AK-20 20 160 10 300 mil skinny DIP
W24512AK-25 25 160 10 300 mil skinny DIP
W24512AK-35 35 140 10 300 mil skinny DIP
W24512AJ-15 15 200 10 300 mil SOJ
W24512AJ-20 20 160 10 300 mil SOJ
W24512AJ-25 25 160 10 300 mil SOJ
W24512AJ-35 35 140 10 300 mil SOJ
W24512AS-15 15 200 10 450 mil SOP
W24512AS-20 20 160 10 450 mil SOP
W24512AS-25 25 160 10 450 mil SOP
W24512AS-35 35 140 10 450 mil SOP
W24512AT-15 15 200 10
W24512AT-20 20 160 10
W24512AT-25 25 160 10
W24512AT-35 35 140 10
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
standard type one TSOP
standard type one TSOP
standard type one TSOP
standard type one TSOP
Publication Release Date: March 1999
- 7 - Revision A7
Page 8
PACKAGE DIMENSIONS
______________________
__
__
__
__
__
32-pin SOJ
W24512A
32
1
S
Seating Plane
32-pin SO Wide Body
32
1
S
Seating Plane
17
E
H
e
16
D
A
2
A
B
b
e
A
1
Symbol
Min. Nom.
A
A
1
A
2
B
b
c
D
E
e
e
1
H
e
L
S
Y
θ
L
θ
__ __
0.020
0.095 0.100 0.105
0.008
0.815
0.3000.295
0.080
__
0 10
e
1
Max.
0.140
__
0.0320.0280.026
0.0220.0180.016
0.0140.010
0.8350.825
0.305
0.0560.0500.044
0.2870.2670.247
0.3450.3350.325
0.045
0.004
Dimension in mmDimension in Inches
Min. Nom.
0.508
2.413
20.701
8.255
2.032
°
0
c
Max.
3.556
__
2.540 2.667
0.8130.7110.660
0.4570.406
0.559
0.2540.203
0.356
21.20920.955
7.7477.6207.493
1.4221.2701.118
7.2906.7826.274
8.7638.509
1.143
0.102
__
°
10
Y
Dimension in Inches
Symbol
17
E
E
H
e
1
L
16
b
D
2
A
A
e
y
1
A
See Detail F
Detail F
e
1
c
L
E
A
A
A
b
c
D
E
e
HE
L
L
S
y
θ
Notes:
1. Dimension D Max. & S include mold flash
or tie bar burrs.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Dimension D & E include mold mismatch
and are determined at the mold parting line.
4. Controlling dimension: Inches.
5. General appearance spec should be based
on final visual inspection spec.
1
2
E
Nom.
Min.
0.004
0.106
0.101
0.014
0.016
0.0080.006
0.805
0.5560.546 14.3814.1213.87
0.023
0.031
0.047
0.055
0
Dimension in mm
Nom.
Max. Max.
Min.
0.118
0.10
0.111
2.57
2.69
0.36
0.004
10
0.41
0.200.15
20.45
11.18
11.30
1.12 1.27 1.420.044 0.050
0.58 0.79 0.99
1.40
0
0.020
0.012 0.31
0.817
0.4500.4450.440
0.056
0.556
0.039
0.063 1.19
0.036
.
11.43
20.75
3.00
2.82
0.51
1.60
0.91
0.10
10
- 8 -
Page 9
Package Dimensions, continued
6. General appearance spec. should be based on
32-pin TSOP
M
e
0.10(0.004)
b
θ
L
L1
W24512A
H
D
D
c
E
A
A
2
1
A
Y
Dimension in Inches
Symbol
Min. Nom. Max.
__
__
A
0.002
A
1
2
0.037
A
b
0.007 0.008
c
0.005 0.006
0.720 0.724
D
0.311 0.315
E
0.780 0.787
H
D
__
e
0.016 0.020
L
__
1
L
0.000 0.004
Y
1
θ
__
0.039
0.020
0.031
3 5
0.047
0.006
0.041
0.009
0.007
0.728
0.319
0.795
__
0.024
__
Note:
Controlling dimension: Millimeter
Dimension in mm
Min.
Nom.
__
__
__
0.05
0.95
0.17
0.20 0.23
0.12
0.15 0.17
18.30
18.40 18.50
7.90
8.00 8.10
19.80
20.00 20.20
__
0.50
0.40
0.50 0.60
__
0.80
____
0.00
1
3 5
Max.
1.20
0.15
1.051.00
__
__
0.10
32-pin P-DIP Skinny (300 mil)
32
1
E
1
S
A
A
2
L
D
e
B
1
B
0.200
0.155
0.022
0.0640.058
0.014
0.335
0.294
0.110
0.140
0.470
0.065
15
Dimension in mm
0.38
3.68
3.81
0.41
0.46
0.20
0.25
7.49
8.00
7.26
7.36
2.29 2.54 2.790.090 0.100
3.05
3.30
°
0
11.43
5.08
3.94
0.56
1.631.47
0.36
3.56
11.94
1.65
8.50
7.46
°
15
Dimension in Inches
Symbol
Min. Nom. Max. Max.Nom.Min.
A
0.015
A
1
0.150
0.145
A
2
0.016
B
17
16
E
Base Plane
1
A
1
Mounting Plane
e
a
c
A
B
c
D
E
E 1
e
L
a
e
S
Notes:
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
0.018
0.060 1.52
1
0.010
0.008
1.60 1.62 40.64 41.15
0.295
0.315
0.286
0.290
1
0.120
0.130
0
0.430 10.92
0.450
A
final visual inspection spec.
Publication Release Date: March 1999
- 9 - Revision A7
Page 10
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A7 Mar. 1999 - Arrange acceee time for 15/20/25/35 nS
W24512A
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792647
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 10 -
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
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