Rainbow Electronics W24256 User Manual

Preliminary W24256

R

32K × 8 CMOS STATIC RAM

GENERAL DESCRIPTION

The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.

FEATURES

•

Low power consumption:

•

Access time: 70 nS (max.)

•

Active :300 mW

Standby :250 µW

•

Single 5V power supply

•

Fully static operation

•

All inputs and outputs directly TTL compatible

•

Three-state outputs

•

Battery back-up operation capability

•

Data retention voltage: 2V (min.)

•

Packaged in 28-pin 600 mil DIP, 330 mil SOP
and standard type one TSOP (8 mm × 13.4
mm)

PIN CONFIGURATIONS

1

A14
A12

2

A7

3

A6

4

A5

5

A4

6

28-pin

7

DIP

8

9

10

11

12

13

14

1
2
3
4
5
6

28-pin

7

TSOP

8
9
10
11
12
13
14

WE
V
A14
A12

A11

A13

A3

A2

A1

A0

I/O1

I/O2

I/O3
V

SS

OE

A9
A8

DD

A7
A6
A5
A4
A3

BLOCK DIAGRAM

CLK GEN.

A12

A14

A2

WE
CS
OE

A3

A4

A5

A6

A7

A13

I/O1

I/O8

28

V

DD

27

WE

26

A13

25

A8

24

A9

23

A11

22

OE

21

A10

20

CS

I/O8

19

I/O7

18

I/O6

17

I/O5

16

I/O4

15

R
O

W

D
E
C
O
D
E

DATA
CNTRL.

CLK
GEN.

PRECHARGE CKT.

CORE CELL ARRAY

512 ROWS

64 X 8 COLUMNS

I/O CKT.

COLUMN DECODER

A10 A1 A0A8A9

A11

PIN DESCRIPTION

A10

28
27

CS

26

I/O8

25

I/O7

24

I/O6

23

I/O5

22

I/O4

21

SS

V

20

I/O3

19

I/O2

18

I/O1

17

A0
A1

16

A2

15

SYMBOL DESCRIPTION

A0−A14

I/O1−I/O8

CS

WE

OE

Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input

VDD Power Supply
VSS Ground

Publication Release Date: October 1999

- 1 - Revision A1

Preliminary W24256

CS OE WE

TRUTH TABLE

V

MODE

I/O1

−

I/O8

H X X Not Selected High Z ISB, ISB1

L H H Output Disable High Z IDD
L L H Read Data Out IDD
L X L Write Data In IDD

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER RATING UNIT

Supply Voltage to VSS Potential -0.5 to +7.0 V
Input/Output to V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150
Operating Temperature 0 to 70

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.

SS

Potential -0.5 to VDD +0.5 V

DD CURRENT

°

C

°C

Operating Characteristics

DD = 5V

(V

Input Low Voltage V
Input High Voltage V
Input Leakage Current I
Output Leakage Current I

Output Low Voltage V
Output High Voltage V
Operating Power
Supply Current
Standby Power Supply

Current

Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V.

10%; VSS = 0V; TA = 0° C to 70° C)

±

PARAMETER SYM.

I
LL - - 50

TEST CONDITIONS MIN. TYP.* MAX. UNIT

IL

IH

LI

VIN = VSS to VDD -5 - +5

LO

VI/O = VSS to VDD,
(min.) or

WE

= V

OL IOL

OH IOH

DD

I

= +2.1 mA - - 0.4 V

= -1.0 mA 2.4 - - V

CS

= VIL (max.), I/O = 0 mA ,

- -0.5 - +0.8 V

- +2.2 - VDD +1 V

-5 - +5

IH

OE

= VIH (min.) or

IL

(max.)

CS

= V

- - 60 mA

Cycle = min , Duty = 100 %

I

SB

CS

IH

(min.), Cycle = min.

= V

- - 3 mA

Duty = 100%

SB1

CS ≥

V

DD

-0.2V

L - - 100

µ

A

µ

A

µ

A

µ

A

- 2 -

CAPACITANCE

(VDD = 5V, TA = 25° C, f = 1 MHz)

PARAMETER SYM. CONDITIONS MAX. UNIT

Input Capacitance CIN V
Input/Output Capacitance C

Note: These parameters are sampled but not 100% tested.

I/O

V

IN

= 0V 6 pF

OUT

= 0V 8 pF

Preliminary W24256

AC CHARACTERISTICS

AC Test Conditions

PARAMETER CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below

AC TEST LOADS AND WAVEFORM

1 TTL

OUTPUT

100 pF
Including
Jig and
Scope

3.0V

0V

5 nS

OUTPUT

(For T T T T T T )

CLZ, OLZ,

90%
10%

90%

10%

CHZ,

5 nS

OHZ, WHZ, OW

1 TTL

5 pF
Including
Jig and
Scope

Publication Release Date: October 1999

- 3 - Revision A1

Preliminary W24256

AC Characteristics, continued

DD = 5V

(V

Read Cycle

Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time T
Output Enable to Output Valid T
Chip Selection to Output in Low Z T
Output Enable to Output in Low Z T
Chip Deselection to Output in High Z T
Output Disable to Output in High Z T
Output Hold from Address Change TOH 3 - nS

These parameters are sampled but not 100% tested

∗

10%; VSS = 0V; TA = 0° C to 70° C)

±

PARAMETER SYM. W24256-70L/LL UNIT

MIN. MAX.

ACS

- 70 nS

AOE

- 30 nS

CLZ

* 5 - nS

OLZ

* 5 - nS

CHZ

* - 20 nS

OHZ

* - 20 nS

Write Cycle

PARAMETER SYM. W24256-70L/LL UNIT

MIN. MAX.

Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 70 - nS
Address Valid to End of Write TAW 70 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 50 - nS
Write Recovery Time

CS, WE
Data Valid to End of Write TDW 30 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z T
Output Disable to Output in High Z T
Output Active from End of Write TOW 5 - nS

These parameters are sampled but not 100% tested

∗

WR

0 - nS

T

WHZ

* - 25 nS

OHZ

* - 30 nS

- 4 -

TIMING WAVEFORMS

Read Cycle 1

(Address Controlled)

Address

OUT

D

Read Cycle 2

(Chip Select Controlled)

CS

D

OUT

TCLZ

Preliminary W24256

RC

T

AA

T

OH

T

TACS

TOH

T

CHZ

Read Cycle 3

(Output Enable Controlled)

RC

T

Address

T

AA

OE

AOE

T

CS

D

OUT

TOLZ

ACS

T

CLZ

T

Publication Release Date: October 1999

- 5 - Revision A1

T

OH

T

OHZ

CHZ

T

Timing Waveforms, continued

OE

Write Cycle 1

Address

OE

CS

WE

D

OUT

D

IN

Write Cycle 2

= VIL Fixed)

(

Preliminary W24256

T

WC

T

WR

T

CW

T

AW

T

T

AS

T

OHZ

(1, 4)

WP

T

T

DW

DH

T

WC

Address

(1, 4)

T

DW

T

WR

T

OH

T

OW

T

DH

(2) (3)

T

CW

CS

T

AW

WE

D

OUT

D

IN

T

AS

T

WP

T

WHZ

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from D

OUT are the same as the data written to DIN during the write cycle.

3. DOUT provides the read data for the next address.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

- 6 -

Preliminary W24256

DATA RETENTION CHARACTERISTICS

(TA = 0° C to 70° C)

PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT

VDD for Data Retention VDR

Data Retention Current I

Chip Deselect to Data

DDDR

CDR

T

DD

CS ≥

CS ≥

-0.2V

V

DD

-0.2V, VDD = 3V

V

See data retention waveform 0 - - nS

Retention Time
Operation Recovery Time TR TRC* - - nS

Read Cycle Time

*

DATA RETENTION WAVEFORM

DD

V

CS

0.9 DD

V

T

CDR

IH

V

>

VDR2V

=

>

DD

VCS

=

- 0.2V

0.9

T

2.0 - 5.5 V

- - 20

DDV

R

IH

V

µ

A

ORDERING INFORMATION

PART NO. ACCESS

TIME

(nS)

W24256-70L 70 60 100 600 mil DIP
W24256-70LL 70 60 50 600 mil DIP
W24256S-70L 70 60 100 330 mil SOP
W24256S-70LL 70 60 50 330 mil SOP
W24256Q-70L 70 60 100 Standard type one TSOP
W24256Q-70LL 70 60 50 Standard type one TSOP

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.

- 7 - Revision A1

OPERATING

CURRENT MAX.

(

mA)

STANDBY

CURRENT MAX.

(

A)

µ

Publication Release Date: October 1999

PACKAGE

PACKAGE DIMENSIONS

28-pin P-DIP

Preliminary W24256

28

E

1

1

S

A

2A

L

D

B

B

1

28-pin SOP Wide Body

28

1

D

S

Seating Plane

e

Dimension in Inches

Symbol

Min. Nom. Max. Max.Nom.Min.

A

0.010

A

1

0.150

0.155

A

2

0.016

0.018

B

0.060 1.52

B1

0.008

0.010

c

1.460 1.470 37.08 37.34

D

0.6000.590

15

14

A

1

Base Plane

E

c

Seating Plane

e

1

15

E

EH

14

b

A

A

2

1

A

y

a

θ

L

1

e

See Detail F

e

A

Detail F

1e

c

E

L

E

0.540

E

1

0.090

0.100

e

1

0.120

0.130

L

015

a

0.630

0.650

A

e
S

Notes:

1. Dimensions D Max. & S include mold flash or
tie bar burrs.

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.

4. Dimension B1 does not include dambar
protrusion/intrusion.

5. Controlling dimension: Inches.

6. General appearance spec. should be based on
final visual inspection spec.

Dimension in Inches

Symbol

Notes:

1. Dimensions D Max. & S include mold flash
or tie bar burrs.

2. Dimension b does not include dambar
protrusion/intrusion.

3. Dimensions D & E include mold mismatch
and determined at the mold parting line.

4. Controlling dimension: Inches.

5. General appearance spec should be based
on final visual inspection spec.

A
A
A
b
c
D
E

e
H

L
L
S
y

θ

1

2

E

E

Nom.

Min.

0.004

0.098

0.093

0.014

0.016

0.0100.008

0.713

0.028

0.036

0.059

0.067

0 10

Dimension in mm

0.210 5.33

0.25

0.160

3.81

3.94

0.41

0.46

0.022

0.0640.058

0.20

0.014

0.25

15.24

0.610

14.99

13.72 13.9713.84

0.5500.545

2.29

0.110

2.54 2.79

3.05

0.140

3.30

16.00 16.51

0.670

0.090

.

Dimension in mm

Nom.

Max. Max.

Min.

0.112

0.10

0.103

2.36

2.49

0.36

0.41

0.020

0.250.20

0.014 0.36

0.733

18.11

8.28

8.41

0.3360.3310.326

1.12 1.27 1.420.044 0.050 0.056

0.4770.4650.453 12.1211.8111.51

0.044

0.91 1.12

0.71

0.075 1.50

1.70

0.047

0.004

0

.

15.49

2.85

2.62

0.51

18.62

8.53

1.91

4.06

0.56

1.631.47

0.36

3.56

17.02

2.29

1.19

0.10

10

150

- 8 -

Package Dimensions, continued

28-pin Standard Type One TSOP

H

D

D

1

e

b

θ

L

L

1

Preliminary W24256

Dimension In Inches

Symbol

Min.

Nom. Max. Min. Nom.

c

E

A

2

A

A

1

Y

A

0.002

1

A

A

b
c
D

E
H
e

L

L
Y

θ

0.035

2

0.007 0.008 0.011

0.004

0.461 0.465 0.469

0.311 0.315 0.319

0.520 0.528 0.536

D

0.020

1

0.000

0

0.040

0.006

0.022

0.024 0.028

0.010

Controlling dimension: Millimeters

3

0.047

0.006

0.041

0.008

0.004

5

Dimension In mm

0.05

1.000.95

0.17

0.20 0.27

0.10

0.15 0.21

11.70

11.80

8.00 8.10

7.90

13.40

13.20

0.55

0.50

0.60

0.25

0.00

35

0

Max.

1.20

0.15

1.05

11.90

13.60

0.70

0.10

Publication Release Date: October 1999

- 9 - Revision A1

Preliminary W24256

VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A1 Oct. 1999 - Initial issued

Headquarters

No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: [phone]
FAX: [phone]
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: [phone]
FAX: [phone]

Note: All data and specifications are subject to change without notice.

Winbond Electronics (H.K.) Ltd.

Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: [phone]
FAX: [phone]

Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.

2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: [phone]

FAX: [phone]

- 10 -