Features
• Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of
50 mA Each
• Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of
50 mA Each
• ON Resistance High Side R
• ON Resistance Low Side R
< 10 Ω Versus Total Temperature Range
on
< 7 Ω Versus Total Temperature Range
on
• Short-circuit Detection of Each Driver Stage
• Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection
• Independent Control of Each Driver Stage via an 8-bit Shift Register
• Status Output Reports Short-circuit Condition
• Status Output Reports when All Loads Are Switched Off
• Timing of Status Output Reset Signalizes Failure Mode
• Temperature Protection in Conjunction with Short-circuit Detection
Description
The U6820BM is a driver interface in BCDMOS technology with 8 independent driver
stages having a maximum current capability of 50 mA each. Its partitioning into 4
high-side and 4 low-side driver stages allows an easy connection of either 4 halfbridges or 2 H-bridges on the pc board. The U6820BM communicates with a microcontroller via an 8-bit serial interface. Integrated protection against short circuit and
overtemperature give added value. EMI protection and 2-kV ESD protection together
with automotive qualification referring to conducted interference (ISO/TR 7637/1)
make this IC ideal for both automotive and industrial applications.
Dual Quad
BCDMOS
Driver IC
U6820BM
Figure 1. Block Diagram
V
CC
6
V
CC
14
STATUS
HH
HH
L
S2S
S
1
4
Input Register
4
GND
CC
CLK
11
CS
12
13
DI
3SS4
HS4 HS3 HS2 HS1
16
Current
limiter
L
L
L
S
S
S
3
2
1
V
CC
Current
limiter
Current
limiter
Control
logic
Current
limiter
9
1015
8 1
Current
limiter
Thermal protection
Power-on reset
Current
limiter
Current
limiter
Current
limiter
3
V
S
V
CC
V
CC
5
GND
S
27
LS1LS2LS3LS4
Rev. 4527A–BCD–03/02
1
Pin Configuration
Figure 2. Pinning SO16
HS1
LS1
VS
GNDCC
GNDS
VCC
LS2
HS2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HS4
LS4
STATUS
DI
CLK
CS
LS3
HS3
Pin Description
Pin Symbol Function
1 HS1 Output high side 1
2 LS1 Output low side 1
3 VS Supply voltage 6 V to 18 V
4 GNDCC Digital ground
5 GNDS Power ground
6 VCC Supply voltage 5 V (external)
7 LS2 Output low side 2
8 HS2 Output high side 2
9 HS3 Output high side 3
10 LS3 Output low side 3
11 CS Set supply status (chip select)
12 CLK Clock line for 8-bit control shift register
13 DI Data line for 8-bit control shift register
14 STATUS Status output (H = fault, diagnostic “H” if all driver stages are switched off)
15 LS4 Output low side 4
16 HS4 Output high side 4
2
U6820BM
4527A–BCD–03/02
U6820BM
Description of the
Control Interface to
the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit command register (CR) and a 4-bit counter.
The data input takes place with commands at Pins DI (data input), CS (chip select) and
CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR.
The first information written into the SR is the least significant bit (LSB). The Pin STATUS is used for diagnostic purposes and reports any fault condition to the
microcontroller.
The input CS in accordance with the CR controls the serial interface. A high level at CS
disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows
only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffective. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is
transferred into the CR. If the number of clock cycles during the low phase of CS was
less or more than eight transitions, no transfer will take place. A new command switches
the output stages on or off immediately.
Each output stage is controlled by one specific bit of the CR. Low level means “supply
off” or inactive, and high level means “supply on” or active. If all 8 bits are at a low level,
the output stages will be set into standby mode.
If one of the output stages detects a short circuit and additionally overtemperature condition, the corresponding control bit in the CR is set to low. This reset has priority over
an external command to CR, thus, this does not affect the 1
tects the IC against overtemperature by activating the temperature shut down
immediately.
st
control bit. The priority pro-
The STATUS Output The STATUS output is at low level during normal operation. If one or more output stages
detect short circuit or if overtemperature is indicated, the STATUS output changes to
high level (OR-connection).
For diagnostic purposes (self test of the status output), the status output can also be
brought into high level during standby mode.
Timing of the Status
Output Reset Signalizes
the Failure Mode
Power-on Reset After switching on the supply voltage, all data latches are reset and the outputs are
The use of different reset conditions at the STATUS output simplifies the failure analysis
during normal operation, and is also beneficial during testing.
The storage content can be used for STATUS output. It is indicated and latched immediately with the rising edge of CS at STATUS output if less than 8 clocks were received
during the low phase of CS. The reset is initiated by the falling edge of the 8
(bit 7) of the next data input.
Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the
rising edge of the 9
(bit 1) of the next data input.
The detection of overtemperature is latched internally. It is reset by the falling edge of
th
clock (bit 3) of a data transfer if overtemperature is no longer present.
the 4
switched off. The typical power-on reset threshold is V
vated after the first data transfer.
th
clock. The reset is initiated by the falling edge of the 2nd clock
= 3.7 V. The outputs are acti-
CC
th
clock
4527A–BCD–03/02
3
Short-circuit Protection The current of the output stages is limited by an active feedback control. Short circuit at
one output stage sets the diagnostic Pin 14 (STATUS) to high. In case of both conditions, short circuit at one of the outputs and temperature detection, the affected output is
switched off selectively. It will be activated again after the first new data transfer.
Inductance Protection Clamping diodes and FETs are integrated to protect the IC against too high or too low
voltages at the outputs. They prevent the IC from latch up and parasitic currents which
may exceed power dissipation.
Temperature Protection The IC is protected by an overtemperature detection. As soon as the junction tempera-
= 155°C typically is exceeded, the diagnostic Pin 14 (STATUS) is set “high”.
ture T
j
General overtemperature detection along with short-circuit condition at a specific output
result in temperature shut down at that specific output. After temperature shut down, the
data input register has to be set again with a hysteresis of typically
=140°C).
(T
j
∆T = 15 K
ESD Protection All output stages are protected against electrostatic discharge up to 5 kV (HBM) with
external components (see Figure 5), all other pins are protected up to 2 kV (HBM).
Table 1. Timing of the STATUS Output
Shift Register
0000000000000000 All out = OK off off off off off off off off H New CS
1111111111111111 All on = OK on on on on on on on on L
0000000100000001 E.g. one on = OK off off off off off off off on L
0111111101111111 Short at LS3 off on on on on on on on H No short
1111111111101111 Temp & short at HS4 on on on off on on on on H New CS4
1100001100000000 V
11100011xxxxxxxx CS with less 8 CLK x x x x x x x x H New CS 8
00011100xxxxxxxx CS with more 8 CLK x x x x x x x x H New CS 2
Command
Register
Condition
< 3.7 V = P-ON off off off off off off off off H P-ON, CS
VCC
Low-side Switch High-side Switch Status
LS1 LS2 LS3 LS4 HS1 HS2 HS3 HS4 Set Reset
4
U6820BM
4527A–BCD–03/02