Rainbow Electronics U3742BM User Manual

Features

• IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal

Strength Indicator) Output

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self-polling with a Programmable Time

Frame Check

• Supply Voltage 4.5 V to 5.5 V

• Operating Temperature Range -40°C to 105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD. 883 (4 KV HBM)

• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW

Front-end Filter (Up to 40 dB Achievable with Newer SAWs)

• Communication to Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

Description

The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been especially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manches­ter or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF
transmitter IC U2741B. Its main applications in the area of wireless control are teleme­tering, security technology, tire-pressure monitoring and keyless-entry systems. It can
be used in the frequency receiving range of f
data transmission. All the statements made in this data sheet refer both to

433.92 MHz and 315 MHz applications.

= 300 MHz to 450 MHz for ASK or FSK

0

UHF ASK/FSK
Receiver

U3742BM

Rev. 4735A–RKE–11/03

Figure 1. System Block Diagram

1 Li cell

Encoder

ATARx9x

Keys

Figure 2. Block Diagram

FSK/ASK

CDEM

RSSI

SENS

AVCC

AGND

DGND

UHF ASK/FSK

Remote control transmitter

U2741B

PLL

XTO

VCO

Power

amp.

FSK/ASK-

Demodulator

and data filter

IF Amp

4. Order

Antenna Antenna

Dem_out

Limiter outRSSI

Sensitivity
reduction

UHF ASK/FSK

Remote control receiver

U3742BM

Demod.

IF Amp

LNA VCO

50 kΩ

Polling circuit

and

control logic

FE CLK

Control

PLL XTO

V

S

DATA

ENABLE

TEST

MODE

DVCC

1...3

Micro-

controller

LPF

MIXVCC

LNAGND

LNA_IN

2

U3742BM

LNA

3 MHz

IF Amp

LPF

3 MHz

Standby logic

VCO XTO

f

64

LFGND

LFVCC

XTO

LF

4735A–RKE–11/03

Pin Configuration

Figure 3. Pinning SO20

SENS

FSK/ASK

U3742BM

20

19

DATA

ENABLE

1

2

CDEM

AVCC

AGND

DGND

MIXVCC

LNAGND

LNA_IN

NC

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor

2 FSK/ASK

3 CDEM Lower cut-off frequency of the data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer

9LNA_INRF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply

Selecting FSK/ASK
Low: FSK, High: ASK

3

4

5

6

7

8

9

10

18

17

16

15

14

13

12

11

TEST

RSSI

MODE

DVCC

XTO

LFGND

LF

LFVCC

4735A–RKE–11/03

3

Pin Description (Continued)

Pin Symbol Function

Selecting 433.92 MHz/315 MHz

16 MODE

Low: 4.90625 MHz (USA)

High: 6.76438 (Europe)
17 RSSI Output of the RSSI amplifier
18 TEST Test pin, during operation at GND

Enables the polling mode
19 ENABLE

Low: polling mode off (sleep mode)

High: polling mode on (active mode)
20 DATA Data output/configuration input

RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input

signal into a 1 MHz IF signal. According to Figure 2 on page 2, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at pin LF. f

by the phase frequency detector. The current output of the phase frequency

to f

XTO

is divided by a factor of 64. The divided frequency is compared

LO

LO

detector is connected to a passive loop filter and thereby generates the control voltage

for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is

V

LF

equal to f
f

= fLO/64

XTO

. If fLO is determined, f

XTO

can be calculated using the following formula:

XTO

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys­tal. According to Figure 4, the crystal should be connected to GND via the capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f

. When designing the system in terms of receiving bandwidth, the accuracy

LO

of the crystal and the XTO must be considered.

. The VCO (voltage-controlled

XTO

for the mixer. fLO is dependent on

and

XTO

Figure 4. PLL Peripherals

V

S

DVCC

C

L

XTO

LFGND

LF

R

V

LFVCC

4

U3742BM

S

1

C

9

C

10

R1 = 820 Ω

C

= 4.7 nF

9

= 1 nF

C

10

4735A–RKE–11/03

U3742BM

The passive loop filter connected to pin LF is designed for a loop bandwidth of

= 100 kHz. This value for B

B

Loop

LO. Figure 4 on page 4 shows the appropriate loop filter components to achieve the
desired loop bandwidth. If the filter components are changed for any reason, please
note that the maximum capacitive load at pin LF is limited. If the capacitive load is
exceeded, a bit check may no longer be possible since f
the bit check starts to evaluate the incoming data stream. Self-polling does therefore
also not work in that case.

fLO is determined by the RF input frequency fRF and the IF frequency fIF using the follow­ing formula:

= fRF - f

f

LO

IF

To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is f

= 1 MHz. To achieve a good accuracy of the filter's corner fre-

IF

quencies, the filter is tuned by the crystal frequency f
fixed relation between f

and fLO, that depends on the logic level at pin MODE. This is

IF

described by the following formulas:

f

LO

MODE 0 (USA) f

MODE 1 (Europe) f

IF

IF

----------==
314

f

LO

------------ ------==

432.92

exhibits the best possible noise performance of the

Loop

cannot settle in time before

LO

. This means that there is a

XTO

The relation is designed to achieve the nominal IF frequency of f
applications. For applications where f
case of f
equal to 1 MHz. f

= 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not

RF

is then dependent on the logical level at pin MODE and on fRF. Table

IF

= 315 MHz, MODE must be set to '0'. In the

RF

= 1 MHz for most

IF

1 on page 6 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF

input pin LNA_IN. The input impedance of that pin is provided in the electrical parame­ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver U3742BM exhibits its highest sensitivity at the best signal-to­noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans­formation network.

A good practice when designing the network is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of

DP

= 40 dB can be achieved. There are SAWs available that exhibit a notch at

Ref

Df = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The

selectivity of the receiver is also improved by using a SAW. In typical automotive appli­cations, a SAW is used.

Figure 5 on page 6 shows a typical input matching network for f

= 433.92 MHz using a SAW. Figure 6 on page 6 illustrates input matching to 50 W

f

RF

= 315 MHz and

RF

without a SAW. The input matching networks shown in Figure 6 on page 6 are the refer­ence networks for the parameters given in the electrical characteristics.

4735A–RKE–11/03

5

Table 1. Calculation of LO and IF Frequency

Conditions

fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

f

RF

300 MHz < f

< 365 MHz, MODE = 0

RF

365 MHz < fRF < 450 MHz, MODE = 1

Figure 5. Input Matching Network with SAW Filter

Local Oscillator
Frequency Intermediate Frequency

f

LO

f

LO

1

------------ ----------------=
1

1

----------+
314

f

RF

1

------------------+

432.92

RF

------------ --------=

f

f

LO

f

----------=

IF

314

f

f

IF

LO

------------ ------=

432.92

8

LNAGND

U3742BM

IN
IN_GND

9

LNA_IN

C

16

100p

27n

B3555

CASE_GND

3, 4 7, 8

L

3

OUT_GND

C

17

8.2p

TOKO LL2012

F27NJ

OUT

C

3

22p

fRF = 433.92 MHz

L

C

8.2p

2

TOKO LL2012

F33NJ

33n

RF

IN

L

25n

2

1
2

Figure 6. Input Matching Network without SAW Filter

fRF = 433.92 MHz

15p

25n

8

LNAGND

U3742BM

9

LNA_IN

RF

5

6

fRF = 315 MHz

C

3

47p

fRF = 315 MHz

IN

C

2

10p

33p

L

2

TOKO LL2012

F82NJ

82n

L

25n

25n

1

2

IN
IN_GND

8

LNAGND

U3742BM

9

LNA_IN

C

16

100p

L

47n

B3551

CASE_GND

3, 4 7, 8

8

LNAGND

U3742BM

9

LNA_IN

3

TOKO LL2012

OUT_GND

C

17

22p

F47NJ

OUT

5
6

RF

IN

3.3p

6

U3742BM

22n

100p

TOKO LL2012

F22NJ

RF

IN

3.3p

39n

100p

TOKO LL2012

F39NJ

4735A–RKE–11/03

U3742BM

Please note that for all coupling conditions (see Figure 5 on page 6 and Figure 6 on
page 6), the bond wire inductivity of the LNA ground is compensated. C
resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a
DC path. Its value is not critical but must be large enough not to detune the series reso­nance circuit. For cost reduction, this inductor can be easily printed on the PCB. This
configuration improves the sensitivity of the receiver by about 1 dB to 2 dB.

Analog Signal
Processing

IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f

= 433.92 MHz is used. For other RF input frequencies, refer to Table 1 on page 6 to

f

RF

determine the center frequency.

= 1 MHz for applications where fRF = 315 MHz or

IF

forms a series

3

The receiver U3742BM - M3 employs an IF bandwidth of B

= 600 kHz and can be used

IF

together with the U2741B in FSK and ASK mode.

RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage

V

Th_red

. V

is determined by the value of the external resistor R

Th_red

nected between pin SENS and GND or V
digital control logic. By this means it is possible to operate the receiver at a lower
sensitivity.

Pin RSSI The output voltage of the RSSI amplifier (V

output signal, the signal strength of different transmitters can be distinguished. The
usable input-power range P
of V

is typically -2.2 mV/K. Due to TC and gain tolerance, it is not possible to find out

RSSI

the absolute level of each transmitter, but the level differences can be used to distin­guish several transmitters. As illustrated in Figure 8 on page 8, the RSSI output voltage
is not constant over the temperature range. Figure 7 on page 8 illustrates an application
that realizes a temperature compensation of V

is -100 dBm to -55 dBm. The temperature coefficient TC

Ref

. The output of the comparator is fed into the

S

) is available at pin RSSI. Using the RSSI

RSSI

.

RSSI

= 60 dB. If the

RSSI

. R

Sense

Sense

is con-

4735A–RKE–11/03

7

Figure 7. Temperature Compensation of V

I ~ Ig(V

LNA_IN

)

RSSI

V

180k

RSSI_temp_comp.

50k

U3742BM

Figure 8. RSSI Characteristic

1.6

1.5

1.4

1.3

1.2

(V)

1.1

RSSI

1.0

V

-40°C

0.9

0.8

0.7

0.6

0.5

25°C

105°C

-110 -100 -90 -80 -70 -60 -50

RSSI

B

= 60

min

I

max

P

V

Ref

RSSI

(dBm)

47 k

min

If R
sensitivity is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced

Sense

, the maximum sensitivity by the signal-to-

Sense

noise ratio of the LNA input. The reduced sensitivity is dependent on the signal strength
at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 6 on page 6 and exhibits the best possi­ble sensitivity.

can be connected to VS or GND via a microcontroller. The receiver can be

R

Sense

switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling
mode, the receiver will not wake up if the RF input signal does not exceed the selected
sensitivity. If the receiver is already active, the data stream at pin DATA will disappear
when the input signal is lower than defined by the reduced sensitivity. Instead of the
data stream, the pattern according to Figure 9 on page 9 is issued at pin DATA to indi­cate that the receiver is still active.

8

U3742BM

4735A–RKE–11/03

Figure 9. Steady L State Limited DATA Output Pattern

U3742BM

DATA

FSK/ASK Demodulator
and Data Filter

tmin2

t

DATA_L_max

The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.
Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.

In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detec­tion reference voltage to a value where a good signal-to-noise ratio is achieved. This
circuit also implies the effective suppression of any kind of inband noise signals or com­peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected
properly.

The FSK demodulator is intended to be used for an FSK deviation of

Df ³ 20 kHz. Lower

values may be used but the sensitivity of the receiver is reduced in that condition. The
minimum usable deviation is dependent on the selected baud rate. In FSK mode, only
BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be
detected if the S/N Ratio exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its pass band
can be adopted to the characteristics of the data signal. The data filter consists of a
1st-order high-pass and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to
pin CDEM. The cut-off frequency of the high-pass filter is defined by the following
formula:

f

cu_DF

------------- ----------------- ----------------- ------------=
2

1

p´ 30 kW´ CDEM´

4735A–RKE–11/03

In self-polling mode, the data filter must settle very rapidly to achieve a low current con­sumption. Therefore, CDEM cannot be increased to very high values if self-polling is
used. On the other hand, CDEM must be large enough to meet the data filter require­ments according to the data signal. Recommended values for CDEM are given in
“Electrical Characteristics” on page 25. The values are slightly different for ASK and
FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu­ration of the Receiver” on page 19). BR_Range must be set in accordance to the used
baud rate.

The U3742BM is designed to operate with data coding where the DC level of the data
signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of V
and V

= 66%. The sensitivity may be reduced by up to 1.5 dB in that condition.

DC_max

DC_min

= 33%

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(tee_sig). These limits are defined in the electrical characteristics. They should not be
exceeded to maintain full sensitivity of the receiver.

9

Receiving
Characteristics

The RF receiver U3742BM can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front-end filter is illustrated in Figure 10. This exam­ple relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror
frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitiv­ity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.

When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal­culated to be the sum of the deviation of the crystal and the XTO deviation of the
U3742BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of
the U3742BM is an additional deviation due to the XTO circuit. This deviation is speci­fied to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in
that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.

Figure 10. Receiving Frequency Response

0

-10

-20

-30

-40

-50

dP (dB)

-60

-70

-80

-90

-100

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6

df (MHz)

without SAW

with SAW

Polling Circuit and
Control Logic

10

U3742BM

The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro­controller. This flexibility enables the user meets the specifications in terms of current
consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the con­nected microcontroller, or it can be operated by up to three uni-directional ports.

4735A–RKE–11/03