Rainbow Electronics U3742BM User Manual

Features

• IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal

Strength Indicator) Output

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self-polling with a Programmable Time

Frame Check

• Supply Voltage 4.5 V to 5.5 V

• Operating Temperature Range -40°C to 105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD. 883 (4 KV HBM)

• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW

Front-end Filter (Up to 40 dB Achievable with Newer SAWs)

• Communication to Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

Description

The U3742BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been especially developed for the demands of RF low-cost data transmission systems
with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manches­ter or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF
transmitter IC U2741B. Its main applications in the area of wireless control are teleme­tering, security technology, tire-pressure monitoring and keyless-entry systems. It can
be used in the frequency receiving range of f
data transmission. All the statements made in this data sheet refer both to

433.92 MHz and 315 MHz applications.

= 300 MHz to 450 MHz for ASK or FSK

0

UHF ASK/FSK
Receiver

U3742BM

Rev. 4735A–RKE–11/03

Figure 1. System Block Diagram

1 Li cell

Encoder

ATARx9x

Keys

Figure 2. Block Diagram

FSK/ASK

CDEM

RSSI

SENS

AVCC

AGND

DGND

UHF ASK/FSK

Remote control transmitter

U2741B

PLL

XTO

VCO

Power

amp.

FSK/ASK-

Demodulator

and data filter

IF Amp

4. Order

Antenna Antenna

Dem_out

Limiter outRSSI

Sensitivity
reduction

UHF ASK/FSK

Remote control receiver

U3742BM

Demod.

IF Amp

LNA VCO

50 kΩ

Polling circuit

and

control logic

FE CLK

Control

PLL XTO

V

S

DATA

ENABLE

TEST

MODE

DVCC

1...3

Micro-

controller

LPF

MIXVCC

LNAGND

LNA_IN

2

U3742BM

LNA

3 MHz

IF Amp

LPF

3 MHz

Standby logic

VCO XTO

f

64

LFGND

LFVCC

XTO

LF

4735A–RKE–11/03

Pin Configuration

Figure 3. Pinning SO20

SENS

FSK/ASK

U3742BM

20

19

DATA

ENABLE

1

2

CDEM

AVCC

AGND

DGND

MIXVCC

LNAGND

LNA_IN

NC

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor

2 FSK/ASK

3 CDEM Lower cut-off frequency of the data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer

9LNA_INRF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply

Selecting FSK/ASK
Low: FSK, High: ASK

3

4

5

6

7

8

9

10

18

17

16

15

14

13

12

11

TEST

RSSI

MODE

DVCC

XTO

LFGND

LF

LFVCC

4735A–RKE–11/03

3

Pin Description (Continued)

Pin Symbol Function

Selecting 433.92 MHz/315 MHz

16 MODE

Low: 4.90625 MHz (USA)

High: 6.76438 (Europe)
17 RSSI Output of the RSSI amplifier
18 TEST Test pin, during operation at GND

Enables the polling mode
19 ENABLE

Low: polling mode off (sleep mode)

High: polling mode on (active mode)
20 DATA Data output/configuration input

RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input

signal into a 1 MHz IF signal. According to Figure 2 on page 2, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at pin LF. f

by the phase frequency detector. The current output of the phase frequency

to f

XTO

is divided by a factor of 64. The divided frequency is compared

LO

LO

detector is connected to a passive loop filter and thereby generates the control voltage

for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is

V

LF

equal to f
f

= fLO/64

XTO

. If fLO is determined, f

XTO

can be calculated using the following formula:

XTO

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys­tal. According to Figure 4, the crystal should be connected to GND via the capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f

. When designing the system in terms of receiving bandwidth, the accuracy

LO

of the crystal and the XTO must be considered.

. The VCO (voltage-controlled

XTO

for the mixer. fLO is dependent on

and

XTO

Figure 4. PLL Peripherals

V

S

DVCC

C

L

XTO

LFGND

LF

R

V

LFVCC

4

U3742BM

S

1

C

9

C

10

R1 = 820 Ω

C

= 4.7 nF

9

= 1 nF

C

10

4735A–RKE–11/03

U3742BM

The passive loop filter connected to pin LF is designed for a loop bandwidth of

= 100 kHz. This value for B

B

Loop

LO. Figure 4 on page 4 shows the appropriate loop filter components to achieve the
desired loop bandwidth. If the filter components are changed for any reason, please
note that the maximum capacitive load at pin LF is limited. If the capacitive load is
exceeded, a bit check may no longer be possible since f
the bit check starts to evaluate the incoming data stream. Self-polling does therefore
also not work in that case.

fLO is determined by the RF input frequency fRF and the IF frequency fIF using the follow­ing formula:

= fRF - f

f

LO

IF

To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is f

= 1 MHz. To achieve a good accuracy of the filter's corner fre-

IF

quencies, the filter is tuned by the crystal frequency f
fixed relation between f

and fLO, that depends on the logic level at pin MODE. This is

IF

described by the following formulas:

f

LO

MODE 0 (USA) f

MODE 1 (Europe) f

IF

IF

----------==
314

f

LO

------------ ------==

432.92

exhibits the best possible noise performance of the

Loop

cannot settle in time before

LO

. This means that there is a

XTO

The relation is designed to achieve the nominal IF frequency of f
applications. For applications where f
case of f
equal to 1 MHz. f

= 433.92 MHz, MODE must be set to '1'. For other RF frequencies, fIF is not

RF

is then dependent on the logical level at pin MODE and on fRF. Table

IF

= 315 MHz, MODE must be set to '0'. In the

RF

= 1 MHz for most

IF

1 on page 6 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF

input pin LNA_IN. The input impedance of that pin is provided in the electrical parame­ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver U3742BM exhibits its highest sensitivity at the best signal-to­noise ratio in the LNA. Hence, noise matching is the best choice for designing the trans­formation network.

A good practice when designing the network is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of

DP

= 40 dB can be achieved. There are SAWs available that exhibit a notch at

Ref

Df = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The

selectivity of the receiver is also improved by using a SAW. In typical automotive appli­cations, a SAW is used.

Figure 5 on page 6 shows a typical input matching network for f

= 433.92 MHz using a SAW. Figure 6 on page 6 illustrates input matching to 50 W

f

RF

= 315 MHz and

RF

without a SAW. The input matching networks shown in Figure 6 on page 6 are the refer­ence networks for the parameters given in the electrical characteristics.

4735A–RKE–11/03

5

Table 1. Calculation of LO and IF Frequency

Conditions

fRF = 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

f

RF

300 MHz < f

< 365 MHz, MODE = 0

RF

365 MHz < fRF < 450 MHz, MODE = 1

Figure 5. Input Matching Network with SAW Filter

Local Oscillator
Frequency Intermediate Frequency

f

LO

f

LO

1

------------ ----------------=
1

1

----------+
314

f

RF

1

------------------+

432.92

RF

------------ --------=

f

f

LO

f

----------=

IF

314

f

f

IF

LO

------------ ------=

432.92

8

LNAGND

U3742BM

IN
IN_GND

9

LNA_IN

C

16

100p

27n

B3555

CASE_GND

3, 4 7, 8

L

3

OUT_GND

C

17

8.2p

TOKO LL2012

F27NJ

OUT

C

3

22p

fRF = 433.92 MHz

L

C

8.2p

2

TOKO LL2012

F33NJ

33n

RF

IN

L

25n

2

1
2

Figure 6. Input Matching Network without SAW Filter

fRF = 433.92 MHz

15p

25n

8

LNAGND

U3742BM

9

LNA_IN

RF

5

6

fRF = 315 MHz

C

3

47p

fRF = 315 MHz

IN

C

2

10p

33p

L

2

TOKO LL2012

F82NJ

82n

L

25n

25n

1

2

IN
IN_GND

8

LNAGND

U3742BM

9

LNA_IN

C

16

100p

L

47n

B3551

CASE_GND

3, 4 7, 8

8

LNAGND

U3742BM

9

LNA_IN

3

TOKO LL2012

OUT_GND

C

17

22p

F47NJ

OUT

5
6

RF

IN

3.3p

6

U3742BM

22n

100p

TOKO LL2012

F22NJ

RF

IN

3.3p

39n

100p

TOKO LL2012

F39NJ

4735A–RKE–11/03

U3742BM

Please note that for all coupling conditions (see Figure 5 on page 6 and Figure 6 on
page 6), the bond wire inductivity of the LNA ground is compensated. C
resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a
DC path. Its value is not critical but must be large enough not to detune the series reso­nance circuit. For cost reduction, this inductor can be easily printed on the PCB. This
configuration improves the sensitivity of the receiver by about 1 dB to 2 dB.

Analog Signal
Processing

IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f

= 433.92 MHz is used. For other RF input frequencies, refer to Table 1 on page 6 to

f

RF

determine the center frequency.

= 1 MHz for applications where fRF = 315 MHz or

IF

forms a series

3

The receiver U3742BM - M3 employs an IF bandwidth of B

= 600 kHz and can be used

IF

together with the U2741B in FSK and ASK mode.

RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage

V

Th_red

. V

is determined by the value of the external resistor R

Th_red

nected between pin SENS and GND or V
digital control logic. By this means it is possible to operate the receiver at a lower
sensitivity.

Pin RSSI The output voltage of the RSSI amplifier (V

output signal, the signal strength of different transmitters can be distinguished. The
usable input-power range P
of V

is typically -2.2 mV/K. Due to TC and gain tolerance, it is not possible to find out

RSSI

the absolute level of each transmitter, but the level differences can be used to distin­guish several transmitters. As illustrated in Figure 8 on page 8, the RSSI output voltage
is not constant over the temperature range. Figure 7 on page 8 illustrates an application
that realizes a temperature compensation of V

is -100 dBm to -55 dBm. The temperature coefficient TC

Ref

. The output of the comparator is fed into the

S

) is available at pin RSSI. Using the RSSI

RSSI

.

RSSI

= 60 dB. If the

RSSI

. R

Sense

Sense

is con-

4735A–RKE–11/03

7

Figure 7. Temperature Compensation of V

I ~ Ig(V

LNA_IN

)

RSSI

V

180k

RSSI_temp_comp.

50k

U3742BM

Figure 8. RSSI Characteristic

1.6

1.5

1.4

1.3

1.2

(V)

1.1

RSSI

1.0

V

-40°C

0.9

0.8

0.7

0.6

0.5

25°C

105°C

-110 -100 -90 -80 -70 -60 -50

RSSI

B

= 60

min

I

max

P

V

Ref

RSSI

(dBm)

47 k

min

If R
sensitivity is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced

Sense

, the maximum sensitivity by the signal-to-

Sense

noise ratio of the LNA input. The reduced sensitivity is dependent on the signal strength
at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 6 on page 6 and exhibits the best possi­ble sensitivity.

can be connected to VS or GND via a microcontroller. The receiver can be

R

Sense

switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling
mode, the receiver will not wake up if the RF input signal does not exceed the selected
sensitivity. If the receiver is already active, the data stream at pin DATA will disappear
when the input signal is lower than defined by the reduced sensitivity. Instead of the
data stream, the pattern according to Figure 9 on page 9 is issued at pin DATA to indi­cate that the receiver is still active.

8

U3742BM

4735A–RKE–11/03

Figure 9. Steady L State Limited DATA Output Pattern

U3742BM

DATA

FSK/ASK Demodulator
and Data Filter

tmin2

t

DATA_L_max

The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.
Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.

In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detec­tion reference voltage to a value where a good signal-to-noise ratio is achieved. This
circuit also implies the effective suppression of any kind of inband noise signals or com­peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected
properly.

The FSK demodulator is intended to be used for an FSK deviation of

Df ³ 20 kHz. Lower

values may be used but the sensitivity of the receiver is reduced in that condition. The
minimum usable deviation is dependent on the selected baud rate. In FSK mode, only
BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be
detected if the S/N Ratio exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its pass band
can be adopted to the characteristics of the data signal. The data filter consists of a
1st-order high-pass and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to
pin CDEM. The cut-off frequency of the high-pass filter is defined by the following
formula:

f

cu_DF

------------- ----------------- ----------------- ------------=
2

1

p´ 30 kW´ CDEM´

4735A–RKE–11/03

In self-polling mode, the data filter must settle very rapidly to achieve a low current con­sumption. Therefore, CDEM cannot be increased to very high values if self-polling is
used. On the other hand, CDEM must be large enough to meet the data filter require­ments according to the data signal. Recommended values for CDEM are given in
“Electrical Characteristics” on page 25. The values are slightly different for ASK and
FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu­ration of the Receiver” on page 19). BR_Range must be set in accordance to the used
baud rate.

The U3742BM is designed to operate with data coding where the DC level of the data
signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of V
and V

= 66%. The sensitivity may be reduced by up to 1.5 dB in that condition.

DC_max

DC_min

= 33%

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(tee_sig). These limits are defined in the electrical characteristics. They should not be
exceeded to maintain full sensitivity of the receiver.

9

Receiving
Characteristics

The RF receiver U3742BM can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front-end filter is illustrated in Figure 10. This exam­ple relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror
frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitiv­ity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.

When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal­culated to be the sum of the deviation of the crystal and the XTO deviation of the
U3742BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of
the U3742BM is an additional deviation due to the XTO circuit. This deviation is speci­fied to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in
that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.

Figure 10. Receiving Frequency Response

0

-10

-20

-30

-40

-50

dP (dB)

-60

-70

-80

-90

-100

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6

df (MHz)

without SAW

with SAW

Polling Circuit and
Control Logic

10

U3742BM

The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro­controller. This flexibility enables the user meets the specifications in terms of current
consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the con­nected microcontroller, or it can be operated by up to three uni-directional ports.

4735A–RKE–11/03

U3742BM

Basic Clock Cycle of the
Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 11, this clock cycle T

is derived from the crystal oscillator

Clk

(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys­tal oscillator (f

) is defined by the RF input signal (f

XTO

operating frequency of the local oscillator (f

LO

).

) which also defines the

RFin

Figure 11. Generation of the Basic Clock Cycle

T

CLK

Divider

:14/:10

XTO

f

XTO

MODE

16

DVCC

15

XTO

14

Pin MODE can now be set in accordance with the desired clock cycle T

L : USA(:10)
H: Europe(:14)

Clk

. T

controls

Clk

the following application-relevant parameters:

• Timing of the polling circuit including bit check

• Timing of the analog and digital signal processing

• Timing of the register programming

• Frequency of the reset marker

• IF filter center frequency (f
Most applications are dominated by two transmission frequencies: f

mainly used in the USA, f

-dependent parameters, the electrical characteristics display three conditions for

T

Clk

Send

)

IF0

= 315 MHz is

Send

= 433.92 MHz in Europe. In order to ease the usage of all

each parameter.

• Application USA (f

• Application Europe (f

• Other applications (T
The electrical characteristic is given as a function of T

= 4.90625 MHz, MODE = L, T

XTO

= 6.76438 MHz, MODE = H, T

XTO

is dependent on f

Clk

XTO

= 2.0383 µs)

Clk

= 2.0697 µs)

Clk

and on the logical state of pin MODE.

).

Clk

The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T

is defined

XClk

by the following formulas for further reference:

4735A–RKE–11/03

BR_Range = BR_Range0:

BR_Range1:
BR_Range2:
BR_Range3:

T
T
T
T

XClk

XClk

XClk

XClk

= 8 ´ T
= 4 ´ T
= 2 ´ T
= 1 ´ T

Clk

Clk

Clk

Clk

11

Polling Mode According to Figure 13 on page 14, the receiver stays in polling mode in a continuous

cycle of three different modes. In sleep mode, the signal processing circuitry is disabled
for the time period T
period, T

, all signal processing circuits are enabled and settled. In the following bit

Startup

while consuming low current of IS = I

Sleep

check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter
signal. If no valid signal is present, the receiver is set back to sleep mode after the
period T
age value for T
the current consumption is IS = I

. This period varies check by check as it is a statistical process. An aver-

Bitcheck

is given in the electrical characteristics. During T

Bitcheck

. The average current consumption in polling mode is

Son

dependent on the duty cycle of the active mode and can be calculated as:

. During the start-up

Soff

and T

Startup

Bitcheck

I

I

Spoll

During T

SoffTSleepISonTStartupTBitcheck

------------ ------------- ------------- ----------- ------------ ------------- ------------- ------------- ------=

T

++

SleepTStartupTBitcheck

and T

Sleep

Startup

tee the reception of a transmitted command, the transmitter must start the telegram with
an adequate preburst. The required length of the preburst is dependent on the polling
parameters T
(T

Start,microcontroller

(N

) to be tested.

Bitcheck

Sleep

, T

). T

Startup
Bitcheck

The following formula indicates how to calculate the preburst length.
T

Preburst

³ T

Sleep

+ T

Startup

Sleep Mode The length of period T

the extension factor X

. It is calculated to be:

T

Clk

T

= Sleep ´ X

Sleep

Sleep

In US- and European applications, the maximum value of T
is set to 1. The time resolution is about 2 ms in that case. The sleep time can be
extended to almost half a second by setting X
XSleep

or by bit XSleep

Std

below:
XSleep
XSleep

= 1 implies the standard extension factor. The sleep time is always extended.

Std

= 1 implies the temporary extension factor. The extended sleep time is used

Temp

as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto­matically resulting in a regular sleep time. This functionality can be used to save current
in the presence of a modulated disturber similar to an expected transmitter signal. The
connected microcontroller is rarely activated in that condition. If the disturber disap­pears, the receiver switches back to regular polling and is again sensitive to appropriate
transmitter signals.

+()´+´

, the receiver is not sensitive to a transmitter signal. To guaran-

, T

and the startup time of a connected microcontroller

Bitcheck

thus depends on the actual bit rate and the number of bits

+ T

is defined by the 5-bit word Sleep of the OPMODE register,

Sleep

, according to Table 8 on page 21, and the basic clock cycle

Sleep

´ 1024 ´ T

+ T

Bitcheck

Temp

Start_microcontroller

Clk

is about 60 ms if X

Sleep

Sleep

to 8. X

can be set to 8 by bit

Sleep

resulting in a different mode of action as described

Sleep

12

According to Table 7 on page 21, the highest register value of Sleep sets the receiver
into a permanent sleep condition. The receiver remains in that condition until another
value for Sleep is programmed into the OPMODE register. This function is desirable
where several devices share a single data line.

U3742BM

4735A–RKE–11/03

U3742BM

Bit Check Mode In bit check mode, the incoming data stream is examined to distinguish between a valid

signal from a corresponding transmitter and signals due to noise. This is done by subse­quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of these edge-to-edge
tests, before the receiver switches to receiving mode, is also programmable.

Configuring the Bit Check Assuming a modulation scheme that contains 2 edges per bit, two time frame checks

are verifying one bit. This is valid for Manchester, bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to receiving mode due to noise. In the presence of a valid transmitter signal, the
bit check takes less time if N
time is not dependent on N
are tested successfully and the data signal is transferred to pin DATA.

According to Figure 12, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit check limit T
T

or tee exceeds T

Lim_min

switches to sleep mode.

in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge

Bitcheck

is set to a higher value, the receiver is less likely to

Bitcheck

is set to a lower value. In polling mode, the bit check

Bitcheck

. Figure 11 on page 11 shows an example where 3 bits

Bitcheck

is in between the lower bit check limit T

ee

Lim_max

Lim_max

, the check will be continued. If tee is smaller than

, the bit check will be terminated and the receiver

Lim_min

and

Figure 12. Valid Time Window for Bit Check

1/f

Sig

Dem_out

For best noise immunity it is recommended to use a low span between T
T

. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

Lim_max

T

Lim_min

T

t

ee

Lim_max

Lim_min

and

preburst. A '11111...' or a '10101...' sequence in Manchester or bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge
time t

. Using preburst patterns that contain various edge-to-edge time periods, the bit

ee

check limits must be programmed according to the required span.
The bit check limits are determined by means of the formula below:
T
T

= Lim_min ´ T

Lim_min

= (Lim_max - 1) ´ T

Lim_max

XClk

XClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the

required T

Lim_max

is T

T

, T

Lim_min

. The minimum edge-to-edge time tee (t

XClk

Lim_max

and T

. The time resolution when defining T

XClk

DATA_L_min

, t

DATA_H_min

and

Lim_min

) is defined
according to the section “Receiving Mode” on page 16. Due to this, the lower limit
should be set to Lim_min

³ 10. The maximum value of the upper limit is Lim_max = 63.

4735A–RKE–11/03

13

Figure 13. Polling Mode Flow Chart

Sleep mode:

All circuits for signal processing
are disabled. Only XTO and
polling logic are enabled.

= I

I

S

Soff

T

= Sleep × X

Sleep

Sleep

Start-up mode:

The signal processing circuits are
enabled. After the start-up time

(T

) all circuits are in stable

Startup

condition and ready to receive.

= I

I

S

Son

T

Startup

Bit check mode:

The incoming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver
is set to receiving mode. Otherwise
it is set to Sleep mode.

I

= I

S

Son

T

Bitcheck

NO

Bit check

OK ?

× 1024 × T

Clk

Sleep: 5-bit word defined by Sleep0 to

Sleep4 in OPMODE register

X

: Extension factor defined by

Sleep

XSleep

according to Table 8

: Basic clock cycle defined by f

T

CLK

: Is defined by the selected baud rate range and T

T

Startup

and XSleep

Std

Temp

XTO

The baud rate range is defined by Baud0 and Baud1

in the OPMODE register.

T

: Depends on the result of the bit check

Bitcheck

If the bit check is ok, T

bitcheck

depends on

the number of bits to be checked (N
and on the utilized data rate.

If the bit check fails, the average time period for
that check depends on the selected baud rate
range and on T

. The baud rate is defined by

Clk

Baud0 and Baud1 in the OPMODE register.

and pin MODE

)

Bitcheck

Clk

.

YES

Receiving mode:

The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set
to Sleep mode through an OFF
command via pin DATA or ENABLE.

IS = I

Son

OFF command

14

U3742BM

4735A–RKE–11/03

Figure 14. Timing Diagram for Complete Successful Bit Check

U3742BM

(Number of checked bits: 3)

Enable IC

Bit check

1/2 Bit

Dem_out

DATA

Startup mode

Figure 15. Timing Diagram During Bit Check

(Lim_min = 14, Lim_max = 24)

Enable IC

T

Startup

Bit check

Dem_out

Bit check counter

0

2345

Bit check ok

1/2 Bit

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Bit check mode

1/2 Bit

6 2451781 3 6 7 8 9 1112131410

Receiving mode

Bit check ok

151617 18 1 2 3 4 56

Bit check ok

1/2 Bit 1/2 Bit

7 8 9 101112131415 1 2 3 4

T

XCLK

Figure 16. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Bit check counter

Startup mode

1/2 Bit

0

2345

6 2451 1 3678

Bit check mode

Bit check failed (CV_Lim < Lim_min)

1112

9

10

0

Sleep mode

4735A–RKE–11/03

15

Figure 17. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max)

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Bit check counter

Startup mode

1/2 Bit

023456 2451 7 36789

1

Bit check mode

111210

13141516171819 21222324

Bit check failed (CV_Lim ≥ Lim_max)

20

0

Sleep mode

Figure 15 to Figure 17 illustrate the bit check for the default bit check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T

. The output of the ASK/FSK demodulator (Dem_out) is unde-

Startup

fined during that period. When the bit check becomes active, the bit check counter is
clocked with the cycle T

XClk

.

Figure 15 on page 15 shows how the bit check proceeds if the bit check counter value
CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a sig­nal edge. In Figure 16 on page 15, the bit check fails as the value CV_lim is lower than
the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated
in Figure 17.

Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK

demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
characteristics. T
baud rate range causes a lower value for T

depends on the selected baud rate range and on T

Bitcheck

resulting in a lower current consump-

Bitcheck

is given in the electrical

Bitcheck

. A higher

Clk

Bitcheck

tion in polling mode.
In the presence of a valid transmitter signal, T

that signal, f
thereby results in a longer period for T
preburst T

and the count of the checked bits, N

Sig

Bitcheck

Preburst

.

requiring a higher value for the transmitter

Receiving Mode If the bit check has been successful for all bits specified by N

is dependant on the frequency of

Bitcheck

. A higher value for N

Bitcheck

Bitcheck

, the receiver

Bitcheck

switches to receiving mode. According to Figure 14, the internal data signal is switched
to pin DATA in that case. A connected microcontroller can be woken up by the negative
edge at pin DATA. The receiver stays in that condition until it is switched back to polling
mode explicitly.

Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different

ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 18 on page 17 illustrates how

. This clock is also used for

XClk

elapsed. The

XClk

4735A–RKE–11/03

16

U3742BM

Dem_out is synchronized by the extended clock cycle T
the bit check counter. Data can change its state only after T
edge-to-edge time period t

XClk

.

of T

of the Data signal as a result is always an integral multiple

ee

U3742BM

The minimum time period between two edges of the data signal is limited to

³ T

t

ee

DATA_min

same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T
ceding edge-to-edge time interval tee as illustrated in Figure 19. If t
specified bit check limits, the following level is frozen for the time period
T

DATA_min

the relevant stable time period.

. This implies an efficient suppression of spikes at the DATA output. At the

DATA_min

= tmin1, in case of tee being outside that bit check limits T

is to some extent affected by the pre-

is in between the

ee

DATA_min

= tmin2 is

The maximum time period for DATA to be Low is limited to T
ensures a finite response time during programming or switching off the receiver via pin
DATA. T

DATA_L_max

is thereby longer than the maximum time period indicated by the
transmitter data stream. Figure 20 gives an example where Dem_out remains Low after
the receiver is in receiving mode.

Figure 18. Synchronization of the Demodulator Output

T

XClk

Clock bit check

Counter

Dem_out

DATA

t

ee

Figure 19. Debouncing of the Demodulator Output

Dem_out

DATA_L_max

. This function

DATA

Lim_min ≤ CV_Lim < Lim_max

t

ee

tmin1

CV_Lim < Lim_min or CV_Lim ≥ Lim_max

t

ee

Figure 20. Steady L State Limited DATA Output Pattern after Transmission

Enable IC

Bit check

Dem_out

DATA

Startup mode

4735A–RKE–11/03

Bit check mode

Receiving mode

tmin2

tmin2

t

DATA_L_max

17

After the end of data transmission, the receiver remains active and random noise pulses
appear at pin DATA. The edge-to-edge time period t
pulses is equal to or slightly higher than T

DATA_min

.

of the majority of these noise

ee

Switching the Receiver Back
to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to Low for the period t

microcontroller. Figure 21 illustrates the timing of the OFF command (see also Figure 25
on page 23). The minimum value of t

is not limited but it is recommended not to exceed the specified value to prevent eras-

t

1

ing the reset marker. This item is explained in more detail in the section “Configuration
of the Receiver” on page 19. Setting the receiver to sleep mode via DATA is achieved
by programming bit 1 of the OPMODE register to be '1'. Only one sync pulse (t
issued.

The duration of the OFF command is determined by the sum of t
OFF command, the sleep time T
is limited. The resulting time constant
may not be exceeded to ensure proper operation.

If the receiver is set to polling mode via pin ENABLE, an 'L' pulse (T
at that pin. Figure 22 on page 19 illustrates the timing of that command. After the posi­tive edge of this pulse, the sleep time T
mode as long as ENABLE is held to 'L'. If the receiver is polled exclusively by a micro­controller, T

can be programmed to 0 to enable a instantaneous response time. This

Sleep

command is the faster option than via pin DATA at the cost of an additional connection
to the microcontroller.

Figure 21. Timing Diagram of the OFF-command via Pin DATA

by the connected

1

depends on BR_Range. The maximum value for

1

, t2 and t10. After the

elapses. Note that the capacitive load at pin DATA

Sleep

1

t together with an optional external pull-up resistor

) must be issued

Doze

elapses. The receiver remains in sleep

Sleep

3

) is

Out1 (microcontroller)

DATA (U3742BM)

Serial bi-directional
data line

X

X

Receiving

mode

t

1

t

2

OFF command

t

3

(Startbit)

t

4

Bit 1
("1")

t

5

t

10

t

7

T

Sleep

Startup mode

18

U3742BM

4735A–RKE–11/03

Figure 22. Timing Diagram of the OFF-command via Pin ENABLE

U3742BM

ENABLE

DATA (U3742BM)

Serial bi-directional
data line

Configuration of the
Receiver

X

X

Receiving mode

The U3742BM receiver is configured via two 12-bit RAM registers called OPMODE and
LIMIT. The registers can be programmed by means of the bi-directional DATA port. If
the register contents have changed due to a voltage drop, this condition is indicated by a
certain output pattern called reset marker (RM). The receiver must be reprogrammed in
that case. After a power-on reset (POR), the registers are set to default mode. If the
receiver is operated in default mode, there is no need to program the registers.

Table 3 on page 20 shows the structure of the registers. According to Table 2, bit 1
defines if the receiver is set back to polling mode via the OFF command, (see section
“Receiving Mode” on page 16) or if it is programmed. Bit 2 represents the register
address. It selects the appropriate register to be programmed.

T

Doze

t

off

T

Sleep

Startup mode

Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers

Bit 1 Bit 2 Action

1 x The receiver is set back to polling mode (OFF command)
0 1 The OPMODE register is programmed
0 0 The LIMIT register is programmed

Table 4 on page 20 and the following illustrate the effect of the individual configuration
words. The default configuration is highlighted for each word.

BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim
is used to define the bit check limits T

Lim_min

and T

as shown in Table 4 on page

Lim_max

20.

4735A–RKE–11/03

19

Table 3. Effect of the Configuration Words within the Registers

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14

OFF Command

1

OPMODE Register

0 1 BR_Range N
0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X

(Default)00100010110 0

LIMIT Register

0 0 Lim_min Lim_max
0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0

(Default)00111001100 0

Bitcheck

V

POUT

Sleep XSleep

Sleep StdXSleep Temp

Table 4. Effect of the Configuration Word BR_Range

BR_Range

Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0

00

01

10

11

BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)

BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4

BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2

BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1

Table 5. Effect of the Configuration Word N

N

Bitcheck

Bitcheck

00 0
01 3
1 0 6 (Default)
11 9

Table 6. Effect of the Configuration Bit Reserved

Reserved Bit No Function (Reserved for Future Use)

0(Default)
1

Number of Bits to be CheckedBitChk1 BitChk0

20

U3742BM

4735A–RKE–11/03

U3742BM

Table 7. Effect of the Configuration Word Sleep

Sleep

000000 (Receiver is continuously polling until a valid signal occurs)
000011 (T

Sleep

00010 2
00011 3

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

0101111 (USA: T

.
.
.

.
.
.

.
.
.

.
.
.

.
.

.
11101 29
11110 30
11111 31 (Permanent sleep mode)

Start Value for Sleep Counter

= Sleep × Xsleep × 1024 × T

(T

Sleep

Clk

)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0

» 2ms for XSleep = 1 in US/European applications)

.
.
.

= 22.96 ms, Europe: T

Sleep

= 23.31 ms) (Default)

Sleep

.
.
.

Table 8. Effect of the Configuration Word XSleep

XSleep

Std

XSleep

Temp

Extension Factor for Sleep Time (T

Sleep

0 0 1 (Default)
0 1 8 (XSleep is reset to 1 if bit check fails once)
1 0 8 (XSleep is set permanently)
1 1 8 (XSleep is set permanently)

Table 9. Effect of the Configuration Word Lim_min

Lim_min Lower Limit Value for Bit Check

Lim_min < 10 is not applicable (T

001010 10
001011 11
001100 12
001101 13

001110

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

(USA: T

Lim_min

111101 61
111110 62
111111 63

= Lim_min × XLim × T

Lim_min

14 (Default)

= 228 µs, Europe: T

= Sleep × Xsleep × 1024 × T

)

Clk

= 232 µs)

Lim_min

Clk

)XSleep

4735A–RKE–11/03

21

Table 10. Effect of the Configuration Word Lim_max

Lim_max Upper Limit Value for Bit Check

Lim_max < 12 is not applicable (T

001100 12
001101 13
001110 14

.
.
.

011000

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

(USA: T

.
.
.

.
.
.

.
.
.

.
.
.

.
.

.
111101 61
111110 62
111111 63

= (Lim_max - 1) × XLim × T

Lim_max

24 (Default)

= 375 µs, Europe: T

Lim_max

Lim_max

)

Clk

= 381 µs)

Conservation of the Register
Information

The U3742BM has an integrated power-on reset (POR) and brown-out detection cir­cuitry to provide a mechanism to preserve the RAM register information.

According to Figure 23, a power-on reset is generated if the supply voltage V
below the threshold voltage V
configuration registers in that condition. Once V
after the minimum reset period t
the receiver is turned on.

To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a
reset. The RM is represented by the fixed frequency f
canceled via an 'L' pulse t

•fRM is lower than the lowest feasible frequency of a data signal. This means, RM
cannot be misinterpreted by the connected microcontroller.

• If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by
accident if t
Configuration Register” on page 23.

By means of that mechanism, the receiver cannot lose its register information without
communicating that condition via the reset marker RM.

Figure 23. Generation of the Power-on Reset

V

S

POR

t

Rst

DATA (U3742BM)

X

drops

. The default parameters are programmed into the

ThReset

. A POR is also generated when the supply voltage of

Rst

at pin DATA. The RM implies the following characteristics:

1

is applied according to the proposal in the section “Programming the

1

V

ThReset

exceeds V

S

at a 50% duty cycle. RM can be

RM

, the POR is canceled

ThReset

S

22

U3742BM

1/f

RM

4735A–RKE–11/03

Figure 24. Timing of the Register Programming

U3742BM

Out1
(microcontroller)

DATA (U3742BM)

Serial bi-directional
data line

Receiving

mode

Programming the
Configuration Register

t

1

X

X

t

t

2

t

3

5

t

4

t

6

t

7

Bit 1
("0")

(Startbit) (Register-

Bit 2
("1")

select)

Programming frame

Bit 13
("0")

(Poll8) (Poll8R)

Bit 14
("1")

T

t

Sleep

9

t

8

Startup

mode

The configuration registers are programmed serially via the bi-directional data line
according to Figure 24 and Figure 25.

Figure 25. One-wire Connection to a Microcontroller

U3742BM

Internal pull-up

resistor

Bi-directional

data line

Microcontroller

DATA I/O

Data

Out 1 (microcontroller)

(U3742BM)

To start programming, the serial data line DATA is pulled to 'L' for the time period t1 by
the microcontroller. When DATA has been released, the receiver becomes the master
device. When the programming delay period t
chronization pulses with the pulse length t
window occurs. The delay until the program window starts is determined by t
tion is defined by t

. Within the programming window, the individual bits are set. If the

5

microcontroller pulls down pin DATA for the time period t
no programming pulse t

is issued, this bit is set to '1'. All 14 bits are subsequently pro-

7

grammed in this way. The time frame to program a bit is defined by t
Bit 14 is followed by the equivalent time window t

acknowledge pulse t

(E_Ack) occurs if the just programmed mode word is equivalent to

8

has elapsed, it emits 14 subsequent syn-

2

. After each of these pulses, a programming

3

during t5, the bit is set to '0'. If

7

.

6

. During this window, the equivalent

9

, the dura-

4

the mode word that was already stored in that register. E_Ack should be used to verify
that the mode word was correctly transferred to the register. The register must be pro­grammed twice in that case.

Programming of a register is possible both during sleep and active mode of the receiver.

4735A–RKE–11/03

23

During programming, the LNA, LO, low-pass filter, IF-amplifier and the FSK/ASK
Manchester demodulator are disabled.

The programming start pulse t

initiates the programming of the configuration registers.

1

If bit 1 is set to '1', it represents the OFF-command to set the receiver back to polling
mode at the same time. For the length of the programming start pulse t

, the following

1

convention should be considered:

•t1(min) < t1 < 1535 ´ T

: [t1(min) is the minimum specified value for the relevant

Clk

BR_Range]

Programming (respectively OFF-command) is initiated if the receiver is not in reset
mode. If the receiver is in reset mode, programming (respectively Off-command) is not
initiated, and the reset marker RM is still present at pin DATA.

This period is generally used to switch the receiver to polling mode. In a reset condition,
RM is not canceled by accident.

•t1 > 5632 ´ T

Clk

Programming (respectively OFF-command) is initiated in any case. RM is canceled if
present.

This period is used if the connected microcontroller detected RM. If a configuration reg­ister is programmed, this time period for t

can generally be used. Note that the

1

capacitive load at pin DATA is limited. The resulting time constant t together with an
optional external pull-up resistor may not be exceeded to ensure proper operation.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Max. Unit

Power dissipation P
Junction temperature T
Storage temperature T
Ambient temperature T
Maximum input level, input matched to 50 W P

in_max

tot

stg

amb

j

-55 +125 °C

-40 +105 °C

450 mW
150 °C

10 dBm

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

24

U3742BM

thJA

100 K/W

4735A–RKE–11/03

Electrical Characteristics

U3742BM

All parameters refer to GND, T
wise specified. (V

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Parameter Test Condition Symbol
Basic Clock Cycle of the Digital Circuitry

Basic clock
cycle

Extended
basic clock
cycle

MODE = 0 (USA)
MODE = 1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

T

Clk

T

XClk

Polling Mode

Sleep and XSleep

Sleep time

are defined in the
OPMODE register

T

Sleep

BR_Range0
BR_Range1

Start-up time

BR_Range2
BR_Range3

T

Startup

Average bit check
time while polling
BR_Range0
BR_Range1

T

Bitcheck

BR_Range2

Time for Bit
Check

BR_Range3

Bit check time for a
valid input signal f
N

= 0

Bitcheck

N

= 3

Bitcheck

= 6

N

Bitcheck

= 9

N

Bitcheck

Sig

T

Bitcheck

Receiving Mode

6.76438 Mhz Oscillator
(Mode 1)

2.0697

16.6

8.3

4.1

2.1

Sleep ´

´

X

Sleep

´

1024

2.0697
1855

1061
1061

663

0.45

0.24

0.14

0.14

3/f
6/f
9/f

Sig
Sig
Sig

3.5/f

6.5/f

9.5/f

4.90625 Mhz Oscillator
(Mode 0) Variable Oscillator

2.0383 1/(f

16.3

8.2

4.1

2.0

Sleep
X

Sleep

1024

2.0383
1827

1045
1045

653

0.47

0.26

0.16

0.15

3/f

Sig

Sig

6/f

Sig

Sig

9/f

Sig

Sig

´

´

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

/10)

XTO

1/(f

/14)

XTO

´ T

8

Clk

4 ´ T

Clk

2 ´T

Clk

1 ´ T

Clk

´

Sleep

X

Sleep

1024

T

Clk

´

´

´

896.5

512.5

512.5

320.5

´ T

Clk

µs
µs

µs
µs
µs
µs

ms

µs
µs
µs
µs

ms
ms
ms
ms

3.5/f

6.5/f

9.5/f

Sig
Sig
Sig

3/f
6/f
9/f

T

XClk

Sig
Sig
Sig

T

3.5/f

6.5/f

9.5/f

XClk

Sig
Sig
Sig

ms
ms
ms
ms

Intermediate
frequency

Baud rate
range

Minimum time
period
between
edges at
pin DATA
(Figure 19 on
page 17)

4735A–RKE–11/03

MODE=0 (USA)
MODE=1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range0

BR_Range1

BR_Range2

BR_Range3

f

IF

BR_Range

T

DATA_min

tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2

1.0

1.8

3.2

5.6

1.0

149
182

75
91

37.3

45.5

18.6

22.8

1.8

3.2

5.6

10.0

1.0

1.8

3.2

5.6

1.0 f

1.8

3.2

5.6

10.0

BR_Range0
BR_Range1
BR_Range2 ´ 2 µs/T
BR_Range3 ´ 2 µs/T

147
179

73
90

36.7

44.8

18.3

22.4

XTO

´ 64/432.92

f

XTO

9

11 ´ T

9 ´ T

11 ´ T

9 ´ T

11 ´ T

9 ´ T

11 ´ T

´ 64/314

´ 2 µs/T
´ 2 µs/T

´ T

XClk

XCl

XClk

XClk

XClk

XClk

XClk

XClk

Clk
Clk
Clk
Clk

MHz
MHz

kBaud
kBaud
kBaud
kBaud

µs
µs
µs
µs

µs
µs
µs

25

Electrical Characteristics (Continued)

All parameters refer to GND, T
wise specified. (V

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Parameter Test Condition Symbol

Maximum low
period at DATA
(Figure 20)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

T

DATA_L_max

OFF
command at
pin ENABLE

t

Doze

(Figure 22)

Configuration of the Receiver

Frequency of
the reset
marker

f

RM

(Figure 23)

BR_Range0

BR_Range1

Programming
start pulse
(Figure 21,
Figure 24)

BR_Range2

BR_Range3

t

1

after POR

6.76438 Mhz Oscillator
(Mode 1)

2169
1085

542
271

3.1 3.05

117.9 119.8 Hz

2188

1104

561

290

3176

3176

3176

3176

11656

4.90625 Mhz Oscillator
(Mode 0) Variable Oscillator

2136
1068

534
267

2155

1087

553

286

3128

3128

3128

3128

11479

1.5
T

Clk

1057
T

Clk

533 ´
T

Clk

271 ´
T

Clk

140 ´
T

Clk

5632 ´
T

Clk

´

´

´ T

131

XClk

131 ´ T

XClk

131 ´ T

XClk

131 ´ T

XClk

1

--------------------------------­4096 T

´

CLK

1535 ´

T

Clk

1535 ´

T

Clk

1535 ´

T

Clk

1535 ´

T

Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs
µs
µs
µs

µs

µs

Programming
delay period
(Figure 21,
Figure 24)

Synchroni­zation pulse
(Figure 21,
Figure 24)

Delay until the
program
window starts
(Figure 21,
Figure 24)

Programming
window
(Figure 21,
Figure 24)

Time frame
of a bit
(Figure 24)

Programming
pulse (Figure
21, Figure 24)

´

t

2

t

3

t

4

t

5

t

6

t

7

795 798 783 786

265 261 128 ´ T

131 129 63.5 ´ T

530 522 256 ´ T

1060 1044 512 ´ T

133 529 131 521

384.5
T

Clk

64

T

Clk

´

Clk

Clk

Clk

Clk

385.5 ´
T

Clk

256 ´

T

Clk

µs

µs

µs

µs

µs

µs

26

U3742BM

4735A–RKE–11/03

Electrical Characteristics (Continued)

U3742BM

All parameters refer to GND, T
wise specified. (V

Parameter Test Condition Symbol

Equivalent
acknowledge
pulse: E_Ack
(Figure 24)

Equivalent
time window
(Figure 24)

OFF-bit
programming
window
(Figure 21)

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

6.76438 Mhz Oscillator
(Mode 1)

t

8

t

9

t

10

265 261 128 ´ T

534 526 258 ´ T

930 916 449.5 ´ T

4.90625 Mhz Oscillator
(Mode 0) Variable Oscillator

Clk

Clk

Clk

Electrical Characteristics

All parameters refer to GND, T
wise specified. (V

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Current consumption

LNA Mixer

Third-order intercept point

LO spurious emission at RF

Noise figure LNA and mixer (DSB) Input matching according to Figure 6 NF 7 dB

LNA_IN input impedance

1 dB compression point
(LNA, mixer, IF amplifier)

Maximum input level

Local Oscillator

Operating frequency range VCO f

Phase noise VCO/LO

Spurious of the VCO at ±f
VCO gain K

= 5 V, T

S

In

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Sleep mode
(XTO and polling logic active)

IS

off

190 350 µA

IC active
(startup-, bit check-, receiving mode)

IS

on

7.0 8.6 mA

pin DATA = H

LNA/mixer/IF amplifier
input matched according to Figure 6

Input matched according to Figure 6,
required according to I-ETS 300220

at 433.92 MHz
at 315 MHz

Input matched according to Figure 6,
referred to RF

Input matched according to Figure 6,
BER

£ 10

in

-3

,

ASK mode

f

= 432.92 MHz

osc

at 1 MHz
at 10 MHz

XTO

IIP3 -28 dBm

IS

Zi

IP

P

LORF

LNA_IN

1db

in_max

-73 -57 dBm

1.0 || 1.56

1.3 || 1.0

-40 dBm

-28

-20

VCO

L (fm) -93

299 449 MHz

-90

-113

-110

-55 -47 dBC

VCO

190 MHz/V

kW || pF
k

W || pF

dBm
dBm

dBC/Hz
dBC/Hz

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs

µs

µs

4735A–RKE–11/03

27

Electrical Characteristics (Continued)

All parameters refer to GND, T
wise specified. (V

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

For best LO noise
(design parameter)

Loop bandwidth of the PLL

R

= 820 W

1

B

Loop

100 kHz
C9 = 4.7 nF
C

= 1 nF

10

The capacitive load at pin LF is limited

Capacitive load at pin LF

if bit check is used. The limitation

C

LF_tot

10 nF

therefore also applies to self-polling.
XTO crystal frequency,

appropriate load capacitance must be
connected to XTAL

XTO operating frequency

Series resonance resistor of the
crystal

Static capacitance of the crystal C

6.764375 MHz

4.90625 MHz

f

= 6.764 MHz

XTO

4.906 MHz

f

XTO

R

xto

6.764375

-30 ppm

4.90625

-30 ppm

S

6.764375

4.90625

6.764375
+30 ppm

4.90625

+30 ppm

150
220

MHz

MHz

W
W

6.5 pF

Analog Signal Processing

Input matched according to Figure 6

Input sensitivity ASK

ASK (level of carrier)
BER
f

= 433.92 MHz/315 MHz

in

T = 25

£ 10

°C, V

-3

, fIF = 1 MHz

= 5 V

S

P

Ref_ASK

BR_Range0 -108 -110 -112 dBm

Input sensitivity ASK

BR_Range1 -106.5 -108.5 -110.5 dBm
BR_Range2 -106 -108 -110 dBm
BR_Range3 -104 -106 -108 dBm

Sensitivity variation ASK for the full
operating range compared to

T

= 25°C, VS=5V

amb

Sensitivity variation ASK for full
operating range including IF filter
compared to T

=25°C, VS = 5 V

amb

Input sensitivity FSK

fin = 433.92 MHz/315 MHz
f

= 1 MHz

IF

P

ASK

= P

Ref_ASK

+ DP

Ref

fin = 433.92 MHz/315 MHz
f

= 0.79 MHz to 1.21 MHz

IF

f

= 0.73 MHz to 1.27 MHz

IF

P

= P

ASK

Input matched according to Figure 6,
BER

£ 10

f

= 433.92 MHz/315 MHz

in

T = 25

°C, V

+ DP

Ref_ASK

-3

, fIF = 1 MHz

= 5 V

S

Ref

DP

DP

P

Ref_FSK

Ref

Ref

+2.5 -1.5 dB

+5.5
+7.5

-1.5

-1.5

dB
dB

BR_Range0
df

Input sensitivity FSK

³ ±20 kHz

df

³ ±30 kHz

BR_Range1
df

³ ±20 kHz

df

³ ±30 kHz

-95.5

-96.5

-94.5

-95.5

-97.5

-98.5

-96.5

-97.5

-99.5

-100.5

-98.5

-99.5

dBm
dBm

dBm
dBm

28

U3742BM

4735A–RKE–11/03

Electrical Characteristics (Continued)

U3742BM

All parameters refer to GND, T
wise specified. (V

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Sensitivity variation FSK for the full
operating range compared to
T

=25°C, VS=5V

amb

Sensitivity variation FSK for full
operating range including IF filter
compared to T

=25°C, VS = 5 V

amb

fin = 433.92 MHz/315 MHz
f

= 1 MHz

IF

P

FSK

= P

Ref_FSK

+ DP

Ref

fin = 433.92 MHz/315 MHz
f

= 0.86 MHz to 1.14 MHz

IF

f

= 0.82 MHz to 1.18 MHz

IF

P

FSK

= P

Ref_FSK

+ DP

Ref

DP

DP

Ref

Ref

+2.5 -1.5 dB

+5.5
+7.5

-1.5

-1.5

dB
dB

The sensitivity of the receiver is higher

FSK frequency deviation

for higher values of
BR_Range0
BR_Range1

Df

FSK

Df

FSK

20
20

30
30

50
50

kHz

kHz
BR_Range2 and BR_Range3 are not
suitable for FSK operation

S/N ratio to suppress inband noise
signals

Dynamic range RSSI amplifier DR

Lower cut-off frequency of the data
filter

ASK mode
FSK mode

f

cu_DF

------------- ----------------- ----------------- ------------=
2

p´ 30 kW´ CDEM´

SNR

ASK

SNR

FSK

RSSI

1

f

cu_DF

10

2

12

dB

3

dB

60 dB

0.11 0.16 0.20 kHz

ASK mode

Recommended CDEM for best
performance

BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

CDEM

39
22
12

8.2

nF
nF
nF
nF

FSK mode

Recommended CDEM for best
performance

BR_Range0 (Default)
BR_Range1
BR_Range2 and BR_Range3 are not

CDEM

27
15

nF
nF

suitable for FSK operation

µs
µs
µs
µs

Maximum edge-to-edge time period of
the input data signal for full sensitivity

BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

t

ee_sig

1000

560
320
180

Upper cut-off frequency programmable
in 4 ranges via a serial mode word

Upper cut-off frequency data filter

Minimum edge-to-edge time period of
the input data signal for full sensitivity

Reduced sensitivity

BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

R

connected from pin Sens to VS,

Sense

input matched according to Figure 6

f

u

2.5

4.3

7.6

13.6

3.1

5.4

9.5

17.0

3.7

6.5

11.4

20.4
270

t

ee_sig

156

89
50

P

Ref_Red

kHz
kHz
kHz
kHz

µs
µs
µs
µs

dBm

(peak

level)

4735A–RKE–11/03

29

Electrical Characteristics (Continued)

All parameters refer to GND, T
wise specified. (V

= 5 V, T

S

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless other-

amb

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Reduced sensitivity

Reduced sensitivity variation over full
operating range

(VS=5V, T
R

= 56 kW, fin= 433.92 MHz,

Sense

R

= 100 kW, fin = 433.92 MHz -76 -81 -86 dBm

Sense

R

= 56 kW, fin = 315 MHz -68 -73 -78 dBm

Sense

R

= 100 kW, fin = 315 MHz -77 -82 -87 dBm

Sense

R

= 56 kW

Sense

R

= 100 kW

Sense

P

= P

Red

amb

Ref_Red

=25°C)

+ DP

Red

DP

Red

-67 -72 -77 dBm

5
6

0
0

0
0

dB
dB

Values relative to
R

= 56 kW

Sense

dB
dB
dB
dB
dB
dB

Reduced sensitivity variation for
different values of R

Sense

Threshold voltage for reset

R
R
R
R
R
R
P

Sense
Sense
Sense
Sense
Sense
Sense
Red

= 56 kW
= 68 kW
= 82 kW
= 100 kW
= 120 kW
= 150 kW

= P

Ref_Red

+ DP

Red

DP

V

ThRESET

Red

0

-3.5

-6.0

-9.0

-11.0

-13.5

1.95 2.8 3.75 V

Digital Ports

Data output

- Saturation voltage LOW

- Internal pull-up resistor

- Maximum time constant

- Maximum capacitive load
FSK/ASK input

- Low-level input voltage

- High-level input voltage
ENABLE input

- Low-level input voltage

- High-level input voltage
MODE input

- Low-level input voltage

- High-level input voltage
TEST input

- Low-level input voltage

Iol = 1 mA

t = C

(R

//R

L

pup

Ext

)
without external pull-up resistor
R

= 5 kW

ext

FSK selected
ASK selected

Idle mode
Active mode

Division factor = 10
Division factor = 14

Test input must always be set to LOW

V

OI

R

Pup

39

t

C

L

C

L

V

Il

V

Ih

V

Il

V

Ih

V

Il

V

Ih

V

Il

0.8 ´ V

0.8 ´ V

0.8 ´ V

0.08
50

0.3
61

2.5
41

540

0.2 ´ V

S

0.2 ´ V

S

0.2 ´ V

S

0.2 ´ V

V

k

W

µs
pF
pF

V

S

V

V

S

V

V

S

V

V

S

30

U3742BM

4735A–RKE–11/03

Ordering Information

Extended Type Number Package Remarks

U3742BM-M3FL SO20 Tube
U3742BM-M3FLG3 SO20 Taped and reeled

Package Information

U3742BM

Package SO20

Dimensions in mm

0.4

1.27

20 11

12.95

12.70

11.43

0.25

0.10

2.35

technical drawings
according to DIN
specifications

9.15

8.65

7.5

7.3

0.25

10.50

10.20

4735A–RKE–11/03

110

31

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4735A–RKE–11/03