Rainbow Electronics U3741BM User Manual

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self Polling with a Programmable Time

Frame Check

• Supply Voltage 4.5 V to 5.5 V

• Operating Temperature Range -40°C to 105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD 883 (4KV HBM) Except Pin POUT (2KV HBM)

• High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW

Front-end Filter

– Up to 40 dB is Thereby Achievable with Newer SAWs.

• Programmable Output Port for Sensitivity Selection or for Controlling External

Periphery

• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

• 2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

Description

The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL
RF transmitter U2741B. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
ments made below refer to 433.92-MHz and 315-MHz applications.

= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-

0

UHF ASK
Receiver IC

U3741BM

Rev. 4662B–RKE–10/04

System Block Diagram

1 Li cell

Encoder

ATARx9x

Keys

Block Diagram

UHF ASK/FSK

Remote control transmitter

U2741B

FSK/ASK

CDEM

AVCC

SENS

AGND

DGND

PLL

VCOXTO

Power

amp.

FSK/ASK-

Demodulator

and data filter

IF Amp

4th Order

Antenna

Limiter outRSSI

Antenna

DEMOD_OUT

Sensitivity
reduction

UHF ASK/FSK

Remote control receiver

U3741BM

Demod

Polling circuit

and

control logic

FE CLK

PLL XTO

VCOLNA

50 kΩ

V

S

Control

DATA

ENABLE

TEST

POUT

MODE

DVCC

1...3
µC

LPF

MIXVCC

LNAGND

LNA_IN

2

U3741BM

LNA

3 MHz

IF Amp

LPF

3 MHz

Standby logic

VCO XTO

f

÷ 64

LFGND

LFVCC

XTO

LF

4662B–RKE–10/04

Pin Configuration Figure 1. Pinning SO20

DATA

SENS

FSK/ASK

CDEM

AVCC
AGND
DGND

MIXVCC

LNAGND

LNA_IN

NC

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

ENABLE
TEST
POUT
MODE
DVCC
XTO
LFGND
LF
LFVCC

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor
2 FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK
3 CDEM Lower cut-off frequency data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer

9LNA_INRF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply
16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)
17 POUT Programmable output port
18 TEST Test pin, during operation at GND

Enables the polling mode

19 ENABLE

20 DATA Data output/configuration input

Low: polling mode off (sleep mode)
H: polling mode on (active mode)

U3741BM

4662B–RKE–10/04

3

RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input

signal into a 1-MHz IF signal. According to the block diagram, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at pin LF. f
to f

by the phase frequency detector. The current output of the phase frequency

XTO

is divided by a factor of 64. The divided frequency is compared

LO

LO

detector is connected to a passive loop filter and thereby generates the control voltage

for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is

V

LF

equal to f

f

XTO

. If fLO is determined, f

XTO

f

LO

--------=

64

can be calculated using the following formula:

XTO

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys­tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f

. When designing the system in terms of receiving bandwidth, the accuracy

LO

of the crystal and XTO must be considered.

Figure 2. PLL Peripherals

V

S

DVCC

C

XTO

. The VCO (voltage-controlled

XTO

for the mixer. fLO is dependent on

and

XTO

L

LFGND

R1 = 820 Ω

C9 = 4.7 nF

LF

LFVCC

R1

V

S

C9

C10 = 1 nF

C10

The passive loop filter connected to pin LF is designed for a loop bandwidth of

= 100 kHz. This value for B

B

Loop

exhibits the best possible noise performance of the

Loop

LO. Figure 2 shows the appropriate loop filter components to achieve the desired loop
bandwidth. If the filter components are changed for any reason, please note that the
maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f

cannot settle in time before the bit check

LO

starts to evaluate the incoming data stream. Therefore, self polling also does not work in
that case.

is determined by the RF input frequency fRF and the IF frequency fIF using the follow-

f

LO

ing formula:

f

LOfRFfIF

–=

4

U3741BM

4662B–RKE–10/04

U3741BM

To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is f
quencies, the filter is tuned by the crystal frequency f
fixed relation between f
described by the following formulas:

MODE 0 (USA) f

MODE 0 (Europe) f

IF

= 1 MHz. To achieve a good accuracy of the filter’s corner fre-

IF

and fLO that depends on the logic level at pin mode. This is

IF

f

LO

----------==

314

f

LO

------------- -----==

432.92

IF

. This means that there is a

XTO

The relation is designed to achieve the nominal IF frequency of f
applications. For applications where f
case of f
not equal to 1 MHz. f

= 433.92 MHz, the MODE must be set to ‘1’. For other RF frequencies, fIF is

RF

is then dependent on the logical level at pin MODE and on fRF.

IF

= 315 MHz, the MODE must be set to ‘0’. In the

RF

= 1 MHz for most

IF

Table 1 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF

input pin LNA_IN. The input impedance of that pin is provided in the electrical parame­ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver U3741BM exhibits its highest sensitivity at the best sig­nal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the
transformation network.

A good practice when designing the network is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of

= 40 dB can be achieved. There are SAWs available that exhibit a notch at

∆P

Ref

∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The
selectivity of the receiver is also improved by using a SAW. In typical automotive appli­cations, a SAW is used.

Figure 3 on page 6 shows a typical input matching network for f

= 433.92 MHz using a SAW. Figure 4 on page 6 illustrates an input matching to 50 Ω

f

RF

= 315 MHz and

RF

without a SAW. The input matching networks shown in Figure 4 are the reference net­works for the parameters given in the “Electrical Characteristics”.

Table 1. Calculation of LO and IF Frequency

Conditions Local Oscillator Frequency Intermediate Frequency

= 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz

f

RF

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

f

RF

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < f

4662B–RKE–10/04

< 450 MHz, MODE = 1

RF

f

LO

1

f

------------ ------------- ---= f

LO

1

1

----------+

314

f

RF

1

------------ ------+

432.92

f

RF

------------ -------= f

IF

IF

f

LO

----------=
314

f

LO

------------ ------=

432.92

5

Figure 3. Input Matching Network with SAW Filter

8

LNAGND

C3

22p

fRF = 433.92 MHz

C2

8.2p

TOKO LL2012

F33NJ

RF

IN

L2

33n

L

25n

1
2

IN
IN_GND

U3741BM

9

LNA_IN

C16

100p

27n

B3555

CASE_GND

3, 4 7, 8

L3

C17

8.2p

TOKO LL2012

27NJ

OUT

OUT_GND

5
6

Figure 4. Input Matching Network without SAW Filter

fRF = 433.92 MHz

15p

25n

8

LNAGND

U3741BM

9

LNA_IN

fRF = 315 MHz

RF

IN

fRF = 315 MHz

33p

C3

47p

TOKO LL2012

C2

10p

L2

F82NJ

82n12

25n

L

25n

IN
IN_GND

8

LNAGND

U3741BM

9

LNA_IN

8

LNAGND

U3741BM

9

LNA_IN

C16

100p

L3

47n

B3551

CASE_GND

3, 4

TOKO LL2012

OUT_GND

7, 8

C17

22p

F47NJ

OUT

5
6

RF

RF

IN

3.3p
22n

100p

TOKO LL2012

F22NJ

IN

3.3p
39n

100p

TOKO LL2012

F39NJ

Please note that for all coupling conditions (see Figure 3 and Figure 4), the bond wire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit
together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its
value is not critical but must be large enough not to detune the series resonance circuit.
For cost reduction, this inductor can be easily printed on the PCB. This configuration
improves the sensitivity of the receiver by about 1 dB to 2 dB.

6

U3741BM

4662B–RKE–10/04

U3741BM

Analog Signal Processing

IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f

= 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine

f

RF

= 1 MHz for applications where f

IF

the center frequency.
The U3741BM is available with 2 different IF bandwidths. U3741BM-M2, the version

with B

= 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter

IF

U2741B is used. The receiver U3741BM-M3 employs an IF bandwidth of B
This version can be used together with the U2741B in FSK and ASK mode. If used in
ASK applications, it allows higher tolerances for the receiver and PLL transmitter crys­tals. SAW transmitters exhibit much higher transmit frequency tolerances compared to
PLL transmitters. Generally, it is necessary to use B

= 600 kHz together with such

IF

transmitters.

RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

= 315 MHz or

RF

= 600 kHz.

IF

= 60 dB. If the

RSSI

In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage

VTh_red. VTh_red is determined by the value of the external resistor R

Sense

. R

Sense

is
connected between pin Sense and GND or VS. The output of the comparator is fed into
the digital control logic. By this means it is possible to operate the receiver at lower
sensitivity.

If R
sensitivity is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced

Sense

, the maximum sensitivity by the sig-

Sense

nal-to-noise ratio of the LNA input. The reduced sensitivity is dependent on the signal
strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 4 on page 6 and exhibits the best possi­ble sensitivity.

can be connected to VS or GND via a microcontroller or by the digital output port

R

Sense

POUT of the U3741BM receiver IC. The receiver can be switched from full sensitivity to
reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake
up if the RF input signal does not exceed the selected sensitivity. If the receiver is
already active, the data stream at pin DATA will disappear when the input signal is lower
than defined by the reduced sensitivity. Instead of the data stream, the pattern accord­ing to Figure 5 is issued at pin DATA to indicate that the receiver is still active.

Figure 5. Steady L State Limited DATA Output Pattern

4662B–RKE–10/04

DATA

t

min2

t

DATA_L_max

7

FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.
Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detec­tion reference voltage to a value where a good signal-to-noise ratio is achieved. This
circuit also implies the effective suppression of any kind of in-band noise signals or com­peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected
properly.

The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower
values may be used but the sensitivity of the receiver is reduced in that condition. The
minimum usable deviation is dependent on the selected baud rate. In FSK mode, only
BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be
detected if the S/N Ratio exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its bandpass
can be adopted to the characteristics of the data signal. The data filter consists of a
1st-order high-pass and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to
pin CDEM. The cut-off frequency of the high-pass filter is defined by the following for­mula:

f

cu_DF

In self-polling mode, the data filter must settle very rapidly to achieve a low current con­sumption. Therefore, CDEM cannot be increased to very high values if self polling is
used. On the other hand, CDEM must be large enough to meet the data filter require­ments according to the data signal. Recommended values for CDEM are given in the
“Electrical Characteristics” on page 23. The values are slightly different for ASK and
FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu­ration of the Receiver” on page 17). BR_Range must be set in accordance to the used
baud rate.

The U3741BM is designed to operate with data coding where the DC level of the data
signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of
VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB
in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(tee_sig). These limits are defined in the “Electrical Characteristics” on page 23. They
should not be exceeded to maintain full sensitivity of the receiver.

------------ ------------ ------------- ----------- -------------=

2 π× 30 kΩ× CDEM×

1

8

U3741BM

4662B–RKE–10/04

U3741BM

Receiving Characteristics

The RF receiver U3741BM can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front end-filter is illustrated in Figure 6. This example
relates to ASK mode and the 300-kHz bandwidth version of the U3741BM. FSK mode
and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror fre­quency is reduced by 40 dB. The plots are printed relative to the maximum sensitivity. If
a SAW filter is used, an insertion loss of about 4 dB must be considered.

When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal­culated to be the sum of the deviation of the crystal and the XTO deviation of the
U3741BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of
the U3741BM is an additional deviation due to the XTO circuit. This deviation is speci­fied to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in
that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.

Figure 6. Receiving Frequency Response

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

dP (dB)

-70.0

-80.0

-90.0

-100.0

-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

df (MHz)

without SAW

with SAW

4662B–RKE–10/04

9

Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro­controller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the con­nected microcontroller, it can be operated by up to three uni-directional ports.

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 7, this clock cycle T

is derived from the crystal oscillator

Clk

(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys­tal oscillator (f

) is defined by the RF input signal (f

XTO

operating frequency of the local oscillator (f

LO

).

) which also defines the

RFin

Figure 7. Generation of the Basic Clock Cycle

T

Clk

Divider
:14/:10

f

XTO

XTO

Pin MODE can now be set in accordance with the desired clock cycle T

MODE

16

DVCC

15

XTO

14

L : USA (:10)
H: Europe (:14)

Clk

. T

controls

Clk

the following application-relevant parameters:

• Timing of the polling circuit including bit check

• Timing of analog and digital signal processing

• Timing of register programming

• Frequency of the reset marker

• F filter center frequency (f
Most applications are dominated by two transmission frequencies: f

mainly used in the USA, f

-dependent parameters, the electrical characteristics display three conditions for

T

Clk

Send

)

IF0

= 315 MHz is

Send

= 433.92 MHz in Europe. In order to ease the usage of all

each parameter.

10

U3741BM

4662B–RKE–10/04

U3741BM

• USA Applications

(f

= 4.90625 MHz, MODE = L, T

XTO

• Europe Applications

(f

= 6.76438 MHz, MODE = H, T

XTO

• Other applications

(T

is dependent on f

Clk

and on the logical state of pin MODE. The electrical

XTO

characteristic is given as a function of T

The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T
by the following formulas for further reference:

= 2.0383 µs)

Clk

= 2.0697 µs)

Clk

).

Clk

is defined

XClk

T
T
T

XClk

XClk

XClk

XClk

= 8 × T
= 4 × T
= 2 × T
= 1 × T

Clk

Clk

Clk

Clk

BR_Range = BR_Range0: T

BR_Range1:
BR_Range2:
BR_Range3:

Polling Mode According to Figure 3 on page 6, the receiver stays in polling mode in a continuous

cycle of three different modes. In sleep mode, the signal processing circuitry is disabled
for the time period T
period, T

, all signal processing circuits are enabled and settled. In the following bit

Startup

while consuming a low current of IS = I

Sleep

check mode, the incoming data stream is analyzed bit by bit against a valid transmitter
signal. If no valid signal is present, the receiver is set back to sleep mode after the
period T
age value for T
and T

Bitcheck

. This period varies check by check as it is a statistical process. An aver-

Bitcheck

the current consumption is IS = I

is given in “Electrical Characteristics” on page 23. During T

Bitcheck

. The average current consumption in

Son

polling mode is dependent on the duty cycle of the active mode and can be calculated
as:

I

Spoll

During T

I

SoffTSleepISonTStartupTBitcheck

------------ ------------- ------------- ----------- ------------ ------------- ------------- ------------- --------=

T

++

SleepTStartupTBitcheck

Sleep

and T

, the receiver is not sensitive to a transmitter signal. To guaran-

Startup

+()×+×

tee the reception of a transmitted command, the transmitter must start the telegram with
an adequate preburst. The required length of the preburst is dependent on the polling
parameters T

Start,µC

). T

Bitcheck

(T

, T

Sleep

thus depends on the actual bit rate and the number of bits (N

Startup

, T

and the startup time of a connected microcontroller

Bitcheck

be tested.

. During the start-up

Soff

Bitcheck

Startup

) to

The following formula indicates how to calculate the preburst length.
T

Preburst

≥ T

Sleep

+ T

Startup

Sleep Mode The length of period T

the extension factor X

. It is calculated to be:

T

Clk

T

Sleep

Sleep X

× 1024× T

Sleep

In US and European applications, the maximum value of T
set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended
to almost half a second by setting X

resulting in a different mode of action as described below:

4662B–RKE–10/04

bit X

SleepTemp

+ T

is defined by the 5-bit word Sleep of the OPMODE register,

Sleep

, according to Figure 10 on page 13, and the basic clock cycle

Sleep

Bitcheck

×=

Clk

+ T

Sleep

Start_µC

to 8. X

is about 60 ms if X

Sleep

can be set to 8 by bit X

Sleep

SleepStd

is

Sleep

or by

11

Figure 8. Polling Mode Flow Chart

Sleep Mode:

All circuits for signal processing are
disabled. Only XTO and polling logic is
enabled.
Output level on pin IC_ACTIVE => low
I

= I

S

SON

T

= Sleep × X

Sleep

Start-up Mode:

The signal processing circuits are
enabled. After the start-up time (T
circuits are in stable condition and ready
to receive.
I

= I

S

SON

T

Startup

Bit-check Mode:

The incomming data stream is analyzed.
If the timing indicates a valid transmitter
signal, the receiver is set to receiving
mode. Otherwise it is set to Sleep mode.
I

= I

S

Son

T

Bit-check

NO

X
X

= 1 implies the standard extension factor. The sleep time is always extended.

SleepStd

SleepTemp

= 1 implies the temporary extension factor. The extended sleep time is used
as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto­matically resulting in a regular sleep time. This functionality can be used to save current
in presence of a modulated disturber similar to an expected transmitter signal. The con­nected microcontroller is rarely activated in that condition. If the disturber disappears,
the receiver switches back to regular polling and is again sensitive to appropriate trans­mitter signals.

According to Table 7 on page 19, the highest register value of Sleep sets the receiver to
a permanent sleep condition. The receiver remains in that condition until another value
for Sleep is programmed into the OPMODE register. This function is desirable where
several devices share a single data line.

× 1024 × T

Sleep

Bit-check

OK?

Clk

Startup

) all

Sleep: 5-bit word defined by Sleep0 to Sleep4 in

X

Sleep

T

Clk

T

Startup

T

Bit-check

OPMODE register

: Extension factor defined by X

according to Table 8

: Basic clock cycle defined by f

MODE

SleepTemp

and pin

XTO

: Is defined by the selected baud rate range

and T

. The baud-rate range is defined

Clk

by Baud0 and Baud1 in the OPMODE
register.

: Depends on the result of the bit check.

If the bit check is ok, T
on the number of bits to be checked
(N

) and on the utilized data rate.

Bit-checked

Bit-check

depends

If the bit check fails, the average time
period for that check depends on the
selected baud-rate range on T
baud-rate range is defined by Baud0 and

Clk

. The

Baud1 in the OPMODE register.

12

Receiving Mode:

The receiver is turned on permanently
and passes the data stream to the
connected microcontroller. It can be set to
Sleep mode through an OFF command
via pin DATA or ENABLE
I

= I

S

SON

U3741BM

YES

OFF command

4662B–RKE–10/04

Figure 9. Timing Diagram for a Completely Successful Bit Check

U3741BM

Number of Checked Bits: 3

Enable IC

Bit check

Dem_out

DATA

Polling mode

1/2 Bit

1/2 Bit

Bit check ok

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Receiving mode

Bit Check Mode In bit check mode, the incoming data stream is examined to distinguish between a valid

signal from a corresponding transmitter and signals due to noise. This is done by subse­quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of this edge-to-edge
test, before the receiver switches to receiving, mode is also programmable.

Configuring the Bit Check Assuming a modulation scheme that contains 2 edges per bit, two time frame checks

are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to the receiving mode due to noise. In the presence of a valid transmitter signal,
the bit check takes less time if N
check time is not dependent on N
tested successfully and the data signal is transferred to pin DATA.

in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge

Bitcheck

is set to a higher value, the receiver is less likely to

Bitcheck

is set to a lower value. In polling mode, the bit

Bitcheck

. Figure 9 shows an example where 3 bits are

Bitcheck

According to Figure 10, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit check limit T
T

Lim_min

or tee exceeds T

Lim_max

Lim_max

, the bit check will be terminated and the receiver

is in between the lower bit check limit T

ee

, the check will be continued. If tee is smaller than

Lim_min

and

switches to sleep mode.

Figure 10. Valid Time Window for Bit Check

1/f

Sig

Dem_out

For best noise immunity it is recommended to use a low span between T
T

. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

Lim_max

t

T

lim_min

T

lim_max

ee

and

Lim_min

preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good
choice in this regard. A good compromise between receiver sensitivity and susceptibility
to noise is a time window of ±25% regarding the expected edge-to-edge time t

. Using

ee

preburst patterns that contain various edge-to-edge time periods, the bit check limits
must be programmed according to the required span.

4662B–RKE–10/04

13

The bit check limits are determined by means of the formula below:
T

T

= Lim_min × T

Lim_min

= (Lim_max –1) × T

Lim_max

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the

required T

Lim_max

is T

T
according to the section “Receiving Mode” on page 15. Due to this, the lower limit
should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63.

Figure 11, Figure 12 and Figure 13 on page 15 illustrate the bit check for the default bit
check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal pro­cessing circuits are enabled during T
(Dem_out) is undefined during that period. When the bit check becomes active, the bit
check counter is clocked with the cycle T

Figure 11 shows how the bit check proceeds if the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 12, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 13 on page 15.

Figure 11. Timing Diagram During Bit Check

(Lim_min = 14, Lim_max = 24)

Enable IC

T

Bit check

Dem_out

Startup

XClk

XClk

, T

Lim_min

XClk

Lim_max

. The minimum edge-to-edge time tee (t

and T

1/2 Bit

. The time resolution when defining T

XClk

Startup

XClk

Bit check ok

and

DATA_L_min

, t

DATA_H_min

Lim_min

) is defined

. The output of the ASK/FSK demodulator

.

Bit check ok

1/2 Bit 1/2 Bit

Bit check
Counter

0

234 5

1

245

81 3 6789 111213 1410

7

6

T

XClk

16 17

15

18 1

Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Bit check
Counter

0

Startup Mode

6 2451 1 36789

2345

Bit check Mode

Bit check failed ( CV_Lim < Lim_min )

1/2 Bit

10

1112

0

Sleep Mode

234

56

7 8 9 1011121314

15 1 2

34

14

U3741BM

4662B–RKE–10/04

Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

U3741BM

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Bit check
Counter

0

Startup Mode

2345

1

6 245

7 3678

1

Bit check Mode

1/2 Bit

9

13141516171819 21

111210

Bit check failed (CV_Lim = Lim_max)

24

2223

20

0

Sleep Mode

Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK

demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
Characteristics”. T
baudrate range causes a lower value for T

depends on the selected baud rate range and on T

Bitcheck

resulting in lower current consumption

Bitcheck

is given in “Electrical

Bitcheck

Bitcheck

. A higher

Clk

in polling mode.
In the presence of a valid transmitter signal, T

that signal, f
thereby results in a longer period for T
preburst T

and the count of the checked bits, N

Sig

Bitcheck

Preburst

.

requiring a higher value for the transmitter

Receiving Mode If the bit check has been successful for all bits specified by N

is dependant on the frequency of

Bitcheck

. A higher value for N

Bitcheck

Bitcheck

, the receiver

Bitcheck

switches to receiving mode. According to Figure 9 on page 13, the internal data signal is
switched to pin DATA in that case. A connected microcontroller can be woken up by the
negative edge at pin DATA. The receiver stays in that condition until it is switched back
to polling mode explicitly.

Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different

ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 14 on page 16 illustrates how
Dem_out is synchronized by the extended clock cycle T
the bit check counter. Data can change its state only after T
edge-to-edge time period t

XClk

.

of T

of the Data signal as a result is always an integral multiple

ee

. This clock is also used for

XClk

elapsed. The

XClk

The minimum time period between two edges of the data signal is limited to

≥ T

t

ee

DATA_min

. This implies an efficient suppression of spikes at the DATA output. At the
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T
ceding edge-to-edge time interval t

as illustrated in Figure 15. If tee is in between the

ee

DATA_min

is to some extent affected by the pre-

specified bit check limits, the following level is frozen for the time period
T

DATA_min

= tmin1, in case of tee being outside that bit check limits T

DATA_min

= tmin2 is the

relevant stable time period.
The maximum time period for DATA to be low is limited to T

DATA_L_max

. This function
ensures a finite response time during programming or switching off the receiver via pin
DATA. T

DATA_L_max

is thereby longer than the maximum time period indicated by the
transmitter data stream. Figure 16 gives an example where Dem_out remains low after
the receiver has switched to receiving mode.

4662B–RKE–10/04

15

Figure 14. Synchronization of the Demodulator Output

T

XClk

Clock Bitcheck
counter

Dem_out

DATA

t

ee

Figure 15. Debouncing of the Demodulator Output

Dem_out

DATA

tmin1Lim_min ≤ CV_Lim < Lim_max

t

ee

CV_Lim < Lim_min or CV_Lim ≥ Lim_max

t

ee

Figure 16. Steady L State Limited DATA Output Pattern after Transmission

Enable IC

Bit check

Dem_out

tmin2

DATA

Sleep mode

Switching the Receiver Back to Sleep Mode

16

U3741BM

Bit check mode

Receiving mode

tmin2

t

DATA_L_max

After the end of a data transmission, the receiver remains active and random noise
pulses appear at pin DATA. The edge-to-edge time period t
noise pulses is equal to or slightly higher than T

DATA_min

.

of the majority of these

ee

The receiver can be set back to polling mode via pin DATA or via pin ENABLE.
When using pin DATA, this pin must be pulled to low for the period t1 by the connected

microcontroller. Figure 17 illustrates the timing of the OFF command (see also Figure 21
on page 21). The minimum value of t1 depends on the BR_Range. The maximum value
for t1 is not limited but it is recommended not to exceed the specified value to prevent
erasing the reset marker. This item is explained in more detail in the section “Configura­tion of the Receiver” on page 17. Setting the receiver to sleep mode via DATA is
achieved by programming bit 1 of the OPMODE register to 1. Only one sync pulse (t3) is
issued.

The duration of the OFF command is determined by the sum of t1, t2 and t10. After the
OFF command, the sleep time T

elapses. Note that the capacitive load at pin DATA

Sleep

is limited. The resulting time constant τ together with an optional external pull-up resis­tor may not be exceeded to ensure proper operation.

4662B–RKE–10/04

U3741BM

If the receiver is set to polling mode via pin ENABLE, an ‘L’ pulse (T
at that pin. Figure 18 illustrates the timing of that command. After the positive edge of
this pulse, the sleep time T

Sleep

ENABLE is held to ‘L’. If the receiver is polled exclusively by a microcontroller, T
be programmed to 0 to enable a instantaneous response time. This command is the
faster option than via pin DATA at the cost of an additional connection to the
microcontroller.

Figure 17. Timing Diagram of the OFF Command Via Pin DATA

t1 t2 t3t4t5

t10

t7

Out1 (microcontroller)

DATA (U3741BM)

Serial bi-directional
data line

X

X

Receiver
on

OFF command

Bit 1
("1")

(Start bit)

) must be issued

Doze

elapses. The receiver remains in sleep mode as long as

can

Sleep

X

X

T

Sleep

Startup mode

Figure 18. Timing Diagram of the OFF Command Via Pin ENABLE

ENABLE

DATA (U3741BM)

Serial bi-directional

data line

Configuration of the Receiver

T

Doze

toff

X

X

Receiver on

The U3741BM receiver is configured via two 12-bit RAM registers called OPMODE and
LIMIT. The registers can be programmed by means of the bi-directional DATA port. If

T

Sleep

the register contents have changed due to a voltage drop, this condition is indicated by a
certain output pattern called reset marker (RM). The receiver must be reprogrammed in
that case. After a power-on reset (POR), the registers are set to default mode. If the
receiver is operated in default mode, there is no need to program the registers.

Table 3 on page 18 shows the structure of the registers. According to Table 2 on page
18, bit 1 defines if the receiver is set back to polling mode via the OFF command, (see
section “Receiving Mode” on page 15) or if it is programmed. Bit 2 represents the regis­ter address. It selects the appropriate register to be programmed.

X

X

Startup mode

4662B–RKE–10/04

17

Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers

Bit 1 Bit 2 Action

1 x The receiver is set back to polling mode (OFF command)
0 1 The OPMODE register is programmed
0 0 The LIMIT register is programmed

Table 4 and the following illustrate the effect of the individual configuration words. The
default configuration is highlighted for each word.

BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim
is used to define the bit check limits T

Lim_min

and T

as shown in Table 4.

Lim_max

POUT can be used to control the sensitivity of the receiver. In that application, POUT is
set to 1 to reduce the sensitivity. This implies that the receiver operates with full sensitiv­ity after a POR.

Table 3. Effect of the Configuration Words within the Registers

Bit1 Bit2 Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14

OFF Command

1

OPMODE Register

0 1 BR_Range N
0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X

(Default)001000101100

LIMIT Register

0 0 Lim_min Lim_max
0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0

(Default)001110011000

Bitcheck

V

POUT

Sleep X

Sleep StdXSleep Temp

Sleep

Table 4. Effect of the Configuration Word BR_Range

BR_Range

Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0

BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)

BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4

BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2

BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1

18

00

01

10

11

U3741BM

4662B–RKE–10/04

U3741BM

Table 5. Effect of the Configuration Word N

N

Bitcheck

Bitcheck

Number of Bits to be CheckedBitChk1 BitChk0

00 0
01 3
1 0 6 (Default)
11 9

Table 6. Effect of the Configuration Bit VPOUT

VPOUT Level of the Multi-purpose Output Port POUT

POUT

00 (Default)
11

Table 7. Effect of the Configuration Word Sleep

Sleep

Start Value for Sleep Counter (T

0 0 0 0 0 0 (Receiver is continuously polling until a valid signal occurs)
00001 1 (T

≈ 2ms for X

Sleep

Sleep

00010 2
00011 3

.
.
.

01011 11 (USA: T

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

= 22.96 ms, Europe: T

Sleep

.
.

.
11101 29
11110 30
1 1 1 1 1 31 (Permanent sleep mode)

= Sleep × X

Sleep

Sleep

= 1 in US-/European applications)

.
.
.

= 23.31 ms) (Default)

Sleep

.
.
.

× 1024 × T

Clk

)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0

Table 8. Effect of the Configuration Word X

X

Sleep

SleepStd

0 0 1 (Default)
01 8 (X
10 8 (X
11 8 (X

4662B–RKE–10/04

X

SleepTemp

Sleep

Extension Factor for Sleep Time (T

is reset to 1 if bit check fails once)

Sleep

is set permanently)

Sleep

is set permanently)

Sleep

= Sleep × X

Sleep

× 1024 × T

Sleep

Clk

)X

19

Table 9. Effect of the Configuration Word Lim_min

Lim_min Lower Limit Value for Bit Check

Lim_min < 10 is not applicable (T

= Lim_min × XLim × T

Lim_min

001010 10
001011 11
001100 12
001101 13

001110

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

(USA: T

Lim_min

14 (Default)

= 228 µs, Europe: T

111101 61
111110 62
111111 63

Table 10. Effect of the Configuration Word Lim_max

Lim_max Upper Limit Value for Bit Check

Lim_max < 12 is not applicable (T

001100 12
001101 13
001110 14

.
.
.

011000

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

.
.
.

(USA: T

.
.
.

.
.
.

.
.
.

.
.
.

.
.

.
111101 61
111110 62
111111 63

= (Lim_max - 1) × XLim × T

Lim_max

24 (Default)

= 375 µs, Europe: T

Lim_max

Lim_min

Lim_max

)

Clk

= 232 µs)

)

Clk

= 381 µs)

Conservation of the Register Information

20

U3741BM

The U3741BM has an integrated power-on reset and brown-out detection circuitry to
provide a mechanism to preserve the RAM register information.

According to Figure 19 on page 21, a power-on reset (POR) is generated if the supply
voltage V

drops below the threshold voltage V

S

grammed into the configuration registers in that condition. Once V
the POR is canceled after the minimum reset period t

. The default parameters are pro-

ThReset

. A POR is also generated when

Rst

exceeds V

S

ThReset

the supply voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a

reset. The RM is represented by the fixed frequency f

at a 50% duty cycle. RM can be

RM

canceled via an ‘L’ pulse t1 at pin DATA. The RM implies the following characteristics:

4662B–RKE–10/04

,

•fRM is lower than the lowest feasible frequency of a data signal. By this means, RM
cannot be misinterpreted by the connected microcontroller.

• If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by
accident if t1 is applied according to the proposal in the section
Configuration Register” on page 21.

By means of that mechanism, the receiver cannot lose its register information without
communicating that condition via the reset marker RM.

Figure 19. Generation of the Power-on Reset

V

S

POR

t

Rst

DATA (U3741BM)

X

V

ThReset

U3741BM

“Programming the

1/f

RM

Figure 20. Timing of the Register Programming

t1 t2 t3

Out1
(microcontroller)

DATA (U3741BM)

Serial bi-directional
data line

Programming the Configuration Register

X

X

Receiver
on

The configuration registers are programmed serially via the bi-directional data line
according to Figure 20 and Figure 21.

Figure 21. One-wire Connection to a Microcontroller

t5

t4

t6

t7

Bit 1
("0")

(Start bit) (Register select)

Bit 2
("1")

U3741BM

Internal pull-up

resistor

Programming Frame

Bit 13

("0")

(Poll8)

Bi-directional

data line

Bit 14

("1")

(Poll8R)

microcontroller

T

Sleep

t9

t8

X

X

Startup
mode

4662B–RKE–10/04

DATA I/O

Out 1 (µC)

DATA (U3741BM)

21

To start programming, the serial data line DATA is pulled to ‘L’ for the time period t1 by
the microcontroller. When DATA has been released, the receiver becomes the master
device. When the programming delay period t2 has elapsed, it emits 14 subsequent
synchronization pulses with the pulse length t3. After each of these pulses, a program­ming window occurs. The delay until the program window starts is determined by t4, the
duration is defined by t5. Within the programming window, the individual bits are set. If
the microcontroller pulls down pin DATA for the time period t7 during t5, the according
bit is set to ‘0’. If no programming pulse t7 is issued, this bit is set to ‘1’. All 14 bits are
subsequently programmed in this way. The time frame to program a bit is defined by t6.

Bit 14 is followed by the equivalent time window t9. During this window, the equivalent
acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to
the mode word that was already stored in that register. E_Ack should be used to verify
that the mode word was correctly transferred to the register. The register must be pro­grammed twice in that case.

Programming of a register is possible both during sleep and active mode of the receiver.
During programming, the LNA, LO, low-pass filter, IF-amplifier and the demodulator are

disabled.
The programming start pulse t1 initiates the programming of the configuration registers.

If bit 1 is set to ‘1’, it represents the OFF command to set the receiver back to polling
mode at the same time. For the length of the programming start pulse t1, the following
convention should be considered:

• t1(min) < t1 < 1535 × T

: [t1(min) is the minimum specified value for the relevant

Clk

BR_Range]

Programming (respectively OFF command) is initiated if the receiver is not in reset
mode. If the receiver is in reset mode, programming (respectively Off command) is not
initiated, and the reset marker RM is still present at pin DATA.

This period is generally used to switch the receiver to polling mode. In a reset condition,
RM is not canceled by accident.

• t1 > 5632 × T

Clk

Programming (respectively OFF command) is initiated in any case. RM is cancelled if
present. This period is used if the connected microcontroller detected RM. If a configura­tion register is programmed, this time period for t1 can generally be used.

Note that the capacitive load at pin DATA is limited. The resulting time constant t
together with an optional external pull-up resistor may not be exceeded to ensure proper
operation.

22

U3741BM

4662B–RKE–10/04

U3741BM

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Max. Unit

Supply voltage V
Power dissipation P
Junction temperature T
Storage temperature T
Ambient temperature T
Maximum input level, input matched to 50 W P

S

tot

j

stg

amb

in_max

-55 +125 °C

-40 +105 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

thJA

100 K/W

6V
450 mW
150 °C

10 dBm

Electrical Characteristics

All parameters refer to GND, T
(V

= 5 V, T

S

Parameter Test Condition Symbol
Basic Clock Cycle of the Digital Circuitry

Basic clock
cycle

Extended
basic clock
cycle

Polling Mode

Sleep time

Start-up time

Time for Bit
Check

= 25°C)

amb

MODE = 0 (USA)
MODE = 1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

Sleep and X
defined in the
OPMODE register

BR_Range0
BR_Range1
BR_Range2
BR_Range3

Average bit check
time while polling
BR_Range0
BR_Range1
BR_Range2
BR_Range3

Bit check time for a
valid input signal f
N

= 0

Bitcheck

= 3

N

Bitcheck

N

= 6

Bitcheck

= 9

N

Bitcheck

Sleep

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

T

Clk

T

XClk

are

T

Sleep

T

Startup

T

Bitcheck

Sig

T

Bitcheck

6.76438-Mhz Osc.
(Mode 1)

2.0697

16.6

8.3

4.1

2.1

Sleep ×

X

Sleep

1024

2.0697
1855

1061
1061

663

0.45

0.24

0.14

0.14

3/f

Sig

6/f

Sig

9/f

Sig

×
×

3.5/f

6.5/f

9.5/f

4.90625-Mhz Osc.

3/f

Sig

Sig

6/f

Sig

Sig

9/f

Sig

Sig

(Mode 0) Variable Oscillator

/10)

1/(f

2.0383

16.3

8.2

4.1

2.0

Sleep

X

Sleep

1024

2.0383
1827

1045
1045

653

×

×

×

1/(f

8
4 × T
2 ×T
1 × T

Sleep
X

1024

320.5

XTO
XTO

× T

Sleep

× T

896.5

512.5

512.5

× T

/14)

Clk
Clk

Clk

Clk

×

×

Clk

Clk

0.47

0.26

0.16

0.15

3.5/f

Sig

6.5/f

Sig

9.5/f

Sig

T

3.5/f

6.5/f

9.5/f

XClk

Sig
Sig
Sig

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs
µs

µs
µs
µs
µs

ms

µs
µs
µs
µs

ms
ms
ms
ms

ms
ms
ms
ms

4662B–RKE–10/04

23

Electrical Characteristics (Continued)

All parameters refer to GND, T

= 5 V, T

(V

S

Parameter Test Condition Symbol
Receiving Mode

Intermediate
frequency

Baud rate
range

Minimum time
period
between
edges at
pin DATA
(Figure 15)

Maximum low
period at DATA
(Figure 16)

OFF
command at
pin ENABLE
(Figure 18)

Configuration of the Receiver

Frequency of
the reset
marker
(Figure 19)

Programming
start pulse
(Figure 17,
Figure 20)

Programming
delay period
(Figure 17,
Figure 20)

Synchroni­zation pulse
(Figure 17,
Figure 20)

= 25°C)

amb

MODE=0 (USA)
MODE=1 (Europe)

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range0

BR_Range1

BR_Range2

BR_Range3

BR_Range0
BR_Range1
BR_Range2
BR_Range3

BR_Range0

BR_Range1

BR_Range2

BR_Range3

after POR

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

6.76438-Mhz Osc.
(Mode 1)

f

IF

1.0 1.0

1.0

BR_Range

1.8

3.2

5.6

T

DATA _min

tmin1
tmin2
tmin1
tmin2
tmin1
tmin2
tmin1
tmin2

149
182

75
91

37.3

45.5

18.6

22.8

2169

T

DATA_L_max

1085

542
271

t

Doze

f

RM

3.1 3.05

117.9 119.8 Hz

2188

1104

t1

561

290

11656

t2 795 798 783 786

t3 265 261 128 × T

1.8

3.2

5.6

10.0

3176

3176

3176

3176

4.90625-Mhz Osc.
(Mode 0) Variable Oscillator

1.0

1.8

3.2

5.6

1.8

3.2

5.6

10.0

BR_Range0 × 2 µs/T
BR_Range1 × 2 µs/T
BR_Range2 × 2 µs/T
BR_Range3 × 2 µs/T

147
179

73
90

36.7

44.8

18.3

22.4

2136
1068

534
267

1.5 ¥
T

Clk

2155

1087

553

286

11479

3128

3128

3128

3128

1057 ×

T

Clk

533 ×

T

Clk

271 ×

T

Clk

140 ×

T

Clk

5632 ×

T

Clk

384.5 ×

T

Clk

f

× 64/314

XTO

× 64/432.92

f

XTO

9 × T

XClk

11 × T

9 × T

XClk

11 × T

9 × T

XClk

11 × T

9 × T

XClk

11 × T

131 × T
131 × T
131 × T
131 × T

1

------------- ------------- -------

×

4096 T

XCl

XClk

XClk

XClk

XClk
XClk
XClk
XClk

Clk

CLK

Clk
Clk
Clk
Clk

1535 ×

T

Clk

1535 ×

T

Clk

1535 ×

T

Clk

1535 ×

T

Clk

385.5

× T

Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

MHz
MHz

kBaud
kBaud
kBaud
kBaud

µs
µs
µs
µs
µs
µs
µs
µs

µs
µs
µs
µs

µs

µs

µs

µs

24

U3741BM

4662B–RKE–10/04

Electrical Characteristics (Continued)

All parameters refer to GND, T

= 5 V, T

(V

S

Parameter Test Condition Symbol

Delay until the
program
window starts
(Figure 17,
Figure 20)

Programming
window
(Figure 17,
Figure 20)

Time frame
of a bit
(Figure 20)

Programming
pulse (Figure
17, Figure 20)

Equivalent
acknowledge
pulse: E_Ack
(Figure 20)

Equivalent
time window
(Figure 20)

OFF-bit
programming
window
(Figure 17)

amb

= 25°C)

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

6.76438-Mhz Osc.
(Mode 1)

t4 131 129 63.5 × T

t5 530 522 256 × T

t6 1060 1044 512 × T

t7 133 529 131 521

t8 265 261 128 × T

t9 534 526 258 × T

t10 930 916 449.5 × T

4.90625-Mhz Osc.
(Mode 0) Variable Oscillator

64 ×

T

Clk

U3741BM

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Clk

µs

µs

µs

µs

µs

µs

µs

Clk

Clk

Clk

256 ×

T

Clk

Clk

Clk

Electrical Characteristics

All parameters refer to GND, T
(V

= 5 V, T

S

amb

= 25°C)

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Current consumption

LNA Mixer

Third-order intercept point

LO spurious emission at RF

Noise figure LNA and mixer (DSB) Input matching according to Figure 4 NF 7 dB

LNA_IN input impedance

1 dB compression point (LNA, mixer, IF
amplifier)

4662B–RKE–10/04

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Sleep mode
(XTO and polling logic active)

IS

off

190 350 µA

IC active
(startup-, bit check-, receiving mode)

IS

on

7.0 8.6 mA

pin DATA = H

LNA/mixer/IF amplifier
input matched according to Figure 4

In

Input matched according to Figure 4,
required according to I-ETS 300220

at 433.92 MHz
at 315 MHz

Input matched according to Figure 4,
referred to RF

in

IIP3 -28 dBm

IS

Zi

IP

LORF

LNA_IN

1db

-73 -57 dBm

1.0 || 1.56

1.3 || 1.0

-40 dBm

kΩ || pF
kΩ || pF

25

Electrical Characteristics (Continued)

All parameters refer to GND, T
(V

S

= 5 V, T

amb

= 25°C)

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Maximum input level

Local Oscillator

Operating frequency range VCO f

Phase noise VCO/LO

Spurious of the VCO at ±f
VCO gain K

Loop bandwidth of the PLL

Capacitive load at pin LF

XTO operating frequency

Series resonance resistor of the crystal

Static capacitance of the crystal C

Analog Signal Processing

Input sensitivity ASK 300-kHz IF filter

Input sensitivity ASK 300-kHz IF filter BR_Range0 -109 -111 -113 dBm
Input sensitivity ASK 300-kHz IF filter BR_Range1 -107 -109 -111 dBm
Input sensitivity ASK 300-kHz IF filter BR_Range2 -106 -108 -110 dBm
Input sensitivity ASK 300-kHz IF filter BR_Range3 -104 -106 -108 dBm

Input sensitivity ASK 600 kHz IF filter

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Input matched according to Figure 4,
BER ≤ 10-3,
ASK mode

f

= 432.92 MHz

osc

at 1 MHz
at 10 MHz

XTO

P

in_max

VCO

299 449 MHz

L (fm) -93

-113

-55 -47 dBC

VCO

190 MHz/V

-28

-20

-90

-110

dBC/Hz
dBC/Hz

For best LO noise
(design parameter)
R1 = 820 Ω

B

Loop

100 kHz

C9 = 4.7 nF
C10 = 1 nF

The capacitive load at pin LF is limited
if bit check is used. The limitation

C

LF_tot

10 nF

therefore also applies to self polling.
XTO crystal frequency,

appropriate load capacitance must be
connected to XTAL

6.764375 MHz

4.90625 MHz

f

= 6.764 MHz

XTO

4.906 MHz

f

XTO

R

xto

S

6.764375

-30 ppm

4.90625

-30 ppm

6.764375

4.90625

6.764375
+30 ppm

4.90625

+30 ppm

150
220

6.5 pF

Input matched according to Figure 4
ASK (level of carrier)
BER ≤ 10-3, B = 300 kHz
fin = 433.92 MHz/315 MHz

P

Ref_ASK

T = 25°C, VS = 5 V
fIF = 1 MHz

Input matched according to Figure 4
ASK (level of carrier)
BER ≤ 10
f

in

T = 25°C, V
f

IF

-3

, B = 600 kHz

= 433.92 MHz/315 MHz

= 5 V

S

= 1 MHz

P

Ref_ASK

dBm
dBm

MHz

MHz

Ω
Ω

26

U3741BM

4662B–RKE–10/04

U3741BM

Electrical Characteristics (Continued)

All parameters refer to GND, T
(V

S

= 5 V, T

amb

= 25°C)

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Input sensitivity ASK 600 kHz IF filter BR_Range0 -108 -110 -112 dBm
Input sensitivity ASK 600 kHz IF filter BR_Range1 -106.5 -108.5 -110.5 dBm
Input sensitivity ASK 600 kHz IF filter BR_Range2 -106 -108 -110 dBm
Input sensitivity ASK 600 kHz IF filter BR_Range3 -104 -106 -108 dBm

Sensitivity variation ASK for the full
operating range compared to

T

= 25°C, VS = 5 V

amb

Sensitivity variation ASK for full
operating range including IF filter
compared to T

= 25°C, VS = 5 V

amb

Sensitivity variation ASK for full
operating range including IF filter
compared to T

= 25°C, VS = 5 V

amb

Input sensitivity FSK 600 kHz IF filter

Input sensitivity FSK 600 kHz IF filter

Input sensitivity FSK 600 kHz IF filter

Sensitivity variation FSK for the full
operating range compared to

= 25°C, VS = 5 V

T

amb

Sensitivity variation FSK for full
operating range including IF filter
compared to T

= 25°C, VS = 5 V

amb

FSK frequency deviation

S/N ratio to suppress inband noise
signals

Dynamic range RSSI ampl. ∆R

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

300-kHz and 600-kHz version
f

= 433.92 MHz/315 MHz

in

= 1 MHz

f

IF

= P

P

ASK

Ref_ASK

+ ∆P

Ref

∆P

Ref

+2.5 -1.5 dB

300-kHz version
f

= 433.92 MHz/315 MHz

in

= 0.88 MHz to 1.12 MHz

f

IF

= 0.85 MHz to 1.15 MHz

f

IF

P

ASK

= P

Ref_ASK

+ ∆P

Ref

∆P

Ref

+5.5
+7.5

-1.5

-1.5

600-kHz version

= 433.92 MHz/315 MHz

f

in

= 0.79 MHz to 1.21 MHz

f

IF

f

= 0.73 MHz to 1.27 MHz

IF

= P

P

ASK

Input matched according to Figure 4,
BER ≤ 10
f

= 433.92 MHz/315 MHz

in

T = 25°C, V

= 1 MHz

f

IF

+ ∆P

Ref_ASK

-3

, B = 600 kHz

= 5 V

S

Ref

∆P

P

Ref_FSK

Ref

+5.5
+7.5

-1.5

-1.5

BR_Range0
df ≥ ±20 kHz
df ≥ ±30 kHz

-95.5

-96.5

-97.5

-98.5

-99.5

-100.5

BR_Range1
df ≥ ±20 kHz
df ≥ ±30 kHz

-94.5

-95.5

-96.5

-97.5

-98.5

-99.5

600-kHz version
f

= 433.92 MHz/315 MHz

in

= 1 MHz

f

IF

= P

P

FSK

Ref_FSK

+ ∆P

Ref

∆P

Ref

+2.5 -1.5 dB

600-kHz version
f

= 433.92 MHz/315 MHz

in

= 0.86 MHz to 1.14 MHz

f

IF

= 0.82 MHz to 1.18 MHz

f

IF

P

FSK

= P

Ref_FSK

+ ∆P

Ref

∆P

Ref

+5.5
+7.5

-1.5

-1.5

The sensitivity of the receiver is higher
for higher values of ∆f
BR_Range0
BR_Range1

FSK

∆f

FSK

20
20

30
30

50

50
BR_Range2 and BR_Range3 are not
suitable for FSK operation

ASK mode
FSK mode

SNR
SNR

ASK

FSK

RSSI

10

12

2

3

60 dB

dB
dB

dB
dB

dBm
dBm

dBm
dBm

dB
dB

kHz
kHz

dB
dB

4662B–RKE–10/04

27

Electrical Characteristics (Continued)

All parameters refer to GND, T
(V

S

= 5 V, T

amb

= 25°C)

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Lower cut-off frequency of the data
filter

Recommended CDEM for best
performance

Recommended CDEM for best
performance

Maximum edge-to-edge time period of
the input data signal for full sensitivity

Upper cut-off frequency data filter

Minimum edge-to-edge time period of
the input data signal for full sensitivity

Reduced sensitivity

Reduced sensitivity

Reduced sensitivity

Reduced sensitivity

Reduced sensitivity

Reduced sensitivity variation over full
operating range

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

f

cu_DF

------------ ------------- ------------- ----------- ----------=

2 π× 30kΩ× CDEM×

1

f

cu_DF

0.11 0.16 0.20 kHz

ASK mode
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

CDEM

39
22
12

8.2

FSK mode
BR_Range0 (Default)
BR_Range1
BR_Range2 and BR_Range3 are not

CDEM 27

15

suitable for FSK operation
BR_Range0 (Default)

BR_Range1
BR_Range2
BR_Range3

t

ee_sig

1000

560
320
180

Upper cut-off frequency programmable
in 4 ranges via
BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

BR_Range0 (Default)
BR_Range1
BR_Range2
BR_Range3

R

connected from pin Sens to VS,

Sense

input matched according to Figure 4

R

= 56 kΩ, f

Sense

= 5 V, T

(V

S

at B = 300 kHz
at B = 600 kHz

R

= 100 kΩ, fin = 433.92 MHz

Sense

at B = 300 kHz
at B = 600 kHz

R

= 56 kΩ, fin = 315 MHz

Sense

at B = 300 kHz
at B = 600 kHz

R

= 100 kΩ, fin = 315 MHz

Sense

at B = 300 kHz
at B = 600 kHz

R

= 56 kΩ

Sense

= 100 kΩ

R

Sense

P

= P

Red

a serial mode word

= 433.92 MHz,

in

= 25°C)

amb

+ DP

Ref_Red

Red

f

u

2.5

4.3

7.6

13.6

3.1

5.4

9.5

17.0

3.7

6.5

11.4

20.4
270

t

ee_sig

156

89
50

P

Ref_Red

∆P

Red

-71

-67

-80

-76

-72

-68

-81

-77
5

6

-76

-72

-85

-81

-77

-73

-86

-82
0

0

-81

-77

-90

-86

-82

-78

-91

-87
0

0

(peak

nF
nF
nF
nF

nF
nF

µs
µs
µs
µs

kHz
kHz
kHz
kHz

µs
µs
µs
µs

dBm

level)

dBm
dBm

dBm
dBm

dBm
dBm

dBm
dBm

dB
dB

28

U3741BM

4662B–RKE–10/04

U3741BM

Electrical Characteristics (Continued)

All parameters refer to GND, T
(V

S

= 5 V, T

amb

= 25°C)

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Reduced sensitivity variation for
different values of R

Sense

Threshold voltage for reset V

Digital Ports

Data output

- Saturation voltage LOW

- Internal pull-up resistor

- Maximum time constant

- Maximum capacitive load
POUT output

- Saturation voltage LOW

- Saturation voltage HIGH
FSK/ASK input

- Low-level input voltage

- High-level input voltage
ENABLE input

- Low-level input voltage

- High-level input voltage
MODE input

- Low-level input voltage

- High-level input voltage
TEST input

- Low-level input voltage

= -40°C to +105°C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Values relative to
R

= 56 kΩ

Sense

= 56 kΩ

R

Sense

R

= 68 kΩ

Sense

= 82 kΩ

R

Sense

= 100 kΩ

R

Sense

R

= 120 kΩ

Sense

= 150 kΩ

R

Sense

= P

P

Red

Ref_Red

+ ∆P

Red

I

= 1 mA

ol

(R

//R

t = C

L

pup

Ext

)

without ext. pull-up resistor
R

= 5 kΩ

ext

∆P

Red

ThRESET

V

OI

R

Pup

τ

C

L

C

L

1.95 2.8 3.75 V

39

0

-3.5

-6.0

-9.0

-11.0

-13.5

0.08
50

0.3
61

2.5
41

540

I

POUT

I

POUT

= 1 mA
= -1 mA

V

Ol

V

Oh

VS - 0.3 V

V

S

0.08

- 0.14V

0.3 V

FSK selected
ASK selected

V

Il

V

Ih

0.8 × V

S

0.2 × V

S

Idle mode
Active mode

V

Il

V

Ih

0.8 × V

S

0.2 × V

S

Division factor = 10
Division factor = 14

Test input must always be set to LOW

V

Il

V

Ih

V

Il

0.8 × V

S

0.2 × V

0.2 × V

S

S

dB
dB
dB
dB
dB
dB

V

kΩ

µs
pF
pF

V

V
V

V
V

V
V

V

4662B–RKE–10/04

29

Ordering Information

Extended Type Number Package Remarks

U3741BM-P2FL SO20 2: IF bandwidth of 300 kHz, tube
U3741BM-P2FLG3 SO20 2: IF bandwidth of 300 kHz, taped and reeled
U3741BM-P3FL SO20 3: IF bandwidth of 600 kHz, tube
U3741BM-P3FLG3 SO20 3: IF bandwidth of 600 kHz, taped and reeled

Package Information

Package SO20

Dimensions in mm

0.4

1.27

20 11

12.95

12.70

11.43

0.25

0.10

2.35

technical drawings
according to DIN
specificatio ns

9.15

8.65

7.5

7.3

0.25

10.50

10.20

30

110

U3741BM

4662B–RKE–10/04

U3741BM

Revision History Please note that the following page numbers referred to in this section refer to the

specific revision mentioned, not to this document.

Changes from Rev. 4662A - 06/03 to Rev. 4662B - 10/04

1. Put datasheet in a new template.

2. Heading rows at Table “Absolute Maximum Ratings” added.

3. Table “Ordering Information” on page 30 changed.

4662B–RKE–10/04

31

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