Rainbow Electronics U3741BM User Manual

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self Polling with a Programmable Time

Frame Check

• Supply Voltage 4.5 V to 5.5 V

• Operating Temperature Range -40°C to 105°C

• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD 883 (4KV HBM) Except Pin POUT (2KV HBM)

• High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW

Front-end Filter

– Up to 40 dB is Thereby Achievable with Newer SAWs.

• Programmable Output Port for Sensitivity Selection or for Controlling External

Periphery

• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

• 2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

Description

The U3741BM is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL
RF transmitter U2741B. Its main applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in the frequency receiving
range of f
ments made below refer to 433.92-MHz and 315-MHz applications.

= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-

0

UHF ASK
Receiver IC

U3741BM

Rev. 4662B–RKE–10/04

System Block Diagram

1 Li cell

Encoder

ATARx9x

Keys

Block Diagram

UHF ASK/FSK

Remote control transmitter

U2741B

FSK/ASK

CDEM

AVCC

SENS

AGND

DGND

PLL

VCOXTO

Power

amp.

FSK/ASK-

Demodulator

and data filter

IF Amp

4th Order

Antenna

Limiter outRSSI

Antenna

DEMOD_OUT

Sensitivity
reduction

UHF ASK/FSK

Remote control receiver

U3741BM

Demod

Polling circuit

and

control logic

FE CLK

PLL XTO

VCOLNA

50 kΩ

V

S

Control

DATA

ENABLE

TEST

POUT

MODE

DVCC

1...3
µC

LPF

MIXVCC

LNAGND

LNA_IN

2

U3741BM

LNA

3 MHz

IF Amp

LPF

3 MHz

Standby logic

VCO XTO

f

÷ 64

LFGND

LFVCC

XTO

LF

4662B–RKE–10/04

Pin Configuration Figure 1. Pinning SO20

DATA

SENS

FSK/ASK

CDEM

AVCC
AGND
DGND

MIXVCC

LNAGND

LNA_IN

NC

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

ENABLE
TEST
POUT
MODE
DVCC
XTO
LFGND
LF
LFVCC

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor
2 FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK
3 CDEM Lower cut-off frequency data filter
4 AVCC Analog power supply
5 AGND Analog ground
6 DGND Digital ground
7 MIXVCC Power supply mixer
8 LNAGND High-frequency ground LNA and mixer

9LNA_INRF input
10 NC Not connected
11 LFVCC Power supply VCO
12 LF Loop filter
13 LFGND Ground VCO
14 XTO Crystal oscillator
15 DVCC Digital power supply
16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)
17 POUT Programmable output port
18 TEST Test pin, during operation at GND

Enables the polling mode

19 ENABLE

20 DATA Data output/configuration input

Low: polling mode off (sleep mode)
H: polling mode on (active mode)

U3741BM

4662B–RKE–10/04

3

RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input

signal into a 1-MHz IF signal. According to the block diagram, the front end consists of
an LNA (low noise amplifier), LO (local oscillator), a mixer and RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO
(crystal oscillator) generates the reference frequency f
oscillator) generates the drive voltage frequency f
the voltage at pin LF. f
to f

by the phase frequency detector. The current output of the phase frequency

XTO

is divided by a factor of 64. The divided frequency is compared

LO

LO

detector is connected to a passive loop filter and thereby generates the control voltage

for the VCO. By means of that configuration, VLF is controlled in a way that fLO/64 is

V

LF

equal to f

f

XTO

. If fLO is determined, f

XTO

f

LO

--------=

64

can be calculated using the following formula:

XTO

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys­tal. According to Figure 2, the crystal should be connected to GND via a capacitor CL.
The value of that capacitor is recommended by the crystal supplier. The value of CL
should be optimized for the individual board layout to achieve the exact value of f
hereby of f

. When designing the system in terms of receiving bandwidth, the accuracy

LO

of the crystal and XTO must be considered.

Figure 2. PLL Peripherals

V

S

DVCC

C

XTO

. The VCO (voltage-controlled

XTO

for the mixer. fLO is dependent on

and

XTO

L

LFGND

R1 = 820 Ω

C9 = 4.7 nF

LF

LFVCC

R1

V

S

C9

C10 = 1 nF

C10

The passive loop filter connected to pin LF is designed for a loop bandwidth of

= 100 kHz. This value for B

B

Loop

exhibits the best possible noise performance of the

Loop

LO. Figure 2 shows the appropriate loop filter components to achieve the desired loop
bandwidth. If the filter components are changed for any reason, please note that the
maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit
check may no longer be possible since f

cannot settle in time before the bit check

LO

starts to evaluate the incoming data stream. Therefore, self polling also does not work in
that case.

is determined by the RF input frequency fRF and the IF frequency fIF using the follow-

f

LO

ing formula:

f

LOfRFfIF

–=

4

U3741BM

4662B–RKE–10/04

U3741BM

To determine fLO, the construction of the IF filter must be considered at this point. The
nominal IF frequency is f
quencies, the filter is tuned by the crystal frequency f
fixed relation between f
described by the following formulas:

MODE 0 (USA) f

MODE 0 (Europe) f

IF

= 1 MHz. To achieve a good accuracy of the filter’s corner fre-

IF

and fLO that depends on the logic level at pin mode. This is

IF

f

LO

----------==

314

f

LO

------------- -----==

432.92

IF

. This means that there is a

XTO

The relation is designed to achieve the nominal IF frequency of f
applications. For applications where f
case of f
not equal to 1 MHz. f

= 433.92 MHz, the MODE must be set to ‘1’. For other RF frequencies, fIF is

RF

is then dependent on the logical level at pin MODE and on fRF.

IF

= 315 MHz, the MODE must be set to ‘0’. In the

RF

= 1 MHz for most

IF

Table 1 summarizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF

input pin LNA_IN. The input impedance of that pin is provided in the electrical parame­ters. The parasitic board inductances and capacitances also influence the input
matching. The RF receiver U3741BM exhibits its highest sensitivity at the best sig­nal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the
transformation network.

A good practice when designing the network is to start with power matching. From that
starting point, the values of the components can be varied to some extent to achieve the
best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of

= 40 dB can be achieved. There are SAWs available that exhibit a notch at

∆P

Ref

∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The
selectivity of the receiver is also improved by using a SAW. In typical automotive appli­cations, a SAW is used.

Figure 3 on page 6 shows a typical input matching network for f

= 433.92 MHz using a SAW. Figure 4 on page 6 illustrates an input matching to 50 Ω

f

RF

= 315 MHz and

RF

without a SAW. The input matching networks shown in Figure 4 are the reference net­works for the parameters given in the “Electrical Characteristics”.

Table 1. Calculation of LO and IF Frequency

Conditions Local Oscillator Frequency Intermediate Frequency

= 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz

f

RF

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

f

RF

300 MHz < fRF < 365 MHz, MODE = 0

365 MHz < f

4662B–RKE–10/04

< 450 MHz, MODE = 1

RF

f

LO

1

f

------------ ------------- ---= f

LO

1

1

----------+

314

f

RF

1

------------ ------+

432.92

f

RF

------------ -------= f

IF

IF

f

LO

----------=
314

f

LO

------------ ------=

432.92

5

Figure 3. Input Matching Network with SAW Filter

8

LNAGND

C3

22p

fRF = 433.92 MHz

C2

8.2p

TOKO LL2012

F33NJ

RF

IN

L2

33n

L

25n

1
2

IN
IN_GND

U3741BM

9

LNA_IN

C16

100p

27n

B3555

CASE_GND

3, 4 7, 8

L3

C17

8.2p

TOKO LL2012

27NJ

OUT

OUT_GND

5
6

Figure 4. Input Matching Network without SAW Filter

fRF = 433.92 MHz

15p

25n

8

LNAGND

U3741BM

9

LNA_IN

fRF = 315 MHz

RF

IN

fRF = 315 MHz

33p

C3

47p

TOKO LL2012

C2

10p

L2

F82NJ

82n12

25n

L

25n

IN
IN_GND

8

LNAGND

U3741BM

9

LNA_IN

8

LNAGND

U3741BM

9

LNA_IN

C16

100p

L3

47n

B3551

CASE_GND

3, 4

TOKO LL2012

OUT_GND

7, 8

C17

22p

F47NJ

OUT

5
6

RF

RF

IN

3.3p
22n

100p

TOKO LL2012

F22NJ

IN

3.3p
39n

100p

TOKO LL2012

F39NJ

Please note that for all coupling conditions (see Figure 3 and Figure 4), the bond wire
inductivity of the LNA ground is compensated. C3 forms a series resonance circuit
together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its
value is not critical but must be large enough not to detune the series resonance circuit.
For cost reduction, this inductor can be easily printed on the PCB. This configuration
improves the sensitivity of the receiver by about 1 dB to 2 dB.

6

U3741BM

4662B–RKE–10/04

U3741BM

Analog Signal Processing

IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f

= 433.92 MHz is used. For other RF input frequencies, refer to Table 1 to determine

f

RF

= 1 MHz for applications where f

IF

the center frequency.
The U3741BM is available with 2 different IF bandwidths. U3741BM-M2, the version

with B

= 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter

IF

U2741B is used. The receiver U3741BM-M3 employs an IF bandwidth of B
This version can be used together with the U2741B in FSK and ASK mode. If used in
ASK applications, it allows higher tolerances for the receiver and PLL transmitter crys­tals. SAW transmitters exhibit much higher transmit frequency tolerances compared to
PLL transmitters. Generally, it is necessary to use B

= 600 kHz together with such

IF

transmitters.

RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR
RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK
mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is
defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage
due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input
signal is about 60 dB higher compared to the RF input signal at full sensitivity.

= 315 MHz or

RF

= 600 kHz.

IF

= 60 dB. If the

RSSI

In FSK mode, the S/N ratio is not affected by the dynamic range of the RSSI amplifier.
The output voltage of the RSSI amplifier is internally compared to a threshold voltage

VTh_red. VTh_red is determined by the value of the external resistor R

Sense

. R

Sense

is
connected between pin Sense and GND or VS. The output of the comparator is fed into
the digital control logic. By this means it is possible to operate the receiver at lower
sensitivity.

If R
sensitivity is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced

Sense

, the maximum sensitivity by the sig-

Sense

nal-to-noise ratio of the LNA input. The reduced sensitivity is dependent on the signal
strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain,
the sensitivity values given in the electrical characteristics refer to a specific input
matching. This matching is illustrated in Figure 4 on page 6 and exhibits the best possi­ble sensitivity.

can be connected to VS or GND via a microcontroller or by the digital output port

R

Sense

POUT of the U3741BM receiver IC. The receiver can be switched from full sensitivity to
reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake
up if the RF input signal does not exceed the selected sensitivity. If the receiver is
already active, the data stream at pin DATA will disappear when the input signal is lower
than defined by the reduced sensitivity. Instead of the data stream, the pattern accord­ing to Figure 5 is issued at pin DATA to indicate that the receiver is still active.

Figure 5. Steady L State Limited DATA Output Pattern

4662B–RKE–10/04

DATA

t

min2

t

DATA_L_max

7

FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the
ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK.
Logic 'L' sets the demodulator to FSK, Logic 'H' sets it into ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detec­tion reference voltage to a value where a good signal-to-noise ratio is achieved. This
circuit also implies the effective suppression of any kind of in-band noise signals or com­peting transmitters. If the S/N ratio exceeds 10 dB, the data signal can be detected
properly.

The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower
values may be used but the sensitivity of the receiver is reduced in that condition. The
minimum usable deviation is dependent on the selected baud rate. In FSK mode, only
BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be
detected if the S/N Ratio exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the
digital signal processing circuit. The data filter improves the S/N ratio as its bandpass
can be adopted to the characteristics of the data signal. The data filter consists of a
1st-order high-pass and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to
pin CDEM. The cut-off frequency of the high-pass filter is defined by the following for­mula:

f

cu_DF

In self-polling mode, the data filter must settle very rapidly to achieve a low current con­sumption. Therefore, CDEM cannot be increased to very high values if self polling is
used. On the other hand, CDEM must be large enough to meet the data filter require­ments according to the data signal. Recommended values for CDEM are given in the
“Electrical Characteristics” on page 23. The values are slightly different for ASK and
FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range
(BR_Range). BR_Range is defined in the OPMODE register (refer to section “Configu­ration of the Receiver” on page 17). BR_Range must be set in accordance to the used
baud rate.

The U3741BM is designed to operate with data coding where the DC level of the data
signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain within the range of
VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB
in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time
(tee_sig). These limits are defined in the “Electrical Characteristics” on page 23. They
should not be exceeded to maintain full sensitivity of the receiver.

------------ ------------ ------------- ----------- -------------=

2 π× 30 kΩ× CDEM×

1

8

U3741BM

4662B–RKE–10/04

U3741BM

Receiving Characteristics

The RF receiver U3741BM can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity. The
selectivity with and without a SAW front end-filter is illustrated in Figure 6. This example
relates to ASK mode and the 300-kHz bandwidth version of the U3741BM. FSK mode
and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror fre­quency is reduced by 40 dB. The plots are printed relative to the maximum sensitivity. If
a SAW filter is used, an insertion loss of about 4 dB must be considered.

When designing the system in terms of receiving bandwidth, the LO deviation must be
considered as it also determines the IF center frequency. The total LO deviation is cal­culated to be the sum of the deviation of the crystal and the XTO deviation of the
U3741BM. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of
the U3741BM is an additional deviation due to the XTO circuit. This deviation is speci­fied to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in
that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.

Figure 6. Receiving Frequency Response

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

dP (dB)

-70.0

-80.0

-90.0

-100.0

-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

df (MHz)

without SAW

with SAW

4662B–RKE–10/04

9

Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while being sensitive to signals
from a corresponding transmitter. This is achieved via the polling circuit. This circuit
enables the signal path periodically for a short time. During this time the bit check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected the
receiver remains active and transfers the data to the connected microcontroller. If there
is no valid signal present, the receiver is in sleep mode most of the time resulting in low
current consumption. This condition is called polling mode. A connected microcontroller
is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected micro­controller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.

Regarding the number of connection wires to the microcontroller, the receiver is very
flexible. It can be either operated by a single bi-directional line to save ports to the con­nected microcontroller, it can be operated by up to three uni-directional ports.

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 7, this clock cycle T

is derived from the crystal oscillator

Clk

(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys­tal oscillator (f

) is defined by the RF input signal (f

XTO

operating frequency of the local oscillator (f

LO

).

) which also defines the

RFin

Figure 7. Generation of the Basic Clock Cycle

T

Clk

Divider
:14/:10

f

XTO

XTO

Pin MODE can now be set in accordance with the desired clock cycle T

MODE

16

DVCC

15

XTO

14

L : USA (:10)
H: Europe (:14)

Clk

. T

controls

Clk

the following application-relevant parameters:

• Timing of the polling circuit including bit check

• Timing of analog and digital signal processing

• Timing of register programming

• Frequency of the reset marker

• F filter center frequency (f
Most applications are dominated by two transmission frequencies: f

mainly used in the USA, f

-dependent parameters, the electrical characteristics display three conditions for

T

Clk

Send

)

IF0

= 315 MHz is

Send

= 433.92 MHz in Europe. In order to ease the usage of all

each parameter.

10

U3741BM

4662B–RKE–10/04