Rainbow Electronics TS81102G0 User Manual

Features

• Programmable DMUX Ratio:

– 1:4: Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX

• Parallel Output Mode

• 8-/10-bit

• ECL Differential Input Data

• DataReady or DataReady/2 Input Clock

• Input Clock Sampling Delay Adjust

• Single-ended Output Data:

– Adjustable Common Mode and Swing – Logic Threshold Reference Output – (ECL, PECL, TTL)

• Asynchronous Reset

• Synchronous Reset

• ADC + DMUX Multi-channel Applications:

– Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment

• Differential Data Ready Output

• Built-in Self Test (BIST)

• Dual Power Supply V

• Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)

• TBGA 240 (Cavity Down) Package

= -5V, VCC = +5V

DMUX 8-/10-bit 2 GHz 1:4/8

TS81102G0

Description

The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor, designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B.

The TS81102G0 uses an inn ovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency).

Rev. 2105C–BDC–11/03

Block Diagram

Figure 1. Block Diagram

Data Path Clock Path

SwiAdj

VplusDOut

VCC

even

master

latch

even

slave

latch

GND

VEE

DIODE

BIST

8/10

BIST

8/10

FS/8

mux

I[0..7/9]

odd

master

latch

odd

slave

latch

NbBit

NAP

RatioSel

DEMUXDelAdjCtrl

ClkInType

B 2

Phase control

ClkPar

shift register)

Port Selection Clock

ClkIn

delay

mux

Counter

(8 stage

FS/8

AsyncReset

SyncReset

(to be confirmed)

RstGen

Reset

Counter Status

RatioSel

ADCDelAdjCtrl

ADCDelAdjIn

delay

Latch Sel Even/Odd [1..8/10]

Data

Output

Clock

8/10

A[0..7/9]

C[0..7/9]

E[0..7/9]

G[0..7/9]

B[0..7/9]

D[0..7/9]

F[0..7/9]

RefA

RefC

RefE

RefG

RefB

RefD

Even Ports Odd Ports

TS81102G0

H[0..7/9]

RefF

RefH

DataReady generation

DR/DR

ADCDelAdjOut

2105C–BDC–11/03

TS81102G0

Internal Timing

This diagram corresponds to an established opera tion of the DMUX with Synchronous Reset.

Diagram

Figure 2. Internal Timing Diagram

500 ps min

N N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24

Data In

DR In = Fs

DR/2 In = Fs/2 = ClkPar

Master Even Latch

Master Odd Latch

Slave Even Latch

Slave Odd Latch

Synchronous reset = Fs/8

Internal reset pulse

Port Select A Port Select B Port Select C

N+1

N+1 N+31

N+1

N+25 N+26 N+27 N+28 N+29 N+30 N+31

N+24 N+26 N+28 N+30N+14 N+16 N+18 N+20 N+22N+6 N+8 N+10 N+12N N+2 N+4

N+3 N+5 N+7 N+9 N+11 N+13 N+15 N+17 N+19 N+21 N+23 N+25 N+27 N+29

N+2

N+4

N+6

N+8

N+10

N+12

N+14

N+16

N+18

N+20

N+22

N+24

N+26

N+3

N+5

N+7

N+9

N+11

N+13

N+15

N+17

N+19

N+21

N+23

N+25

N+27

N+28

N+30

N+29

Port Select D Port Select E

Port Select F Port Select G Port Select H

Latch Select A Latch Select B Latch Select C Latch Select D Latch Select E Latch Select F

Latch Select G

Latch Select H

A to H Port Out

A to H LatchOut

DROut

N N+8 N+16 N+24

N+1 N+9 N+17 N+25

N+2 N+10 N+18 N+26

N+3 N+11 N+19 N+27

N+4 N+12 N+20

N+5 N+13 N+21

N+6 N+14 N+22

N+7 N+15 N+23

N to N+7 N+8 to N+15 N+16 to N+23

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Functional Description

The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be processed at the DMUX output.

The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1 Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio.

The TS81102G0 is able to process 8 or 10-bit data flows. The input clock can be an ECL differential signal or single-ended DC cou pled signal. Mo reover

it can be a DataReady or DataReady/2 clock. The input digital data must be an ECL differential signal. The output signals (Data Ready, digital data and reference voltage) are adjustable with

VplusD independent power supply. Typical output modes are ECL, PECL or TTL. The Data Ready output is a differential signal. The digital output data and reference voltages

are single-ended signals. The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the

user to re-synchronize the output port selection and to minimize loss of data that could occur within the DMUX.

A delay adjust cell is available to ensure a good phase between the DMUX’ input clock and input data.

Another delay adjust cell is available to contro l the ADCss sampling instant alignment, in case of the ADCs interleaving.

A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test sequence is very useful for testing the DMUX at first use.

A fine tuning of the output swing is also available. The TS81102G0 can be used with the following Atmel ADCs:

• TS8388B(F/FS/GL), 8-bit 1 Gsps ADC

• TS83102G0B, 10-bit 2 Gsps ADC

TS81102G0

2105C–BDC–11/03

Main Function Description

TS81102G0

Programmable DMUX Ratio

The conversion ratio is programmable: 1:4 or 1:8. Figure 3. Programmable DMUX Ratio

Input Words:

1,2,3,4,5,6,7,8,...

1:4

Input Words:

1,2,3,4,5,6,7,8,...

1:8

Output Words: PortA

PortB PortC PortD PortE PortF PortG

PortH

Output Words: PortA

PortB PortC PortD PortE PortF PortG PortH

1 2 3

4 not used not used not used not used

1 2

3 4 5 6 7

5 6 7 8

9 10

11 12 13 14 15 16

...

Parallel Output Mode

Figure 4. Parallel Mode

ClkIn

DR PortA PortB PortC PortD PortE PortF

PortG PortH

Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL)

The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to ensure a proper phase between the clock and input data of the DMUX.

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N N+1 N+2 N+3 N+4 N+5 N+6 N+7

Asynchronous Reset (ASYNCRESET)

Figure 5. Asynchronous Reset

CLKIN

AsyncReset Port A selected Port B selected

Port C selected Port D selected

Port E selected Port F selected

Port G selected Port H selected

The Asynchronous Reset is a master reset of the port selection, which works on TTL levels. It is active on the high level. During an asynchronous reset, the clock must be in a known state. It is used to start the DMUX.

When it is active, it paralyzes the outputs (the out put clock and output d ata remain at the same level as before the asynchronous reset). When it comes back to its low leve l, the DMUX star ts: the outputs are active and the first processed data is on port A.

Synchronous Reset (SYNCRESET)

Figure 6. Synchronous Reset

DR/2

SyncReset = FS/8

Internal reset

pulse

Port A selected Port B selected Port C selected Port D selected Port E selected

Port F selected Port G selected Port H selected

The DMUX can be synchronously reset to a programmable state dependin g on the conversion ratio. The clock must not be stopped during reset. The synchronizat ion signal is a clock (SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3,…) in 1:8 mode and FS/4*n in 1:4 mode. The front edge of this clock is synchronized with Clkln inside the DMUX, and generates a 200 ps reset pulse. This reset pulse occurs during a f ixed level of Clkln.

If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization, then the output data is immediately corre ct, no modification can b e seen at the output o f the DMUX, and no data is lost (“Internal Timing Diagram” on page 3).

If the DMUX was not synchronized with SyncReset previous to a possible lo ss o f syn chronization, then the output data and data r eady of the DM UX are chang ed. The outp ut data is corr ect after a number of input clocks corresponding to the pipe line delay (“Timing Diagr ams with Synchronous Reset” on page 19).

TS81102G0

2105C–BDC–11/03

TS81102G0

Counter Programmable State

When the counter is reset, its initial states depends on the conversion ratio:

• 1:8: counting on 8 bits,

• 1:4: counting on 4 bits.

Pipeline Delay The maximum pipeline delay depends on the conversion ratio:

• 1:8: pipeline delay = 7

• 1:4: pipeline delay = 3

8-/10-bit, with NAP Mode for the 2

The DMUX is a 10-bit parallel device. The last two bits (bits 8 and 9) may not be used, a nd the corresponding functions are set to nap mode to reduce power consumption.

Unused Bit ECL Differential

Input Data

Input data are ECL compatible (Voh = -0.8V, Vol = -1.8V). The minimum swing required is 100 mV differential. All inputs have a 100Ω differential termination resistor. The middle point of these resistor s is

connected to ground through a 10 pF capacitor. Figure 7. ECL Differential Input Data

Gnd

50Ω Differential Output Data

ClkIn ClkInb

50Ω 50Ω

10 pF

The output clock for the ADC is generate d th ro ug h a 50Ω loaded long tailed. The 50Ω resistor is connected to the ground pad via a diode. The levels are (on the 100Ω differential termination resistor): Vol = -1.4V, Voh = -1.0V.

Figure 8. 50Ω Differential Output Data

Gnd

50Ω

ADCDelAdjOut

50Ω

ADCDelAdjOutb

2105C–BDC–11/03

Single-ended Output Data

To reduce the pin number and power consumption of the DMUX, the eight output ports are single-ended.

To reach the high frequency output (up to 250 MHz) with a reasonable power consumption, the swing must be limited to a maximum of ±500 mV. The common mode is adjustab le from

-1.3V to +2V, with Vplus DOut pins. To ensure better noise immunity, a reference level (common mode) is available (one level by output port).

The output buffers are of ECL type (open emitters – not resistive adapted impedances). They are designed for a 15 mA average output current, and may be used with a 50Ω termin ation impedance.

Figure 9. Single-ended Output Data

VPlusDOut

PadOut

Vee

Following are three application examples for these buffers: ECL/PECL/TTL. Please note that it is possible to have any other odd output format as far as current (36 mA max) and voltage (Vplus Dout – V

≤ 8.3V) limits are not overrid den. The maximum frequency in TTL output

mode depends on the load to be driven.

Table 1. Examples of Application of Buffers

Parameter ECL PECL TTL Unit

VplusDout 0 3.3 3.3 V Vtt -2 1.3 0 V Swing ±0.5 ±0.5 ±1 V Reference -1.3 2 1.5 V Voh -0.8 2.5 2.5 V Vol -1.8 1.5 0.5 V Load 50 50 ≥75 Ω Average Output Current 14 14 15 mA Output Data rate max. 250 250 250 Msps

This corresponds to the “Adjustable Logic Single” in the pinout description. The “Adjustable Single” buffers for reference voltage are the same buffers, but the information

available at the output of these buffers is more like analog than logic.

Note: The Max Output Data Rate is given for a typical 50Ω/2 pF load.

TS81102G0

2105C–BDC–11/03

TS81102G0

Differential Data Ready Output

Built-in Self Test (BIST)

Specifications

Absolute Maximum Ratings

The front edge of the DataReady output occurs when data is available on the correspo nding port. The frequency of this clock depends on the conversion ratio (1: 8 or 1:4), with a dut y cycle of 50%.

The definition is the same as for single-ended output data, but the buffers are differential. This corresponds to the “Adjustable Logic Differential” in the pinout description.

A pseudo-random 10-bit generator is impleme nted in t he DMUX. It generat es a 10-bit signal in the output of the DMUX, with a period of 512 input clocks. The probability of occurrence of codes is uniformly spread over the 1024 possible codes: 0 or 1/1024.

Note that the 256 codes of bits 1 to 8 occur at least once. They start with a BIST command, in phase with the FS/8 clock on Port A. The logic output obt ained on the A to H ports depend s on the conversion ratio. The driving clock of BIST is Clkln. The ClklnType must be set to ‘1’ (DataReady ADC clock) to have a different 10-bit code on each output.

The complete BIST sequence is available on request.

Table 2. Absolute Maximum Ratings

Parameter Symbol Comments Value Unit

Positive supply voltage V Positive output buffer supply voltage V Negative supply voltage V Analog input voltages ADCDelAdjCtrl,

ECL 50Ω input voltage Clkln or Clklnb or

Maximum difference between ECL 50Ω input voltages

PLUSD

ADCDelAdjCtrlb or DMUXDelAdjCtrl, DMUXDelAdjCtrlb or SwiAdj

I[0…9] or I[0…9]b or SyncReset or SyncResetb or ADCDelAdjln or ADCDelAdjlnb

Clkln – Clklnb or I[0…9] - I[0…9]b or SyncReset – Syncresetb or ADCDelAdjln ADCDelAdjlnb

Voltage range for each pad

Differential voltage range

Voltage range for each pad

Minimum differential swing

Maximum differential swing

GND to 6 V GND to 4 V

GND to -6 V

-1 to +1

-2.2 to +0.6 V

0.1

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Table 2. Absolute Maximum Ratings (Continued)

Parameter Symbol Comments Value Unit

Data output current A[0…9] to H[0…9] or

RefA to RefH or DR or DRb

Maximum current 36 mA

TTL input voltage Clkln Type

GND to V

V RatioSel NbBit AsyncReset BIST

Maximum input voltage on diode for

DIODE 700 mV

temperature measurement Maximum input current on diode DIODE 8 mA Maximum junction temperature T Storage temperature T

stg

135 °C

-65 to 150 °C

Note: Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating

conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandator y. See “Thermal and Moisture Characteristics” on page 26.

Recommended Operating Conditions

Table 3. Recommended Operating Conditions

Parameter Symbol Comments

Positive supply voltage V Positive output buffer supply

voltage Positive output buffer supply

voltage Negative supply voltage V Operating temperature range T

TS81102G0

PLUSD

ECL output compatibility – 0 – V

PECL output compatibility – 3.3 – V

TTL output compatibility – 3.3 – V

Commercial grade: “C” Industrial grade: “V”

Recommended Value

Min Typ Max Unit

4.45 5 5.25 V

-5.25-5-4.75V 0 < Tc; Tj < 90

°C

-40 < Tc; Tj < 110

2105C–BDC–11/03

TS81102G0

Electrical Operating

Tj (typical) = 70°C. Full Temperature Range: -40°C < Tc; Tj < 110°C. (Guaranteed temperature range are depending on part number)

Characteristics

Table 4. Electrical Specifications

Parameter Symbol Power Requirements

Positive supply voltage

PLUSD

Negative supply voltage

Supply Currents ECL (50Ω) and PECL (50Ω)

(for every configuration)

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

TTL (75Ω)

(for every configuration)

1:8, 8 bits

1:8, 10 bits

1:4, 8 bits

1:4, 10 bits

Nominal power dissipation

PLUSDOUT

PECL

ECL

TTL

–

Test

Value

Level

4.75 –

-0.25

3.135

5 – 0

3.3

5.25 –

0.25

3.465

1 -5.25 -5 -4.75 V

–

540

–

640

–

270

–

320

–

760

–

900

–

380

–

450

–

1180

719

1140

790 590 592 720 634

1610

872

1770

980 810 670 880 729

–

1820

–

2240

–

910

–

1120

–

2440

–

3010

–

1220

–

1510

–

Unit NoteMin Typ Max

V – V V V

(1)

mA mA mA mA mA mA mA mA mA

(1)

ECL (50Ω)

1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits

2105C–BDC–11/03

PD PD PD PD

5.2

5.9

3.9

4.2

5.6

6.4

4.1

4.5

6.9

4.3

4.7

W W W W

Table 4. Electrical Specifications (Continued)

Parameter Symbol

PECL (50Ω)

1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits

PD PD PD PD

TTL (75Ω)

1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits

PD PD PD PD

Delay Adjust Control

DMUXDelAdjCtrl differential voltage

DDAC 250 ps 500 ps 750 ps Input current

ADCDelAdjCtrl differential voltage

IDDAC

ADAC 250 ps 500 ps 750 ps Input current

IADAC

Digital Outputs

ECL Output (assuming V

= 0V, SWIADJ = 0V, 50Ω

PLUSD

termination resistor on board)

Logic “0” voltage Logic “1” voltage Reference voltage

REF

PECL Output (assuming V

= 3.3V, SWIADJ = 0V, 50Ω

PLUSD

termination resistor on board)

Logic “0” voltage Logic “1” voltage Reference voltage

REF

TTL Output (assuming V

= 3.3V, SWIADJ = 0V, 75Ω

PLUSD

termination resistor on board)

Logic “0” voltage Logic “1” voltage Reference voltage

Output level drift with temperature (data and DR outputs)

REF

–––-1.3–mV/

Test

Level

5.8

6.6

4.2

4.6

6.8

7.8

4.7

5.2

– –

–

– – –

– –

–

– – –

1–

– –

1–

– –

1–

– –

Value

6.2

7.1

4.4

4.8

7.3

8.4

4.9

5.5

–

-0.5 0

0.5 –

–

-0.5 0

0.5 –

-2.12

-1.16

-1.40

1.27

2.44

1.83

0.9

2.31

1.2

6.6

7.6

4.6

5.1

7.7 9

5.1

5.8

– – – – –

– – –

Unit NoteMin Typ Max

W W W W

V V V

°C

TS81102G0

2105C–BDC–11/03

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