• Built-in Antiblooming Device Providing an Electronic Shutter Function
• Pixel: 14 µmx14µm
• Image Zone: 14.34 x 14.34 mm²
• Four Outputs (256 x 1024 pixels) at 20 MHz Each
• Possible Binning 2 x 2
• Optical Shield against Parasitic Reflexions and Stray Light
• A/R Window in 400 - 700 nm Bandwidth
Description
The TH7887A is especially designed for high data rate applications (up to 60 pict/s) in
medical and industrial fields.
This area array image sensor consists of a 1024 x 1024 pixels (14
zone associated to a memory zone (masked with optical shield).
In order to increase data rate, the image zone is divided into four zones (256 x 1024
each) which are read in parallel through 4 different outputs (readout frequency up to
20 MHz/output leading to a total readout frequency of 80 MHz).
The TH7887A is designed with antiblooming gates.
Moreover, the 2 x 2 binning mode is available on this sensor. In this case, the image
size is 512 x 512 with 28
The TH7887A is sealed with a specific anti-reflective window optimized in 400 700 nm bandwidth.
µmx28µm pixels. Each output will read 128 x 512 pixels.
µmx14µm) image
Area Array CCD
Image Sensor
1024 x 1024
Pixels with
Antiblooming
TH7887A
Rev. 2146A–IMAGE–05/02
1
Figure 1. TH7887A Organization
1, 2, 3, 4
PΦ
1, 2, 3, 4
M
Φ
A
Φ
VA
1024 x 1024
Image Zone
1024 x 1024
Memory Zone
VDD1 VS1 VDD2 VS2
VOS1VOS2VOS3VOS4
VDD3 VS3
VDD4 VS4
Φ
M
VGS
ΦR
L 1,2Φ
2
TH7887A
2146A–IMAGE–05/02
Pin Identification
TH7887A
VA
AA
W
V
C
B
A
VSSVOS2 VOS1VOS3VOS4 R
Φ
L1 VSS VDR VS4 VS3 VS2 VS1 VSSΦ
L2 M VGS VDD4 VDD3 VDD2 VDD1 VSSΦΦ
A M4 M3 ΦP3 P2
VSS M2
VSS M1 P4 P1 M4 M1 ΦP4 VSSΦΦΦΦΦ
VDDP N.C
ΦM2
ΦΦΦΦ
VSS P2 M3 VSS P3 VSS
87654321
ΦP1
ΦΦΦΦ
TOP VIEW
Pin NumberSymbolDesignation
A2, A6
B2, C5
B5, C3
A5, C2
A3, A7
B7, C4
B4, C6
C7, A4
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
ΦP4
ΦP3
Image zone clocks
ΦP2
ΦP1
ΦM1
ΦM2
Memory zone clocks
ΦM3
ΦM4
A1
Index
2146A–IMAGE–05/02
V7ΦMMemory to register clock
W8ΦL1
Readout register clocks
V8ΦL2
V2VDD1
V3VDD2
Output amplifier drain supply
V4VDD3
V5VDD4
W2VS1
W3VS2
Output amplifier source supply
W4VS3
W5VS4
AA6VDDPScreen voltage
AA5NCNot connected
V6VGSRegister output gate bias
3
Pin NumberSymbolDesignation
AA1VOS1
AA2VOS2
AA3VOS3
AA4VOS4
AA8ΦRReset clock
C8ΦAAntiblooming gate clock
W6VDRReset bias
C1VAAntiblooming diode bias
AA7, V1, W1VSS
B6, B1, A1, B3VSS
Note:1. Short circuited on package.
Video output signal
Substrate biasW7, A8, B8VSS
4
TH7887A
2146A–IMAGE–05/02
TH7887A
e
Geometrical
Characteristics
Figure 2. Video Line (on each output)
3 isolation lines
First pixel
6 dark reference lines
The image zone features 1024 useful lines (+ 20 extra lines) of 1024 pixels. For readout
only, the full frame is split into 4 blocks of 256 columns.
The video line consists of 256 useful pixels, and 273 elements in total (for each output).
Image zone
Memory zone
7 dark reference lines
1024 useful pixels
3 isolation lines
1 inactive line
1044 line
1044 lin
Pixels 1 to 17 : inactive prescan elements
Pixels 18 to 273 : useful elements
2146A–IMAGE–05/02
Vos1Vos2Vos3Vos4
5
Figure 3. Pixel Layout
14 µm
ΦAΦ AΦ AΦ A
VA
VA
A
A'
Aperture 10.3 µm
14 µm
Φ P1
Φ P2
Φ P3
Φ P4
Φ P1
Figure 4. Cross-section AA’
Potential profile
during integration time
Φ P1
Φ P2
14 µm
Φ P3
Φ P4
Signal charge
for one pixel
Φ P1
Transfer direction
6
TH7887A
2146A–IMAGE–05/02
Absolute Maximum Ratings*
Storage Temperature .................................... -55°Cto+150°C
Operating Temperature ...............................-40°Cto+85°C
*NOTICE:Stresses above those listed under absolute max-
imum ratings may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
Operating Range
The operating range defines the limits where function is guaranteed.
Electrical limits of applied signals are given in the operating conditions section.
Operating
Precautions
Shorting the video outputs to any other pin, even temporarily, can permanently damage
the on-chip output amplifier.
Operating Conditions
Table 1 . DC Characteristics
Value
ParameterSymbol
Output amplifier drain supply
Screen voltageVDDP14.51515.5V
Reset biasVDR14.51515.5V
Antiblooming diode biasVA14.51515.5V
Register output gate biasVGS2.22.52.8V
VDD1, VDD2,
VDD3, VDD4
14.51515.5V
UnitMinTypMax
Output amplifier source supplyVS1,2,3,4–0–V
GroundVSS–0–V
2146A–IMAGE–05/02
7
Timing DiagramThe following diagrams are given for:
•20 MHz readout frequency
•1.25 MHz vertical transfer frequency
Readout of one image is performed in 2 steps:
•image zone to memory zone transfer
•memory zone to register transfer and readout of register
This last step is also an integration period, the duration of which can also be increased
according to the required frame rates.
Figure 5. Frame Timing Diagram
Integration period
Φ A
P1
Φ
Φ P2
Φ P3
Picture readout
Cleaning period (*)
Image to memory zone
Transfer
Memory zone
Φ P4
Φ M1
Φ M2
Φ M3
Φ M4
Φ L1
Φ L2
Φ R
=ΦM
15
15
See fig. 6
1044
1044
1044 pulses
See fig. 7
(*) During the cleaning period, memory clocks must be pulsed as during readout time
(specially for high temperature applications).
8
TH7887A
2146A–IMAGE–05/02
Figure 6. Line Timing Diagram
ΦM1
=
ΦM
TH7887A
Item fig.8
7To
5To
ΦM2
ΦM3
ΦM4
See fig. 9
ΦL1
ΦL2
ΦR
Vos 1,2,3,4
117 18273 min
1
2
1 : 17 inactive pre-scan elements
2 : 256 useful video pixels
Figure 7. Vertical Transfer During Image to Memory Zone Transfer
20 ns < tf < 2 To
100 ns min.
ΦA
1
ΦP1
2
100 ns min.
3To
3To
1044
5To
3To
3To
100 ns min.
100 ns min.
20 ns < tr < 2 To
17
1
1
ΦM1
2146A–IMAGE–05/02
ΦP2
ΦP3
ΦP4
=
ΦM2
ΦM3
ΦM4
ΦM
See fig. 8
9
Figure 8. Transfer Period from Image Zone to Memory Zone (ΦPandΦM)
for 1.25 MHz Vertical Transfer Frequency (Fv = 1/Tv)
Tv=800 ns
Φ M2
Φ M3
Φ M4
tr
To = Tv / 8
3 To
tf
5 To
5 To
3 To5 To
3 To
Φ P1
Φ P2
Φ P3
Φ P4
=ΦM1
=
=
=
Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications
50 ns
16 ns min
Φ
L1
16 ns min
25 ns < tr < To/3
25 ns < tf < To/3
To = 100 ns
t1
12 ns min
t2t2
td
Reset feedthrough
td = 8 ns typical delay time
A
0.3A
td
Φ
L2
Φ
R
Vos 1,2,3,4
t1
Signal
level
t1 = 10 ns typ.
t2 = 5 ns typ.
Cross over of complementary clocks (Φ L1, Φ L2) between 30% and 70% of maximum amplitude.
10
TH7887A
2146A–IMAGE–05/02
TH7887A
Binning Mode
In this mode, the image is composed of 512 x 512 pixels (28 µmx28µm each).
Operation
Figure 10. Summation in the Readout Register of 2 Adjacent Lines.
15 To
5To3To5To
Φ M1
5To3To5To
Φ M2
Φ M3
Φ M1
Φ M
=ΦM1
100 ns min
3To
3To5To3To
5To3To
3T0
Fall times and rise times:
see figures 8 & 9
3To
100 ns min
Φ L1
Φ L2
Figure 11. Summation of 2 Adjacent Pixels
Φ L1
Φ L2
Φ R
Vos 1,2,3,4
Output reset frequency
divided by 2
Pixel i
Useful signal
Pixel i
+
Pixel i+1
In binning mode operation maximum level of elementary pixel (14 x 14 µm) is reduced to Vsat/4.
2146A–IMAGE–05/02
11
Exposure Time
The TH7887A allows exposure time control (electronic shutter function).
Reduction
The exposure time reduction is achieved by pulsing all the Φ Pi gates to 0V to continuously remove all photogenerated electrons through antiblooming drain VA.
Figure 12. Timing Diagram for Electronic Shutter
Image period
Φ
A
Φ
Φ
Φ
Φ
1 µs
P1
P2
P3
P4
1 µs
Table 2 . Drive Clock Characteristics
ParameterSymbol
Image zone clocks
High level
Low level
Memory zone clocks
High level
Low level
Memory to register clocks
High level
Low level
Antiblooming gate
High level (integration)
Low level (transfer)
ΦP1,2,3,4
ΦM1,2,3,4
ΦM
ΦA
Transfer
Fall times and rise times: see figures 7 & 8
Value
8.5
0
8.5
0
8.5
0
5.5
0
9
0.5
9
0.5
9
0.5
5.5
0.5
Obturation
9.5
0.8
9.5
0.8
9.5
0.8
5.5
0.8
UnitRemarksMinTypMax
V
V
V
V
V
V
V
V
Integration
Typical input capacitance
15 nF
See Figure 13
Typical input capacitance
15.5 nF
See Figure 13
Typical input capacitance
10 nF
Typical input capacitance
14 nF
See Figure 13 and Figure 15
12
TH7887A
2146A–IMAGE–05/02
Table 2 . Drive Clock Characteristics (Continued)
TH7887A
Value
ParameterSymbol
Reset gate
High level
Low level
Readout register clocks
High level
Low level
Maximum readout register
frequency
Image zone to memory zone
transfer frequency
ΦR
ΦL1, 2
ΦF
H
ΦF
V
Figure 13. Capacitance Network for Drive Clocks
ΦP2
3.4 nF
2.5 nF
ΦP1
3.3 nF
ΦA
2.5 nF
ΦP3
1.4 nF
ΦP4
UnitRemarksMinTypMax
Typical input capacitance
10
0
8.5
0
–2023MHzSee Figure 9
–1.251.7MHzSee Figure 14
11
0.5
9
0.5
12
0.8
9.5
0.8
V
V
Φ L1ΦL2
V
V
10 pF
50 pF
60 pF75 pF
ΦP2
0.7 nF
0.5 nF
ΦP1
0.7 nF
VA
0.5 nF
ΦP3
1.3 nF
Φ A
Φ P4
2146A–IMAGE–05/02
3.2 nF4.9 nF2.2 nF
2.2 nF
ΦP1Φ P2
4.4 nF
4.4 nF4.4 nF
3.4 nF
ΦP4Φ P3
3.9 nF4.4 nF3.2 nF
3.2 nF
ΦM1Φ M2
4.4 nF
4.4 nF4.4 nF
3.9 nF
ΦM4Φ M3
13
Electrical
Performances
Table 3 . Static and Dynamic Electrical Characteritics
Value
ParameterSymbol
Output amplier supply currentI
Output impedanceZ
DC output levelV
Output conversion factorCVF7.888.2µV/ e-
Electro-optical
Performances
DD
S
REF
•General test conditions:
–To p = 2 5 °C (package back temperature).
–8.5–mAper amplifier
200225250Ω
–11.5–V
UnitRemarksMinTypMax
–Light source: 2854K with 2 mm BG38 filter (unless specified) + F/3.5 optical
aperture.
–60 images per second mode (unless specified).
–Typical operating conditions.
•Readout on each output.
•Measurements exclude dummy elements and blemishes.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibilit y for any errors
which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
AT ME L®is the trademarks of Atmel.
Other terms and product names may be the trademar ks of others.
Printed on recycled paper.
2146A–IMAGE–05/020M
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