Rainbow Electronics TH7834C User Manual
Features
• 6.5 µm x 6.5 µm Photodiode Pixel, at 6.5 µm Pitch
• 2 x 2 Outputs
• High Output Data Rate: 4 x 5 MHz
• High Dynamic Range: 10000: 1
• Antiblooming and Exposure Time Control
• Very Low Lag
• 56 lead 0.6" DIL Package
Description
Atmel’s TH7834C is a linear sensor based on charge-coupled device (CCD) technology. It can be used in a wide range of applications thanks to operating mode flexibility,
very high definition and high dynamic range (document scanning, digital photography,
Art, Industrial and Scientific Applications).
Pixel 1
mark
VOS1
VDR1
VS1
ΦR1-2
VSS
VST
ΦA1-2
VGS1-2
VS
Φ3A
Φ1A
Φ4A
Φ2A
VSS
VSS
Φ2C
Φ4C
Φ1C
Φ3C
VSS
ΦP3-4
VA3-4
ΦLS3-4
VSS
VDD3-4
VS3
VDR3
VOS3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VOS2
VDR2
VS2
VDD1-2
VSS
ΦLS1-2
VA1-2
ΦP1-2
VSS
Φ3D
Φ1D
Φ4D
Φ2D
VSS
VSS
Φ2B
Φ4B
Φ1B
Φ3B
VSS
VGS3-4
ΦA3-4
VST
VSS
ΦR3-4
VS4
VDR4
VOS4
Very Highresolution
Linear CCD
Image Sensor
(12000 Pixels)
TH7834C
TOP VIEW
Rev. 1997A–IMAGE–05/02
1
Pin Description
Pin Number Symbol Designation
1V
2V
3V
4 Φ
5, 9, 14, 15, 20, 24, 33,
OS1
DR1
S1
R1-2
V
SS
Output 1 (Odd Pixels)
Reset DC Bias (Output 1)
Amplifier Source Bias (Output 1)
Reset Clock (Outputs 1 and 2)
Substrate Bias (Ground)
37, 42, 43, 48, 52
6, 34 VST Pixel Storage Gate DC Bias
7 Φ
8V
10 Φ
11 Φ
12 Φ
13 Φ
16 Φ
17 Φ
18 Φ
19 Φ
21 Φ
22 VA
23 Φ
25 V
26 V
27 V
28 V
29 V
30 V
31 V
32 Φ
35 Φ
36 V
38 Φ
39 Φ
40 Φ
41 Φ
44 Φ
45 Φ
A1-2
GS1-2
3A
1A
4A
2A
2C
4C
1C
3C
P3-4
3-4
LS3-4
DD3-4
S3
DR3
OS3
OS4
DR4
S4
R3-4
A3-4
GS3-4
3D
1D
4D
2D
2B
4B
Antiblooming and/or Exposure Time Control
Output Gate DC Bias
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Transfer Clock
Antiblooming Diode Bias
Register End Transport Clock
Amplifier Drain Supplies (Outputs 3, 4)
Amplifier Source Bias (Output 3)
Reset DC Bias (Output 3)
Output 3 (Odd Pixels)
Output 4 (Even Pixels)
Reset DC Bias (Output 4)
Amplifier Source Bias (Output 4)
Reset Clock (Outputs 3 and 4)
Antiblooming and/or Exposure Time Control
Output Gate DC Bias
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
Register Main Transport Clock
2
TH7834C
1997A–IMAGE–05/02
Pin Description (Continued)
Pin Number Symbol Designation
46 Φ
47 Φ
49 Φ
50 VA
51 Φ
53 V
54 V
55 V
56 V
Notes: 1. Pins Φ
A1-2,VGS1-2
1B
3B
P1-2
1-2
LS1-2
DD1-2
S2
DR2
OS2
, Φ
P1-2
connected together inside the package.
2. Two Pins V
connected together inside the package.
ST
Figure 1. TH7834 Block Diagram
ΦLS1-2VDR2 VDR4VS2 VS4
,VA
1-2
, Φ
LS1-2,VDD1-2
Φ3B
Φ1B
Register Main Transport Clock
Register Main Transport Clock
Transfer Clock
Antiblooming Diode Bias
Register End Transport Clock
Amplifier Drain Supplies (Outputs 1, 2)
Amplifier Source Bias (Output 2)
Reset DC Bias (Output 2)
Output 2 (Even Pixels)
, Φ
and respectively, Φ
R1-2
Φ4B
Φ2B
Φ2D
Φ4D
A3-4,VGS3-4
Φ1D
Φ3D
, Φ
P3-4
,VA
3-4,ΦLS3-4,VDD3-4
VGS3-4
TH7834C
, Φ
are not
R3-4
VOS2 VOS4CCD B
ΦP1-2
VDD1-2
ΦR1-2
VST
VOS1 VOS3CCD A CCD C
1
Φ4A
Φ2A
Φ2C
Φ4C
Φ3C
Φ1C
VGS1-2VDR1 VDR3VS1 VS3
Φ1A
Φ3A
CCD D
VST
ΦR3-4
12000
VDD3-4
ΦP3-4
ΦLS3-4
Description TH7834C high resolution linear array consists of 12000 useful pixel photosensitive line,
associated with four CCD shi ft registers and fo ur output amplifiers. Transfer gate s on
both sides of the photosensitive line enable delivery of charges, respectively:
• on one side, charge accumulated by odd pixels (1, 3, 5… 11999), to CCD shift
registers A and C,
• on the other side, charge accumulated by even pixels (2, 4, 6… 12000), to CCD
shift registers B and D.
1997A–IMAGE–05/02
Shift registers 1 and 2 collect charges generated by one half of the photosensitive line
(pixel 1 to 6000), whereas shift registers 3 and 4 collect charges generated by the second half of the photosensitive line (pixels 12000 to 6001).
3
Figure 2. Driving Schematic
The four CCD shift registers have separated clocks. The output signal can be, then,
delivered simultaneously or sequentially on the four outputs.
The four CCD shift registers are designed with 4 separated gates. According to the gate
connection, the signal can be read through 2 or 4 output amplifiers.
According to gate connection, 2 or 4 output operating mode can be chosen. In the 4 output operating mode, signals associated to the end pixels of the array (either pixels
number 1, 2 or pixels number 11999, 12000) are delivered first in time and signals corresponding to the center of the line (pixels number 5999, 6000 and 6001, 6002) are
delivered last in time. Thus, external circuitry and processing are needed to combine the
four video outputs and to restore the normal order of the pixels in accordance with their
spatial distribution on the photosensitive line.
Terminal stages for every CCD shift register have separate clock control inputs in order
to speed up the final charge to voltage conversion and reduce the video output settling
time.
Antiblooming and exposure time control functions are provided.
Symmetrical TH7834 package PIN OUT allow to inverted pin 1 and 56 positions without
damage.
To obtain optimal operating mode, separated driving circuits are recommended for each
readout shift register (at least
Logical signal :
L1
Φ
L2
Φ
Logical signal :
ΦLS and ΦR).
L1
Φ
L2
Φ
Pins (1,2,3,4)B
Φ
VOS2 VOS4CCD B26000
Photosensitive line
VOS1 VOS3CCD A CCD C
1
Logical signal :
Pins (1,2,3,4)AF
L1
Φ
L2
Φ
5999
6002
6001
Pins (1,2,3,4)D
Φ
Pins (1,2,3,4)CF
L1Logical signal :
Φ
L2
Φ
CCD D
12000
11999
PHI3C
4
TH7834C
1997A–IMAGE–05/02