*NOTICE:Stresses above those listed under absolute max-
imum ratings may cause permanent device failure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
Operating RangeThe operating range defines the temperature limits between which functionality is guar-
anteed: 0°Cto70°C.
Operating PrecautionsShorting the video output to V
output amplifier.
or VDD, even temporarily, can permanently damage the
SS
2
TH7804A
1989A–IMAGE–05/02
Operating Conditions (T = 25°)
Table 1 . DC Bias Characteristics
TH7804A
Value
ParameterSymbol
Output Amplifier Drain SupplyV
Reset DC BiasV
Output Gate DC BiasV
Photosensitive Zone And
Register DC Bias
Substrate BiasV
DD
DR
GS
V
T
SS
141516V
VDD-2.4VDD-2VDD-1V
5.566.5V
0.95 V
TN
0.00.0V
Te s t P oi n t 1T P 1V
TestsPoints2And3TP2,TP3V
Notes: 1. Nominal value of VT:
V
=6.7VifΦTclock levels are at their typical value.
TN
2. No use for operation. For testing purpose only.
Note:1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced
by the strap should not exceed 5 pF.
(2) Strapped
ECHA
ECHB
SS
(22) Strapped
DD
(1)
see note
1989A–IMAGE–05/02
3
Figure 1. Basic Test Configuration
Figure 2. Timing Diagram in Basic Mode
4
TH7804A
1989A–IMAGE–05/02
Table 3 . Drive Clock Characteristics (see Figure 2)
TH7804A
Value
ParameterSymbolLogic
Transfer Clock
Φ
, Φ
P
CΦ
T
T
P
Register Transport ClockLow0.00.40.6
Register Transport Clock
Capacitance
Transfer Clock CapacitanceCΦ
High111314
400700pF
130200pF
UnitRemarkMin.Typ.Max.
V
(1)
Note:1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal. If such
spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically
20 to 100Ω) in the corresponding driver output.
Table 4 . Static and Dynamic Electrical Characteristics
Value
ParameterSymbol
DC Output LevelV
Output ImpedanceZ
Register Single-stage Transfer
Efficiency
Max. Data Output FrequencyF
Input Current On Pins: 2, 9, 10,
11, 12, 15, 16, 17, 18, 22
REF
S
CTE99.99299.998%V
Smax
I
e
81012V
500Ω
1220MHz
2µA
LogicRemarkMin.Typ.Max.
(1)
=1V
OS
(2)
= 15V
V
IN
All other pins: 0V
Peak Current Sink on Φ
Peak Current Sink on Φ
Clock(IΦT)
T
Clock(IΦP)
P
Output Amplifier + Internal Logic
Supply Current
Static Power DissipationP
Notes: 1. V
2. Fs = 2 F Φ
Electro-optical
Performance
= average video output voltage.
OS
. The minimum clock frequency is limited by the increase in dark signal.
T
General measurement conditions: TC=25°C; Ti=1ms;FΦT=2.5MHz(F
The filter limits the spectrum to 700 nm; in these conditions 1µJ/cm
lux.s.
Operating conditions (see Figure 1).
First and last pixels, as well as reference elements, are excluded from the specification.
Measurements taken on each output in succession.
P
P
I
DD
D
250mAt
80mAt
17mA
255300mW
2
corresponds to 3.5
RISE
RISE
V
V
V
V
INH
DD
INH
DD
DATA
=15ns
=15ns
=0V
=15V
=0V
=15V
=5MHz)
1989A–IMAGE–05/02
5
Table 5 . Electro-optical Performance
Value
ParameterSymbol
Saturation Output VoltageV
Saturation ExposureE
SAT
SAT
1.31.82.3V
0.30µJ/cm
ResponsivityR4.56V/µJ/cm
Responsivity Unbalance∆R/R28%
UnitRemarkMin.Typ.Max.
(1) (2)
2
2
(3)
Photo Response Non-uniformity
Peak-to-peak
Contrast Transfer Function at FN
(38 I p/mm)
PRNU±3±10% V
CTF70%V
Temporal Noise In Darkness180µV
Dynamic Range (Relative to rms
Noise)
Average Dark SignalV
Dark Signal Non-uniformity
Peak-to-peak
DR40006000
DS
0.080.5mV
DSNU0.150.5mV
Notes: 1. Value measured with respect to zero reference level (see Figure 2).
2. Conversion factor is typically 1.5 µV/e-.
3. ∆R/R is defined as
200 RA RB–
----------- ------------- ----------
RA RB+
where RA is responsivity of video output A, RB is responsivity of video output B.
4. Measured in Correlated Double Sampling (C.D.S.) mode.
Figure 3. Typical Spectral Response
rms
OS
VOS=50mV
to 1V
=0.9V
OS
(4)
6
TH7804A
1989A–IMAGE–05/02
Figure 4. CTF Typical Curves (2854 K Source)
Electro-optical Performance Without Infrared Cut-off Filtering
The TH7804A’s special semiconductor process enables it to exploit the silicon's high
near infrared sensitivity while maintaining good imaging performance in terms of
response uniformity and resolution. Typical changes in performance with and without IR
filtering are summarized below.
TH7804A
With IR Cut-off FilterNo IR Cut-off Filter
Average Video Signal Due to a Given Scene IlluminationV
PRNU (Single Defects Excluded)±5%±5%
CTF at Nyquist Frequency70%50%
Complementary
Operating Modes
TH7804A may be used in several configurations in regards to video output sampling and
charge sensing reset.
OS
VOSx4
1. Sampling Options:
Inhibition of internal sampling pulses allows for two possibilities:
a. no sampling: video output delivered in unsampled form,
b. sampling by external clocks: external sampling pulses directly applied to
Φ
, Φ
ECHA
If internal sampling clocks S
ECHB
inputs.
Φ
ECHA
and SΦ
are not used, it is recommended of
ECHB
unpower the corresponding clock drivers, as this will greatly reduce on-chip power
consumption.
2. External Reset Option:
The position and period of the charge reset clocks may be optimized by using external
clocks on
Φ
and ΦRBinputs. This is specially interesting to optimize the video outputs
RA
for Correlated Double Sampling (in order to reduce noise and improve S/N ratio).
Control signals to be applied in the different configurations are shown in Table 6.
1989A–IMAGE–05/02
7
Table 6 . Selection of Operating Modes
OptionImplementationRemarks
No Sampling
Sampling by External Clocks
Reset Control by External Clocks
(2) and Φ
Φ
ECHA
SΦ
V
(3) and SΦ
ECHA
(19) connected to V
INH
Sampling clocks connected to Φ
SΦ
V
Ext. Φ
Ext. Φ
and SΦ
ECHA
(19) connected to V
INH
on ΦRA(4) input
RA
on ΦRB(18)
RB
(22) connected to V
ECHB
(21) unconnected
ECHB
DD
unconnected
ECHB
DD
DD
ECHAΦECHB
(1)
seeFigure5for
sampling clock timing
(1)
seeFigure4for
reset clock timing
Note:1. Drain supply current IDDdecreases from 10 mA to 8 mA typically when internal sampling clock is disabled.
Table 7 . External ΦRA, ΦRB, Φ
ECHA
, Φ
Clock Characteristics
ECHB
Value s
ParameterSymbolLogic
External Reset Clock
Sampling ClocksLow0.00.40.6V
Reset and Sampling Clock
Capacitance
CΦ
Φ
CΦ
Φ
RA
ECHA
RA
ECHA
, Φ
, Φ
,CΦ
,CΦ
RB
ECHB
RB
ECHB
High1212.513V
1015pF
Insertion of a serial resistor (typically 100Ω) at the driver output avoids spurious negative transients.
UnitMin.Typ.Max.
8
TH7804A
1989A–IMAGE–05/02
TH7804A
Figure 5. Timing Diagram — Clocks and Video Output Timing Diagram With and Without On-chip Sampling.
External reset clocks improve electro-optical performance, as listed below. Other operating conditions and other electrooptical parameters remain unchanged.
Table 8 . Performance Improvements with External ΦRAand ΦRBConfiguration
Value
ParameterSymbol
Saturation Output VoltageV
ResponsivityR8V/µJ/cm
Dynamic RangeDR8000
SAT
2.0V
UnitTyp.
2
Electro-optical performances obtained with complementary modes are not guaranteed for the standard products.
1989A–IMAGE–05/02
9
Outline Drawing
Z = 1.28 ± 0.23
2.16
Notes: 1. If an optical reference is needed, it is recommended to use the window face plane.
2. Variation of Z (azimuth) on the photosensitive area of a device is ≤ ±0.1 mm.
3. Value and tolerance of Y are applicable to each individual pixel of the photosensitive line.
Ordering CodeTH7804ACC
10
TH7804A
1989A–IMAGE–05/02
Atmel HeadquartersAtmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. T he Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as cr itical
components in life support devices or systems.
AT ME L®is the trademarks of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1989A–IMAGE–05/020M
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.