Rainbow Electronics T89C51RC2 User Manual

This errata sheet describes the fu nc tio nal dev iat ion s know n at the rel ea se d ate of this
document.

Errata History

Lot Number Trouble list Status

All

T01, T02, T03, T04, T05, T06, T07, T08, T09, T10, T11,
T12, T13

Not Fixed

Trouble descriptions

80C51 MCUs

T89C51RB2
T89C51RC2

T01

Description

Workaround

T02

Description

Workaround

T03

Description

Workaround

During UART reception, clearing REN may generate unexpected IT.

During Uart reception, if the REN bit is cleared between a start bit detection and the
end of reception, the Uart will not discard the data (RI is set).

Test REN at the beginning of Interrupt routine just after CLR RI, and to run the
Interrupt routine code only if REN is set.

Double IT on external falling edge on INT1 or INT0 in X2 Mode

When CPU is in X2 mode and Timer1 or Timer 0 in X1 mode (CKCON = 0x7F), IEx
flag is not cleared by hardware after servicing interrupt. In this case, the CPU
executes the ISR a second time.

The work around is to clear IEx bit in Interrupt subroutine.
INT1_ISR : ; Interrupt sub routine

CLR IE1

....

Internal Resistor on Reset Pin

Deviation from electrical specification. Typical value for internal resistor on Reset pin:
20K Ohms

No

Errata Sheet

Rev. A – 31-May-01

1

T89C51RB2/RC2

T04

Description
Workaround

T05

Description

Workaround

T06

Description
Workaround

T07

Description
Workaround

Bootloader - Write Page API - V1.1

The Write Page API does not work correctly with the full page size.
Write by 32 bytes size page instead of 128 bytes.

Bootloader - Read Philips compatibility - V1.1.

The previous version added FF bytes after the last address to complete the last 16
bytes line.

Ignore the returned data above the end address of the Read command.

Bootloader - SBV and BSB protection - V1.1

SBV and BSB are not protected with SSB.
No

Bootloader - Program Byte API - V1.1

No returned value Acc=00h if programming OK.
No

Rev. A – 31-May-01

T08

Description

Workaround

T09

Description

Workaround

Bootloader - Write SSB level 0 - V1.1

The command "Write SSB level0" is allowed in level 1 security. So the device can be
unprotected.

No

SPI interface - Transmission on Master Mode

A 9th bit is transmitted by the interface when the clock rate is set on divide by 2
mode and a positive polarity is selected ; the SPR2, SPR1, SPR0 bits are cleared
(000) and CPOL = 1 on the SPCON register.

Set the clock rate divide by 4 and X2 mode.

2