Rainbow Electronics T89C51CC02 User Manual

8-bit MCU with CAN controller and Flash

1. Description

T89C51CC02

Part of the CANaryTMfamily of microcontrollers dedicated to CAN network applications, the T89C51CC02 is a low pin count 8-bit Flash microcontroller.

While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

2. Features

• 80C51 core architecture:

• 256 bytes of on-chip RAM

• 256 bytes of on-chip ERAM

• 16 Kbytes of on-chip Flash memory

Read/Write cycle : 10k Data Retention 10 years at 85°C

• 2 Kbytes of on-chip Flash for Bootloader

• 2 Kbytes of on-chip EEPROM

Read/Write cycle : 100k

• 14-source 4-level interrupt

• Three 16-bit timer/counter

• Full duplex UART compatible 80C51

• maximum crystal frequency 40 MHz. In X2 mode,

20 MHz (CPU core, 40 MHz)

• three or four ports: 16 or 20 digital I/O lines

• two-channel 16-bit PCA with:

- PWM (8-bit)

- High-speed output

- Timer and edge capture

• Double Data Pointer

• 21-bit watchdog timer (including 7 programmable

bits)

• A 10-bit resolution analog to digital converter (ADC)

with 8 multiplexed inputs

• Separate power supply for analog

• Full CAN controller:

• Fully compliant with CAN standard rev 2.0 A

and 2.0 B

• Optimized structure for communication

management (via SFR)

• 4 independent message objects:

- Each message object programmable on transmission or reception

Besides the full CAN controller T89C51CC02 provides 16 Kbytes of Flash memory including In-system Programming (ISP), 2-Kbyte Boot Flash Memory, 2Kbyte EEPROM and 512 bytes RAM.

Special attention is payed to the reduction of the electromagnetic emission of T89C51CC02.

- individual tag and mask filters up to 29-bit identifier/message object

- 8-byte cyclic data register (FIFO)/message object

- 16-bit status & control register/message object

- 16-bit Time-Stamping register/message object

- CAN specification 2.0 part A or 2.0 part B programmable message objects

- Access to message object control and data register via SFR

- Programmable reception buffer lenght up to 4 message objects

- Priority management of reception of hits on several message objects at the same time (Basic CAN Feature)

- Priority management for transmission

- message object overrun interrupt

• Supports

- Time Triggered Communication.

- Autobaud and Listening mode

- Automatic reply mode programmable

• 1 Mbit/s maximum transfer rate at 8MHz* Crystal

frequency in X2 mode.

• Readable error counters

• Programmable link to on-chip Timer for Time

Stamping and Network synchronization

• Independent baud rate prescaler

• Data, Remote, Error and overload frame handling

• Power saving modes:

• Idle mode

• Power down mode

• Power supply: 5V +/- 10% ,3V +/- 10%

• Temperature range: Industrial (-40° to +85°C)

• Packages: PLCC28, SOIC28, (TSSOP28, SOIC24)**

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Preliminary

T89C51CC02

* At BRP = 1 sampling point will be fixed. ** Ask for availability

3. Block Diagram

RxD

TxD

Vcc

Vss

ECI

PCA

T2EX

RxDC

TxDC

XTAL1 XTAL2

CPU

RESET

UART

Timer 0 Timer 1

C51

CORE

RAM 256x8

INT Ctrl

INT0

Flash

Boot

16kx

loader

IB-bus

Port 1

INT1

(1): 8 analog Inputs / 8 Digital I/O (2): 2-Bit I/O Port

PROM

2kx8

Parallel I/O Ports & Ext. Bus

Port 2

P1(1)

P2(2)

2kx8

Port 3

ERAM

256x8

Port 4

P4(2)

Watch

Dog

PCA

Timer2

CAN

CONTROLLER

10 bit

ADC

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Preliminary

4. Pin Configuration

T89C51CC02

VAREF

VAGND

VAVCC

P4.1/RxDC

P4.0/TxDC

P3.5/T1

P3.4/T0 P3.3/INT1 P3.2/INT0

P3.1/TxD P3.0/RxD

P4.0/ TxDC

P2.1 P3.7

P3.6 P3.5 / T1 P3.4 / T0

P3.3 / INT1

P2.1

P3.7

P3.6

4 5

6 7

SO28

9 10 11

12 13

VAGND

P4.1 / TxDC

VAVCC

432

5 6 7 8

PLCC-28

9 10 11

12131415161718

27 26

25 24

23 22 21 20

17 16

P1.2 / AN2 / ECI

P1.1 / AN1 / T2EX

P1.0 / AN 0 / T2

VAREF 1

282726

25 24 23 22 21 20 19

P1.0/

AN0/T2

P1.1/AN1/T2EX P1.2/AN2/ECI

P1.3/AN3/CEX0 P1.4/AN4/CEX1

P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0

RESE

VSS VCC

XTAL1

XTAL2

P1.3 / AN3 / CEX0 P1.4 / AN4 / CEX1 P1.5 / AN5 P1.6 / AN6 P1.7 / AN7 P2.0 RESET

VSS

VCC

XTAL1

XTAL2

P3.1 / TxD

P3.0 / RxD

P3.2 / INT0

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T89C51CC02

Table 1. Pin Description

Pin Name Type Description

VSS GND Circuit ground potential.

VCC Supply voltage during normal, idle, and power-down operation. VAREF Reference Voltage for ADC VAVCC Supply Voltage for ADC

VAGND Reference Ground for ADC / Analog Ground

Port 1:

is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, on the datasheet) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCF register. As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O.

P1.0:7 I/O

P2.0:1 I/O

P3.0:7 I/O

P1.0 / AN0 / T2

Analog input channel 0, External clock input for Timer/counter2.

P1.1 / AN1 / T2EX

Analog input channel 1, Trigger input for Timer/counter2.

P1.2 / AN2 / ECI

Analog input channel 2, PCA external clock input.

PIn the T89C51CC02 Port 1 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

Port 2:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. In the T89C51CC02 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate. The secondary functions are assigned to the pins of port 3 as follows:

P3.0 / RxD:

Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1 / TxD:

Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2 / INT0:

External interrupt 0 input / timer 0 gate control input

P3.3 / INT1:

External interrupt 1 input / timer 1 gate control input

P3.4 / T0:

Timer 0 counter input

P3.5 / T1:

Timer 1 counter input

P3.6

P3.7

In the T89C51CC02 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

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Preliminary

Pin Name Type Description

Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pullup transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function

P4.0:1 I/O

RESET I/O

XTAL1 I

XTAL2 O

to operate. The secondary functions are assigned to the two pins of port 4 as follows:

P4.0 / TxDC:

Transmitter output of CAN controller

P4.1 / RxDC:

Receiver input of CAN controller. In the T89C51CC02 Port 4 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

Reset:

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

XTAL2:

Output from the inverting oscillator amplifier.

T89C51CC02

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4.1. I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.

4.2. Port Structure

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either forgeneral-purpose I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=1,3 or 4). To use a pin for general purpose input, set the bit in the Px register. This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in "quasi-Bidirectional Port Operation" paragraph.

ALTERNATE OUTPUT

READ LATCH

INTERNAL BUS

WRITE TO LATCH

READ PIN

NOTE:

1. The internal pull-up can be disabled on P1 when analog function is selected.

Port.X LATCH

FUNCTION

ALTERNATE INPUT FUNCTION

Figure 1. Port Structure

VCC

INTERNAL PULL-UP (1)

Port.x

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4.3. Read-Modify-Write Instructions

Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read-Modifiy-Write" instructions. Below is a complete list of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:

Table 2. Read-Modify-Write Instructions

Instruction Description Example

ANL logical AND ANL P1, A ORL logical OR ORL P2, A XRL logical EX-OR XRL P3, A

JBC jump if bit = 1 and clear bit JBC P1.1, LABEL CPL complement bit CPL P3.0 INC increment INC P2

DEC decrement DEC P2

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These ReadModify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic)levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attemps by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.

4.4. Quasi-Bidirectional Port Operation

Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input condions by a logical one written to the latch.

NOTE:

Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-Modify-Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition see Figure. This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3.

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Preliminary

T89C51CC02

OUTPUT DATA

INPUT DATA

READ PIN

2 Osc. PERIODS

Figure 2. Internal Pull-Up Configurations

VCCVCCVCC

P1.x P2.x P3.x P4.x

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T89C51CC02

5. SFR Mapping

The Special Function Registers (SFRs) of the T89C51CC02 fall into the following categories:

Table 3. C51 Core SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word

SP 81h

DPL 82h

DPH 83h

Mnemonic Add Name 7 6 5 4 3 2 1 0

P1 90h Port 1 P2 A0h Port 2 (x2) P3 B0h Port 3 P4 C0h Port 4 (x2)

Stack Pointer LSB of SPX

Data Pointer Low byte LSB of DPTR

Data Pointer High byte MSB of DPTR

Table 4. I/O Port SFRs

Table 5. Timers SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

TH0 8Ch Timer/Counter 0 High byte TL0 8Ah Timer/Counter 0 Low byte TH1 8Dh Timer/Counter 1 High byte TL1 8Bh Timer/Counter 1 Low byte TH2 CDh Timer/Counter 2 High byte TL2 CCh Timer/Counter 2 Low byte TCON 88h Timer/Counter 0 and 1 control TMOD 89h Timer/Counter 0 and 1 Modes T2CON C8h Timer/Counter 2 control T2MOD C9h Timer/Counter 2 Mode

RCAP2H CBh

RCAP2L CAh

WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

- - - - - - T2OE DCEN

-----S2S1S0

Table 6. Serial I/O Port SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

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T89C51CC02

Table 7. PCA SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

CCON D8h PCA Timer/Counter Control CMOD D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low byte CH F9h PCA Timer/Counter High byte CCAPM0

CCAPM1 CCAP0H

CCAP1H CCAP0L

CCAP1L

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

FAh

PCA CompareCaptureModule0 H

FBh

PCA Compare Capture Module 1 H

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h Interrupt Enable Control 0 IEN1 E8h Interrupt Enable Control 1 IPL0 B8h Interrupt Priority Control Low 0 IPH0 B7h Interrupt Priority Control High 0 IPL1 F8h Interrupt Priority Control Low 1 IPH1 F7h Interrupt Priority Control High1

CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

CIDL WDTE - - - CPS1 CPS0 ECF

CCAP0H7 CCAP1H7

CCAP0L7 CCAP1L7

ECOM0 ECOM1

CCAP0H6 CCAP1H6

CCAP0L6 CCAP1L6

CAPP0 CAPP1

CCAP0H5 CCAP1H5

CCAP0L5 CCAP1L5

CAP0 CAP1

CCAP0H4 CCAP1H4

CCAP0L4 CCAP1L4

MAT0 MAT1

CCAP0H3 CCAP1H3

CCAP0L3 CCAP1L3

TOG0 TOG1

CCAP0H2 CCAP1H2

CCAP0L2 CCAP1L2

PWM0 PWM1

CCAP0H1 CCAP1H1

CCAP0L1 CCAP1L1

Table 8. Interrupt SFRs

EA AC ET2 ES ET1 EX1 ET0 EX0

- - - - - ETIM EADC ECAN

- PPC PT2 PS PT1 PX1 PT0 PX0

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

- - - - - POVRL PADCL PCANL

- - - - - POVRH PADCH PCANH

ECCF0 ECCF1

CCAP0H0 CCAP1H0

CCAP0L0 CCAP1L0

Table 9. ADC SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

ADCON F3h ADC Control ADCF F6h ADC Configuration ADCLK F2h ADC Clock ADDH F5h ADC Data High byte ADDL F4h ADC Data Low byte

- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

- - - PRS4 PRS3 PRS2 PRS1 PRS0

ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2

- - - - - - ADAT1 ADAT0

Table 10. CAN SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

CANGCON ABh CAN General Control

CANGSTA AAh CAN General Status CANGIT 9Bh CAN General Interrupt CANBT1 B4h CAN Bit Timing 1 CANBT2 B5h CAN Bit Timing 2 CANBT3 B6h CAN Bit Timing 3 CANEN CFh CAN Enable Channel byte CANGIE C1h CAN General Interrupt Enable

CANIE C3h

CAN Interrupt Enable Channel

byte CANSIT BBh CAN Status Interrupt Channel byte CANTCON A1h CAN Timer Control

CANTIMH ADh CAN Timer high

ABRQ OVRQ TTC SYNCTTC

- OVFG - TBSY RBSY ENFG BOFF ERRP

CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

- BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 -

- SJW1 SJW2 - PRS2 PRS1 PRS0 -

- PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

- - - - ENCH3 ENCH2 ENCH1 ENCH0

- - ENRX ENTX ENER ENBUF - -

- - - - IECH3 IECH2 IECH1 IECH0

- - - - SIT3 SIT2 SIT1 SIT0

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIM15CANTIM14CANTIM13CANTIM12CANTIM11CANTIM10CANTIM9CANTIM

AUT-

BAUD

TEST ENA GRES

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T89C51CC02

Mnemonic Add Name 7 6 5 4 3 2 1 0

CANTIML ACh CAN Timer low

CANSTMH AFh CAN Timer Stamp high

CANSTML AEh CAN Timer Stamp low

CANTTCH A5h CAN Timer TTC high

CANTTCL A4h CAN Timer TTC low

CANTEC 9Ch CAN Transmit Error Counter CANREC 9Dh CAN Receive Error Counter CANPAGE B1h CAN Page CANSTCH B2h CAN Status Channel CANCONH B3h CAN Control Channel CANMSG A3h CAN Message Data

CANIDT1 BCh

CANIDT2 BDh

CANIDT3 BEh

CANIDT4 BFh

CANIDM1 C4h

CANIDM2 C5h

CANIDM3 C6h

CANIDM4 C7h

CAN Identifier Tag byte 1(Part A) CAN Identifier Tag byte 1(PartB)

CAN Identifier Tag byte 2 (PartA) CAN Identifier Tag byte 2 (PartB)

CAN Identifier Tag byte 3(PartA) CAN Identifier Tag byte 3(PartB)

CAN Identifier Tag byte 4(PartA) CAN Identifier Tag byte 4(PartB)

CAN Identifier Mask byte 1(PartA) CAN Identifier Mask byte 1(PartB)

CAN Identifier Mask byte 2(PartA) CAN Identifier Mask byte 2(PartB)

CAN Identifier Mask byte 3(PartA) CAN Identifier Mask byte 3(PartB)

CAN Identifier Mask byte 4(PartA) CAN Identifier Mask byte 4(PartB)

CANTIM7CANTIM6CANTIM5CANTIM4CANTIM3CANTIM2CANTIM1CANTIM

TIMSTMP15TIMSTMP14TIMSTMP13TIMSTMP12TIMSTMP11TIMSTMP10TIMSTMP9TIMSTMP

TIMSTMP7TIMSTMP6TIMSTMP5TIMSTMP4TIMSTMP3TIMSTMP2TIMSTMP1TIMSTMP

TIMTTC15TIMTTC14TIMTTC13TIMTTC12TIMTTC11TIMTTC10TIMTTC9TIMTTC

TIMTTC7TIMTTC6TIMTTC5TIMTTC4TIMTTC3TIMTTC2TIMTTC1TIMTTC

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

- - CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

DLCW TXOK RXOK BERR SERR CERR FERR AERR

CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0 IDT10

IDT28

IDT2

IDT20

IDT12-IDT11-IDT10-IDT9

IDT4

IDMSK10 IDMSK28

IDMSK2

IDMSK20

IDMSK12-IDMSK11-IDMSK10-IDMSK9-IDMSK8-IDMSK7-IDMSK6-IDMSK5

IDMSK4-IDMSK3-IDMSK2-IDMSK1-IDMSK0

IDT9

IDT27

IDT1

IDT19

IDT3

IDMSK9

IDMSK27

IDMSK1

IDMSK19

IDT8

IDT26

IDT0

IDT18-IDT17-IDT16-IDT15-IDT14-IDT13

IDT2-IDT1

IDMSK8

IDMSK26

IDMSK0

IDMSK18-IDMSK17-IDMSK16-IDMSK15-IDMSK14-IDMSK13

IDT7

IDT25

IDMSK7

IDMSK25

IDT6

IDT24

IDT8

IDT0

IDMSK6

IDMSK24

IDT5

IDT23

IDT7

RTRTAG

IDMSK5

IDMSK23

RTRMSK - IDEMSK

IDT4

IDT22

IDT6

RB1TAG

IDMSK4

IDMSK22

IDT3

IDT21

IDT5

RB0TAF

IDMSK3

IDMSK21

Table 11. Other SFRs

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87hh Power Control AUXR1 A2h Auxiliary Register 1 CKCON 8Fh Clock Control FCON D1h FLASH Control EECON D2h EEPROM Contol

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

- - ENBOOT - GF3 - - DPS

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

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Table 12. SFR’s mapping

(1)

0/8

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

Note:

2. These registers are bit-addressable.

IPL1

xxxx x000CH0000 0000

0000 0000

IEN1

xxxx x000CL0000 0000

ACC

0000 0000

CCON

00xx xx00

PSW

0000 0000

T2CON

0000 0000

xxxx xx11

IPL0

x000 0000

1111 1111

IEN0

0000 0000

xxxx xx11

SCON

0000 0000

1111 1111

TCON

0000 0000

(1)

0/8

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

1/9 2/A 3/B 4/C 5/D 6/E 7/F

CCAP0H

0000 0000

ADCLK

xx00 0000

CCAP0L

0000 0000

CMOD

00xx x000

FCON

0000 0000

T2MOD

xxxx xx00

CANGIE

0000 0000

SADEN

0000 0000

CANPAGE

0000 0000

SADDR

0000 0000

CANTCON

0000 0000

SBUF

0000 0000

TMOD

0000 0000

0000 0111

1/9 2/A 3/B 4/C 5/D 6/E 7/F

CCAPM0

x000 0000

EECON

xxxx xx00

RCAP2L

0000 0000

CANSTCH

xxxx xxxx

CANGSTA

x0x0 0000

AUXR1

0000 0000

TL0

0000 0000

DPL

0000 0000

CCAP1H

0000 0000

ADCON

x000 0000

CCAP1L

0000 0000

CCAPM1

x000 0000

RCAP2H

0000 0000

CANIE2 xxx 0000

CANSIT2

xxxx 0000

CANCONCH

xxxx xxxx

CANGCON

0000 x000 CANMSG

xxxx xxxx

CANGIT

0x00 0000

TL1

0000 0000

DPH

0000 0000

ADDL

0000 0000

TL2

0000 0000

CANIDM1

xxxx xxxx CANIDT1

xxxx xxxx

CANBT1

xxxx xxxx

CANTIML

0000 0000

CANTTCL

0000 0000

CANTEC

0000 0000

TH0

0000 0000

ADDH

0000 0000

TH2

0000 0000

CANIDM2

xxxx xxxx CANIDT2

xxxx xxxx

CANBT2

xxxx xxxx

CANTIMH

0000 0000

CANTTCH

0000 0000

CANREC

0000 0000

TH1

0000 0000

ADCF

0000 0000

CANIDM3

xxxx xxxx CANIDT3

xxxx xxxx

CANBT3

xxxx xxxx

CANSTMPL

0000 0000 WDTRST

1111 1111

IPH1

xxxx x000

CANEN2

xxxx 0000

CANIDM4

xxxx xxxx CANIDT4

xxxx xxxx

IPH0

x000 0000

CANSTMPH

0000 0000 WDTPRG

xxxx x000

CKCON

0000 0000

PCON

0000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

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6. Clock

6.1. Introduction

The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.

• Saves power consumption while keeping the same CPU power (oscillator power saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software.

An extra feature is available for selected hardware in the X2 mode. This feature allows starting of the CPU in the X2 mode, without starting in the standard mode.

The hardware CPU X2 mode can be read and write via IAP (SetX2mode, ClearX2mode, ReadX2mode), see InSystem Programming section.

These IAPs are detailed in the "In-System Programming" section.

6.2. Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 4 shows the mode switching waveforms.

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XTAL1

XTAL2

÷ 2

PCON.1

CKCON.0

X2B

Hardware byte

÷ 2

1 0

÷ 2

1 0

÷ 2

PCON.0

IDL

CPU Core Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

1 0

FT0 Clock

FT1 Clock

FT2 Clock

FUart Clock

FPca Clock

FWd Clock

FCan Clock

PERIPH

CKCON.0

CLOCK

Peripheral Clock Symbol

CANX2

CKCON.7

WDX2

CKCON.6

PCAX2

CKCON.5

SIX2

CKCON.4

T2X2

CKCON.3

T1X2

CKCON.2

T0X2

CKCON.1

Figure 3. Clock CPU Generation Diagram

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XTAL1

XTAL2

X2 bit

CPU clock

X2 ModeSTD Mode STD Mode

Figure 4. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 5) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.

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6.3. Register

CKCON (S:8Fh)

Clock Control Register

7 6 5 4 3 2 1 0

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit Number Bit Mnemonic Description

CAN clock (1)

7 CANX2

6 WDX2

5 PCAX2

4 SIX2

3 T2X2

2 T1X2

1 T0X2

0X2

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Watchdog clock (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2) (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer1 clock (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer0 clock (1)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Settoselect 6 clock periodspermachinecycle (X2 mode) andtoenablethe individual peripherals"X2"bits.

NOTE:

1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.

Reset Value = 0000 0000b

Figure 5. CKCON Register

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7. Program/Code Memory

7.1. Introduction

The T89C51CC02 implement 16 Kbytes of on-chip program/code memory. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the FLASH Memory can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool.

3FFFh

16 Kbytes

FLASH

0000h

Figure 6. Program/Code Memory Organization

T89C51CC02

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7.2. FLASH Memory Architecture

T89C51CC02 features two on-chip flash memories:

• Flash memory FM0:

containing 16 Kbytes of program memory (user space) organized into 128 byte pages,

• Flash memory FM1:

2 Kbytes for boot loader and Application Programming Interfaces (API).

The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section.

All Read/Write access operations on FLASH Memory by user application are managed by a set of API described in the "In-System Programming" section.

Hardware Security (1 byte)

Extra Row (128 bytes)

Column Latches (128 bytes)

3FFFh

16 Kbytes

Flash memory

user space

FM0

0000h

Figure 7. Flash memory architecture

7.2.1. FM0 Memory Architecture

The flash memory is made up of 4 blocks (see Figure 7):

1. The memory array (user space) 16 Kbytes

2. The Extra Row

3. The Hardware security bits

4. The column latch registers

2 Kbytes

Flash memory

boot space

FM1

FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register

FFFFh

F800h

7.2.1.1. User Space

This space is composed of a 16 Kbytes FLASH memory organized in 128 pages of 128 bytes. It contains the user’s application code.

7.2.1.2. Extra Row (XRow)

This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage.

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7.2.1.3. Hardware security space

The Hardware security space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode.

7.2.1.4. Column latches

The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte).

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7.3. Overview of FM0 operations

The CPU interfaces to the flash memory through the FCON register and AUXR1 register. These registers are used to:

• Map the memory spaces in the adressable space

• Launch the programming of the memory spaces

• Get the status of the flash memory (busy/not busy)

• Select the flash memory FM0/FM1.

7.3.1. Mapping of the memory space

By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting this bit takes precedence on the EXTRAM bit in AUXR register.

The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 13. A MOVC instruction is then used for reading these spaces.

Table 13. .FM0 blocks select bits

FMOD1 FMOD0 FM0 Adressable space

0 0 User (0000h-3FFFh) 0 1 Extra Row(FF80h-FFFFh) 1 0 Hardware Security (0000h) 1 1 reserved

7.3.2. Launching programming

FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A. Table 14 summarizes the memory spaces to program according to FMOD1:0 bits.

Table 14. Programming spaces

User

Extra Row

Security Space

Reserved

Write to FCON

FPL3:0 FPS FMOD1 FMOD0

5 X 0 0 No action

A X 0 0 Write the column latches in user space

5 X 0 1 No action

A X 0 1 Write the column latches in extra row space

5 X 1 0 No action

A X 1 0 Write the fuse bits space

5 X 1 1 No action

A X 1 1 No action

Operation

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The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is no more available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle mode. Exit is automatically performed at the end of programming.

Caution:

Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode.

7.3.3. Status of the flash memory

The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress.

7.3.4. Selecting FM1/FM1

The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h.

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7.3.5. Loading the Column Latches

Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page.

The following procedure is used to load the column latches and is summarized in Figure 8:

• Map the column latch space by setting FPS bit.

• Load the DPTR with the address to load.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• If needed loop the three last instructions until the page is completely loaded.

Column Latches

Column Latches Mapping

Figure 8. Column Latches Loading Procedure

FPS= 1

Data Load

DPTR= Address

ACC= Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Data memory Mapping

FPS= 0

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7.3.6. Programming the FLASH Spaces

User

The following procedure is used to program the User space and is summarized in Figure 9:

• Load data in the column latches from address 0000h to 3FFFh

• Disable the interrupts.

• Launch the programming by writing the data sequence 50h followed by A0h in FCON register.

The end of the programming indicated by the FBUSY flag cleared.

• Enable the interrupts.

Note:

1. The last page address used when loading the column latch is the one used to select the page programming address.

Extra Row

The following procedure is used to program the Extra Row space and is summarized in Figure 9:

• Load data in the column latches from address FF80h to FFFFh.

• Disable the interrupts.

• Launch the programming by writing the data sequence 52h followed by A2h in FCON register.

The end of the programming indicated by the FBUSY flag cleared.

• Enable the interrupts.

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FLASH Spaces

Programming

Column Latches Loading

see Figure 8

Disable IT

EA= 0

Launch Programming

FCON= 5xh FCON= Axh

FBusy

Cleared?

Erase Mode

FCON = 00h

End Programming

Enable IT

EA= 1

Figure 9. Flash and Extra row Programming Procedure

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Hardware Security

The following procedure is used to program the Hardware Security space and is summarized in Figure 10:

• Set FPS and map Harware byte (FCON = 0x0C)

• Disable the interrupts.

• Load DPTR at address 0000h.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• Launch the programming by writing the data sequence 54h followed by A4h in FCON register.

The end of the programming indicated by the FBusy flag cleared.

• Enable the interrupts.

FLASH Spaces

Programming

FCON = 0Ch

Data Load

DPTR= 00h ACC= Data

Exec: MOVX @DPTR, A

Disable IT

EA= 0

Launch Programming

FCON= 54h FCON= A4h

FBusy

Cleared?

Erase Mode

FCON = 00h

End Programming

Enable IT

EA= 1

Figure 10. Hardware Programming Procedure

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7.3.7. Reading the FLASH Spaces

User

The following procedure is used to read the User space and is summarized in Figure 11:

• Map the User space by writing 00h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to FFFFh.

Extra Row

The following procedure is used to read the Extra Row space and is summarized in Figure 11:

• Map the Extra Row space by writing 02h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= FF80h to FFFFh.

Hardware Security

The following procedure is used to read the Hardware Security space and is summarized in Figure 11:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h.

FLASH Spaces

Reading

FLASH Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

Exec: MOVC A, @A+DPTR

Figure 11. Reading Procedure

ACC= 0

Erase Mode

FCON = 00h

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7.4. Registers

FCON (S:D1h)

FLASH Control Register

7 6 5 4 3 2 1 0

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

Bit Number Bit Mnemonic Description

7-4 FPL3:0

3 FPS

2-1 FMOD1:0

0 FBUSY

Reset Value= 0000 0000b

Programming Launch Command Bits

Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 14.)

FLASH Map Program Space

Set to map the column latch space in the data memory space. Clear to re-map the data memory space.

FLASH Mode

See Table 13 or Table 14.

FLASH Busy

Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be cleared by software.

Figure 12. FCON Register

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8. Data Memory

8.1. Introduction

The T89C51CC02 provides data memory access in two different spaces:

1. The internal space mapped in three separate segments:

• the lower 128 bytes RAM segment.

• the upper 128 bytes RAM segment.

• the expanded 256 bytes RAM segment (ERAM).

A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 13 shows the internal data memory spaces organization.

FFh

256 bytes

Internal ERAM

00h

FFh

80h 80h

7Fh

00h

Upper

128 bytes

Internal RAM

indirect addressing

Lower

128 bytes

Internal RAM

direct or indirect

addressing

Figure 13. Internal Data Memory Organization

FFh

Special

Function

Registers

direct addressing

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8.2. Internal Space

8.2.1. Lower 128 Bytes RAM

The lower 128 bytes of RAM (see Figure 13) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 16) select which bank is in use according to Table 15. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines.

Table 15. Register Bank Selection

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h 0 1 Register bank 0 from 08h to 0Fh 1 0 Register bank 0 from 10h to 17h 1 1 Register bank 0 from 18h to 1Fh

The next 16 bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.

7Fh

30h

20h 18h 10h 08h 00h

2Fh

Bit-Addressable Space (Bit Addresses 0-7Fh)

1Fh 17h

4 Banks of 8 Registers

0Fh

R0-R7

07h

Figure 14. Lower 128 bytes Internal RAM Organization

8.2.2. Upper 128 Bytes RAM

The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode.

8.2.3. Expanded RAM

The on-chip 256 bytes of expanded RAM (ERAM) are accessible from address 0000h to FFh using indirect addressing mode through MOVX instructions.

Caution:

Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.

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8.3. Dual Data Pointer

8.3.1. Description

The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 17) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 15).

DPL0 DPL1

DPTR0

DPTR1

DPH0 DPH1

0 1

DPS

0 1

DPL

AUXR1.0

DPH

DPTR

Figure 15. Dual Data Pointer Implementation

8.3.2. Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search …) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. Latest C compiler take also advantage of this feature by providing enhanced algorithm libraries. The INC instruction is a short (2 bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added

AUXR1 EQU 0A2h

move: mov DPTR,#SOURCE ; address of SOURCE

inc AUXR1 ; switch data pointers mov DPTR,#DEST ; address of DEST

mv_loop: inc AUXR1 ; switch data pointers

movx A,@DPTR ; get a byte from SOURCE inc DPTR ; increment SOURCE address inc AUXR1 ; switch data pointers movx @DPTR,A ; write the byte to DEST inc DPTR ; increment DEST address jnz mv_loop ; check for NULL terminator

end_move:

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