Rainbow Electronics T89C51AC2 User Manual

1. Features

• 80C51 core architecture:
– 256 bytes of on-chip RAM
– 1 Kbytes of on-chip ERAM
– 32 Kbytes of on-chip Flash memory

Data Retention: 10 years at 85°C

Read/Write cycle: 10k
– 2 Kbytes of on-chip Flash for Bootloader
– 2 Kbytes of on-chip EEPROM

Read/Write cycle: 100k
– 14-sources 4-level interrupts
– Three 16-bit timers/counters
– Full duplex UART compatible 80C51
– Maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)
– Five ports: 32 + 2 digital I/O lines
– Five-channel 16-bit PCA with:

PWM (8-bit)
High-speed output

Timer and edge capture
– Double Data Pointer
– 21-bit watchdog timer (7 programmable bits)

• A 10-bit r esolution analog to digitalconverter (ADC) with 8 m ultiplexed inputs

• On-chip emulation Logic (enhanced Hook system)

• Power saving modes:
– Idle mode
– Power down mode

• Power supply: 5V +/- 10% (or 3V** +/- 10%)

• Temperature range: Industrial (-40° to +85°C)

• Packages: TQFP44, PLCC44

Note:

* AtB RP = 1 sampling p oint will be fixed.
** Askfor availability

Enhance d 8-bit
MCU with A/D
Converter and
32 Kbytes

T89C51AC2

2. Description

The T89C51AC2 is a high performance FLASH version of the 80C51 single chip 8-bit
microcontrollers. It contains a 32Kbyte Flash memory block for program and data.

The 32K byte FLASH memory can be programmed either in parallel mod e or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard V CC pin.

The T89C51AC2 retains all feat ures of the 80C52 with 256 bytes of internal RAM, a 7­source 4-level interrupt controller and three timer/counters. In addition, the
T89C51AC2 has a 10 bit A/D converter, a 2Kbytes Boot Flash memory, 2 Kbyte
EEPROM for data, a Programm able Counter Array, an XRAM of 1024 bytes, a Hard­ware Watchdog Timer and a more versatile serial channel that facilitates
multiprocessor communication (EUART).The fully static design of the T89C51AC2
allows to reduc e system power consumption by bringing the clock frequency down to
any value, even DC, without loss of data.

The T89C51AC2 has 2 software-selectable modes of reduced activity and an 8 bit
clock prescaler for f urther reduction in power consumption. In the idle mode the CPU
is frozen while the pe ripherals and the interrupt system are still operating. In the
power-down mode the RAM is saved and all other functions are inoperative.

Rev. B – 19-Dec-01

1

3. Block Diagram

The added features of the T89C51AC2 mak e it more powerful f or applications that need
A/D conversion, pulse width modulation, high spee d I/O and counting capabilities such
as industrial control, consumer goods, alarms, motor control, etc.

While remaining fully compatible with the 80C52 it offers a superset of this standard
microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns
cycle time.

PCA

RxD

TxD

Vss

Vcc

ECI

T2EX

T2

XTAL1
XTAL2

ALE

PSEN

EA

RD

WR

CPU

T0

C51

CORE

T1

RAM

256x8

INT
Ctrl

INT0

UART

Timer 0
Timer 1

RESET

Flash

Boot

32kx

loader

8

2kx8

IB-bus

Parallel I/O Ports & Ext. Bus

Port 0P0Port 1

INT1

(1): 8 analog Inputs / 8 Digital I/O
(2): 2-BitI/O Port

Port 2

P1(1)

EE

PROM

2kx8

P2

Port 3

ERAM

1kx8

Port 4

P3

PCA

Timer2

Emul

Watch

P4(2)

Dog

Unit

10 bit

ADC

2

T89C51AC2

Rev. B – 19-Dec-01

4. Pin Configuration

P1.4 / AN4 / CEX1
P1.5 / AN5 / CEX2
P1.6 / AN6 / CEX3
P1.7 / AN7 / CEX4

EA

P3.0/ RxD

P3.1 / TxD
P3.2 / INT0
P3.3 / INT1

P3.4 / T0
P3.5 / T1

7
8
9
10
11
12
13
14
15
16
17

P1.3 / AN3 / CEX0

P1.2 / A N2 / ECI

P1.1 / AN1 / T2EX

P1.0 / AN 0 / T2

65432

PLCC44

VAREF

VAGND

RESET

1

4443424140

T89C51AC2

VSS

VCC

XTAL1

XTAL2

39

ALE

38

PSEN

37

P0.7 / AD7

36

P0.6 / AD6

35

P0.5 / AD5

34

P0.4 / AD4

33

P0.3 / AD3

32

P0.2 / AD2

31

P0.1 / AD1

30

P0.0 / AD0

29

P2.0 / A8

P1.4 / AN4 / CEX1
P1.5 / AN5 / CEX2
P1.6 / AN6 / CEX3
P1.7 / AN7 / CEX4

EA

P3.0 / RxD

P3.1 / TxD
P3.2 / INT0
P3.3 / INT1

P3.4/ T0
P3.5/ T1

1819202122232425262728

P4.1

P4.0

P3.7/ RD

P3.6 / WR

P1.3 / AN3 / CEX0

P1.2 / AN2 / ECI

P1.1 / AN1 / T2EX

43 42 41 40 3944

1
2
3

4
5
6
7

8

9
10
11

P2.6/ A14

P2.7 / A15

P1.0/ AN0 /T2

VAREF

VAGND

38 37 36 35 34

TQFP44

P2.5/ A13

RESET

VSS

12 13 17161514 201918 21 22

P2.4/ A12

P2.1 / A9

P2.3/ A11

P2.2/ A10

VCC

XTAL1

XTAL2

33

ALE

32

PSEN

31

P0.7 / AD7

30

P0.6 / AD6

29

P0.5 / AD5

28

P0.4 /AD4

27

P0.3 /AD3

26

P0.2 /AD2

25

P0.1 /AD1

24

P0.0 /AD0

23

P2.0 / A8

Rev. B – 19-Dec-01

P4.1

P4.0

P3.7 / RD

P3.6 / WR

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.1 / A9

P2.3 / A11

P2.2 / A10

3

Table 1. Pin Description

Pin Name Type Description

VSS GND Circuit ground.
VCC Supply Voltage.

VAREF Reference Voltage for ADC

VAGND Reference Groundfor ADC

Port 0:

Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used

P0.0:7 I/O

P1.0:7 I/O

as high-impedance inputs. Port 0 is also the multiplexedlow-orderaddress and databus during accessestoexternal
Program and Data Memory.Inthis applicationitusesstrong internal pull-ups whenemitting 1’s.
Port 0 also outputs thecodebytes duringprogram validation. External pull-ups are required during program
verification.

Port 1:

Is an 8-bit bi-directional I/O portwith internalpull-ups. Port 1 pins can be used fordigitalinput/output or as analog
inputs for the AnalogDigitalConverter( ADC). Port 1 pins that have1’s written to them are pulled high by the internal
pull-uptransistors andcanbe used as inputs inthis state.Asinputs,Port1pins thatare beingpulled lowexternally will
be the source of current (I
assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disco nnected).
As a secondarydigitalfunction,port 1 containstheTimer 2 external trigger and clock input; the PCA external clock
input and the PCA module I/O.

P1.0 / AN0 / T2
Analoginput channel 0,
External clock input for Timer/counter2.

P1.1 / AN1 / T2EX
Analoginput channel 1,
Trigger inputfor Timer/counter2.

P1.2 / AN2 / ECI
Analoginput channel 2,
PCA external clock input.

P1.3 / AN3 / CEX0
Analoginput channel 3,
PCA module 0 Entry of input/PWM output.

P1.4 / AN4 / CEX1
Analoginput channel 4,
PCA module 1 Entry of input/PWM output.

P1.5 / AN5 / CEX2
Analoginput channel 5,
PCA module 2 Entry of input/PWM output.

P1.6 / AN6 / CEX3
Analoginput channel 6,
PCA module 3 Entry of input/PWM output.

P1.7 / AN7 / CEX4
Analoginput channel 7,
PCA module 4 Entry ot input/PWM output.
Port 1 receives the low-order address byte during EPROM programming and program verification.

It can drive CMOS inputs without external pull-ups.

, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are

IL

4

T89C51AC2

Rev. B – 19-Dec-01

Pin Name Type Description

Port 2:

Is an 8-bit bi-directional I/O portwith internalpull-ups. Port 2 pins thathave1’s writtento them are pulled high by the
internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will

P2.0:7 I/O

P3.0:7 I/O

be a source of current (I
high-order address byte during accessestotheexternalProgram Memory and during accesses to external Data
Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting
1’s. During accesses to externalData Memory thatuse8bit addresses (MOVX@Ri), Port 2 transmits the contents of
theP2specialfunctionregister.
It also receives high-order addresses and control signals during program validation.
It can drive CMOS inputs without external pull-ups.

Port 3:

Is an 8-bit bi-directional I/O portwith internalpull-ups. Port 3 pins thathave1’s writtento them are pulled high by the
internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low
externally will be a source of current (I
The outputlatch correspondingtoa secondary functionmustbeprogrammedtoone for that function to operate
(exceptforTxD and WR

P3.0 / RxD:
Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1 / TxD:
Transmitter data output(asynchronous)or clock output (synchronous) of the serialinterface

P3.2 / INT0
External interrupt 0 input / timer 0 gate control input

P3.3 / INT1
External interrupt 1 input / timer 1 gate control input

P3.4 / T0:
Timer0 counter input

P3.5 / T1:
Timer1 counter input

P3.6 / WR
External Data Memorywrite strobe; latches the databytefrom port 0 into the external data memory

P3.7 / RD
External Data Memory read strobe; Enables the external data memory.
It can drive CMOS inputs without external pull-ups.

:

:

:

:

, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the

IL

, see section"Electrical Characteristic") because of the internalpull-ups.

IL

). The secondary functions are assigned to the pins of port 3 as follows:

T89C51AC2

P4.0:1 I/O

Rev. B – 19-Dec-01

Port 4:

Is an 2-bit bi-directional I/O portwith internalpull-ups. Port 4 pins thathave1’s writtento them are pulled high by the
internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will
be a source of current (IIL,on thedatasheet)because of the internalpull-uptransistor.

P4.0
P4.1:
It can drive CMOS inputs without external pull-ups.

5

Pin Name Type Description

Reset:

RESET I/O

ALE O

PSEN O

EA I

XTAL1 I

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull­down resistor to VSS permits power-on resetusing onlyan external capacitortoVCC.

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The
ALE is activated every1/6 oscillatorperiods (1/3 in X2 mode) except during an external datamemory access.When
instructions areexecuted from an internal FLASH (EA

PSEN

:

The Program Store Enableoutput is a controlsignal that enablesthe external program memoryofthe bus during
external fetch operations.Itisactivated twice each machine cycle during fetches fromthe external programmemory.
However,whenexecutingfrom of the externalprogram memory two activationsofPSENareskipped during each
access to the external Data memory. The PSEN is not activated for internal fetches.

EA

:

When External Access is held at the high level, instructions are fetched from the internal FLASH when the program
counterislessthen 8000H. When held at thelowlevel,T89C51AC2fetches allinstructions from theexternal program
memory

.

XTAL1:

Input of theinvertingoscillatoramplifier and input of theinternal clockgenerator circuits.
To drivethedevice fromanexternalclock source,XTAL1should be driven, while XTAL2isleft unconnected.To
operateabove a frequency of 16 MHz, a duty cycleof50%should be maintained.

= 1), ALE generation can be disabled by the software.

XTAL2 O

XTAL2:

Output from the inverting oscillator amplifier.

4.1 I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "wri te to latch" signal initiates transfer of internal bus data into the type-D latch. A
CPU "read latch" signal tr ans f ers the latched Q output onto the internal bus. Similarly, a
"read pin" signal transfers the logical level of the Port pin. Some Port data instructio ns
activate the "read latch" signal while others activate the "read pin" signal. Latch instruc­tions are referred to as Read-Mo dify-W rite instru ctions . Each I/O line may be
independently programm ed as input or output.

4.2 Port 1, Port 3 and Port 4

Figure 1 shows the structure of Port s 1 and 3, which ha ve internal pull-ups. An external
source can pull the pin low. Each Port pin can be configured either for general purpose
I/O or for its alternate input output func tion.

To use a pin for general purpose output, set or clear the corresponding bit in the Px reg­ister (x=1,3 or 4). To use a pin for general purpose input, set the bit in the Px regist er.
This turns off the output FET drive.

To configure a pi n for its alternate function, set the bit in the Px regist er. When the latch
is set, the "alternate output function" signal controls the output level (see Figure 1). The
operation of Port s 1, 3 and 4 is discussed further in "quasi-Bidirectional Port Operation"
paragraph.

6

T89C51AC2

Rev. B – 19-Dec-01

Figure 1. Port 1, Port 3 and Port 4 Structure

T89C51AC2

VCC

READ
LATCH

ALTERNATE
OUTPUT
FUNCTION

INTERNAL
PULL-UP (1)

P1.x
P3.x

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

CL

P3.X
P4.X

LATCH

QP1.X

ALTERNATE
INPUT
FUNCTION

P4.x

Note: The internal pull-up can be disabled on P1 when analog function is selected.

4.3 Port 0 and Port2 P ort s 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from t he other Ports in not having internal pull-ups. Figure 3
shows the structure of Port 2. An external source can pul l a Port 2 pin low.

To use a pin for general-purpose output, set or c lear the corresponding bit in t he Px reg­ister ( x =0 or 2). To us e a pin for general purpose input, set the bit in the Px regist er to
turn off the output driver FET.

Figure 2. Port 0 Structure

READ
LATCH

ADDRESS LOW/
DATA

CONTROL

VDD

(2)

P0.x (1)

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

P0.X

LATCH

Q

1
0

Notes: 1. Port 0 is precluded from use as general purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internalstrong pull-upsassist the logic-one output for memory bus cycles only.
Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

Rev. B – 19-Dec-01

7

Figure 3. Port 2 Structure

READ
LATCH

INTERNAL
BUS

WRITE
TO
LATCH

READ
PIN

D

P2.X

LATCH

ADDRESS HIGH/

Q

CONTROL

1
0

Notes: 1. Port 2 is precluded from use as general purpose I/O Por ts when as address/data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
memory bus cycle.

VDD

INTERNAL
PULL-UP (2)

P2.x (1)

When Port 0 and Port 2 are used for an ext ernal memo ry cycle, an internal control signal
switches the output-driver input from t he latch output to the internal address/data line.

4.4 Read-Modify-Write Instructions

Some inst ructions read the latch da ta rather than the pin data. The latch ba se d instruc­tions read the data, modify th e data and t hen rewrite the latch. These are called "Read­Modify-Write" instructions. Below is a complete list of these s pecial instructions (see
Table 2). When the destination operand is a Port o r a Port bit, thes e ins tructions read
the latch rather than the pin:

Table 2. Read-Modify-Write Instructions

Instruction Description Example

ANL logical AND ANL P1, A
ORL logical OR ORL P2, A
XRL logical EX-OR XRL P3, A
JBC jump if bit = 1 and clear bit JBC P1.1, LABEL
CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carrybitto bit y of Port x MOV P1.5,C

CLR Px.y clearbit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

8

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

It is not obvious the last three instructions in this list are Read-Modify-Write inst ructions.
These instructions read the port (all 8 bits), modify the specifically addressed bit and
write the new byte back to the latch. These Re ad-Modify-Write instructions are directed
to the latch rather than the pin in order to avoid possible misinterpretation of voltage
(and therefore, logic) levels at the pin. For example, a Port bit used to dri ve the base of
an external bipolar transistor can not rise above the transistor’s base-emitter junction
voltage (a value lower than VIL). With a logic one written to the bit, attempt s by the CPU
to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather
than the pins returns the correct logic-on e val ue.

4.5 Quasi-Bidirectional Port Operation

Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as
"quasi-bidirectional" Ports. When configured as an input, the pin im pedance appears as
logic one and sources current in response to an external logic zero condition. Port 0 is a
"true bidirectional" pin. The pins float when configured as inpu t. Resets write logic one to
all Port latches. If logical zero is subs equently written to a Port latch, it can be return ed
to input conditions by a logica l o ne written to the latch.

Note: Port latch values change near the end of Read-Modify-Write i nstruction cycles. O utput

buffers (and therefore t he pin state) update early in the instruction after Read-Modify­Write instructioncycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull­up (p1) to aid this logic transition (see Figure 4. ). This increases switch speed. This
extra pull-up sources 100 times normal inte rnal c ircuit current during 2 oscillato r clock
periods. The internal pull-ups are field-effect t ransistors rather than linear resistors. Pull­ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses
logical zero and off when the gate senses logical one. pFET #1 is turned on for two
oscillator periods immediately after a z ero-to-one transition in the Port latch. A logical
one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched
on whenever the a ssociated nFET is switched off. This is traditional CMOS switch con­vention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

2 Osc. PERIODS

VCCVCCVCC

Rev. B – 19-Dec-01

p1(1)

OUTPUT DATA

INPUT DATA

READ PIN

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

p2

n

p3

P1.x
P2.x
P3.x
P4.x

9

5. SFR Mapping The Special Function Registers (SFRs) of the T89C51AC2 fall into the following

categories:

Table 3. C51CoreSFRs

MnemonicAddName 76543210

ACC E0h Accumulator
BF0hBRegister
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer

Data Pointer Low

DPL 82h

DPH 83h

MnemonicAddName 76543210

P0 80h Port 0
P1 90h Port 1

byte
LSB of DPTR

Data Pointer High
byte

MSB of DPTR

Table 4. I/O Port SFRs

P2 A0h Port 2
P3 B0h Port 3
P4 C0h Port 4 (x2)

------

Table 5. TimersSFRs

MnemonicAddName 76543210

TH0 8Ch

TL0 8Ah

TH1 8Dh

TL1 8Bh

TH2 CDh

TL2 CCh

TCON 88h

Timer/Counter0High
byte

Timer/Counter 0 Low
byte

Timer/Counter1High
byte

Timer/Counter 1 Low
byte

Timer/Counter2High
byte

Timer/Counter 2 Low
byte

Timer/Counter 0 and
1 control

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h

10

T89C51AC2

Timer/Counter 0 and
1 Modes

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Rev. B – 19-Dec-01

T89C51AC2

MnemonicAddName 76543210

T2CON C8h

T2MOD C9h

RCAP2H CBh

RCAP2L CAh

WDTRST A6h

WDTPRG A7h

Timer/Counter 2
control

Timer/Counter 2
Mode

Timer/Counter 2
Reload/Capture High
byte

Timer/Counter 2
Reload/Capture Low
byte

WatchDog Timer
Reset

WatchDog Timer
Program

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

------T2OEDCEN

-----S2S1S0

Table 6. Serial I/O Port SFRs

MnemonicAddName 76543210

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADEN B9h SlaveAddress Mask
SADDR A9h Slave Address

Table 7. PCA SFRs

MnemonicAddName 76543210

CCON D8h

CMOD D9h

CL E9h

CH F9h

CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4

DAh
DBh
DCh
DDh
DEh

PCA Timer/Counter
Control

PCA Timer/Counter
Mode

PCA Timer/Counter
Low byte

PCA Timer/Counter
Highbyte

PCA Timer/Counter
Mode 0

PCA Timer/Counter
Mode 1

PCA Timer/Counter
Mode 2

PCA Timer/Counter
Mode 3

PCA Timer/Counter
Mode 4

CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

CIDL WDTE - - - CPS1 CPS0 ECF

ECOM0
ECOM1

-

ECOM2
ECOM3
ECOM4

CAPP0
CAPP1
CAPP2
CAPP3
CAPP4

CAPN0
CAPN1
CAPN2
CAPN3
CAPN4

MAT0
MAT1
MAT2
MAT3
MAT4

TOG0
TOG1
TOG2
TOG3
TOG4

PWM0
PWM1
PWM2
PWM3
PWM4

ECCF0
ECCF1
ECCF2
ECCF3
ECCF4

Rev. B – 19-Dec-01

11

MnemonicAddName 76543210

PCA Compare
Capture Module0 H

CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H

CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L

PCA Compare

FAh

Capture Module1 H

FBh

PCA Compare

FCh

Capture Module2 H

FDh

PCA Compare

FEh

Capture Module3 H
PCA Compare

Capture Module4 H
PCA Compare

Capture Module0 L
PCA Compare

EAh

Capture Module1 L

EBh

PCA Compare

ECh

Capture Module2 L

EDh

PCA Compare

EEh

Capture Module3 L
PCA Compare

Capture Module4 L

CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7

CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7

CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6

CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6

CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5

CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5

CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4

CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4

CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3

CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3

CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2

CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2

CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1

CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1

CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0

CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0

Table 8. Interrupt SFRs

MnemonicAddName 76543210

IEN0 A8h

IEN1 E8h

IPL0 B8h

IPH0 B7h

IPL1 F8h

IPH1 F7h

Interrupt Enable
Control 0

Interrupt Enable
Control 1

Interrupt Priority
Control Low 0

Interrupt Priority
Control High 0

Interrupt Priority
Control Low 1

Interrupt Priority
Control High1

EA EC ET2 ES ET1 EX1 ET0 EX0

------EADC-

- PPC PT2 PS PT1 PX1 PT0 PX0

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

------PADCL-

------PADCH-

Table 9. ADC SFRs

MnemonicAddName 76543210

ADCON F3h ADC Control - PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0
ADCF F6h ADC Co nf iguration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADCLK F2h ADC Clock - - - PRS4 PRS3 PRS2 PRS1 PRS0
ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2
ADDLF4hADCDataLowbyte------ADAT1ADAT0

12

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

Table 10. Other SFRs

MnemonicAddName 76543210

PCON 87h PowerControl SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 - - M0 - XRS1 XRS2 EXTRAM A0
AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS
CKCON 8Fh Clock Control - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
FCON D1h FLASH Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Rev. B – 19-Dec-01

13

0/8

Table 11. SFR’s mapping

(1)

1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

IPL1

xxxx x000

B

0000 0000

IEN1

xxxx x000

ACC

0000 0000

CCON

0000 0000

PSW

0000 0000

T2CON

0000 0000

P4

xxxx xx11

IPL0

x000 0000

P3

1111 1111

IEN0

0000 0000

CH

0000 0000

CL

0000 0000

CMOD

00xx x000

FCON

0000 0000

T2MOD

xxxx xx00

SADEN

0000 0000

SADDR

0000 0000

CCAP0H

0000 0000

ADCLK

xxx0 0000

CCAP0L

0000 0000

CCAPM0

x000 0000

EECON

xxxx xx00

RCAP2L

0000 0000

CCAP1H

0000 0000

ADCON

x000 0000

CCAP1L

0000 0000

CCAPM1

x000 0000

RCAP2H

0000 0000

CCAP2H

0000 0000

ADDL

0000 0000

CCAP2L

0000 0000

CCAPM2

x000 0000

TL2

0000 0000

CCAP3H

0000 0000

ADDH

0000 0000

CCAP3L

0000 0000

CCAPM3

x0000000

TH2

0000 0000

CCAP4H

0000 0000

ADCF

0000 0000

CCAP4L

0000 0000

CCAPM4

x0000000

IPH1

xxxx x000

IPH0

x000 0000

FFh

F7h

EFh

E7h

DF

h

D7h

CF

h

C7h

BFh

B7h

AFh

A0h

98h

90h

88h

80h

P2

1111 1111

SCON

0000 0000

P1

1111 1111

TCON

0000 0000

P0

1111 1111

(1)

0/8

AUXR1

xxxx 00x0

SBUF

0000 0000

TMOD

0000 0000

SP

0000 0111

1/9 2/A 3/B 4/C 5/D 6/E 7/F

TL0

0000 0000

DPL

0000 0000

TL1

0000 0000

DPH

0000 0000

TH0

0000 0000

TH1

0000 0000

WDTRST
1111 1111

AUXR

x00x 1100

Reserved

Notes: 1. These registers are bit-addressable.

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable.
The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit
addresses, in this area, are 0x80 through to 0xFF.

WDTPRG
xxxx x000

CKCON

0000 0000

PCON

00x1 0000

A7h

9Fh

97h

8Fh

87h

14

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

6. Clock The T 89C51AC2 core needs only 6 clock periods per machine cycle. This feature,

called”X2”, provides the following advantages:

• Divides frequency crystals by 2 (che aper cry stals) while keeping the same CPU
power.

• Saves power consum ption while keeping the same CPU power (oscillator power
saving).

• Saves power consum ption by dividing dynamic operating frequency by 2 in
operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
XTAL1 signal and the main clock i nput of the core (phase generat or). This divider may
be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be
enabled by a bit X 2B in the Hardware Security Byte. This bit is des c ribed in the section
"In-System Programming".

6.1 Description The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activat ed
(STD mode).

Setting this bit activates th e X2 featur e (X2 mod e) for the CPU Clock only (see Figure

5.).

The Timers 0, 1 and 2, Uart, P CA, or watchdog switch in X2 mode only if the corre­sponding bit is cleared in the C KCON register.

The clock for the whole circ uit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 t o 60%. Figur e 5. shows the cloc k generation block diagram. The X2
bit is validated on the XTAL1÷2 rising edge to av oid glitches when switching from the X2
to the STD mode. Figure 6 shows the mo de switching waveforms.

Rev. B – 19-Dec-01

15

Figure 5. Clock CPU Generation Diagram

XTAL1

XTAL2

PD

PCON.1

÷ 2

X2B

Hardware byte

X2

CKCON.0

÷ 2

1
0

On RESET

÷ 2

÷ 2

1
0

0
1

÷ 2

1
0

PCON.0

IDL

÷ 2

1
0

÷ 2

1
0

CPU Core
Clock

CLOCK

CPU Core Clock Symbol

and ADC

1
0

FT0 Clock

FT1 Clock

FT2 Clock

FUart Clock

FPca Clock

FWd Clock

CPU

16

CKCON.0

T89C51AC2

X2

WDX2

CKCON.6

PCAX2

CKCON.5

SIX2

CKCON.4

T2X2

CKCON.3

T1X2

CKCON.2

PERIPH

CLOCK

Peripheral Clock Symbol

T0X2

CKCON.1

Rev. B – 19-Dec-01

XTAL1

XTAL2

X2 bit

CPU clock

T89C51AC2

Figure 6. Mode Switching Waveforms

X2 ModeSTD Mode STD Mode

Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be

aware that all peripheralsusing the clock frequency as a time reference (UART, timers...)
will have their time reference divided by two. For example a free running timer generating
an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART wi th a
4800 baud rate will have a 9600 baud rate.

6.2 Register Table 12. CKCON Register

CKCON (S:8Fh)
Clock Control Register

76543210

- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number

6WDX2

5 PCAX2

4SIX2

3T2X2

2T1X2

Bit

Mnemonic Description

Watchdog clock (1)

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (1)

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2) (1)

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock (1)

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer1 clock (1)

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Rev. B – 19-Dec-01

Timer0 clock (1)

1T0X2

Clear to select 6 clock periodsper peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

17

Bit

Number

0X2

Bit

Mnemonic Description

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select6clockperiodspermachine cycle(X2 mode) and to enablethe
individual peripherals "X2"bits.

Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

18

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

7. Data Memory The T89C51AC2 pro vides data memory access in two different space s:

1. The internal space mapped in three separate segments:

• the lower 128 bytes RAM s egment.

• the upper 128 bytes RAM segment.

• the expanded 1024 bytes RAM s egment (ERAM).

2. The external space.

A fourth internal segment is avail able but ded icated to Speci al Function R egisters,
SFRs, (addresses 80h to

Figure 2 shows the internal and exte rn al data m emory spaces organization.

Figure 1. Internal memory - RAM

FFh) accessible by direct addressing mode.

FFh

128 bytes

Internal RAM

indirect addressing

80h

7Fh

128 bytes

Internal RAM

director indirect

00h

addressing

Upper

Lower

FFh

direct addressing

80h

Special

Function

Registers

Figure 2. Internal and External Data Memory Organization E RAM-XRAM

FFFFh

64 Kbytes

External XRAM

Rev. B – 19-Dec-01

256upto1024bytes

Internal ERAM

EXTRAM= 0

00h

Internal

FFh or 3FFh

EXTRAM= 1

0000h

External

19

7.1 Internal Space

7.1.1 Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 2) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks
of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Fig ure 3) select
which bank is in use according to Table 1. This allows more e fficient use of cod e space,
since register instructions are shorter than instructions that use dir ec t addressing, and
can be used for context switching in interrupt service routines .

Table 1. Register Bank Selection

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h
0 1 Register bank 0 from 08h to 0Fh
1 0 Register bank 0 from 10h to 17h
1 1 Register bank 0 from 18h to 1Fh

The next 16 bytes above the register banks form a block of bit-addressable memory
space. The C51 inst ruction set includes a wide selectio n of singl e-bit in s tructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7 Fh.

Figure 3. Lower 128 bytes Internal RAM Organi z ation

7Fh

30h

20h
18h
10h
08h
00h

2Fh

Bit-Addressable Space
(Bit Addresses 0-7Fh)

1Fh

17h

4 Banks of
8Registers

0Fh

R0-R7

07h

7.1.2 Upper 128 Bytes RAM The upper 128 bytes of RAM are accessible from address 80h to FFh us ing only indirect
addressing mode.

7.1.3 Expanded RAM The on-chip 1024 bytes of expanded RAM (ERAM) are ac c es s ible from addres s 0000h
to 03FFh using indirect addressing mode through MOVX instructions. I n this address
range, the bit EXTRAM in AUXR register is used to select the ERAM ( default) or the
XRAM. As s how n in Figure 2 wh en EX TRAM = 0 , the E RAM is se le cte d and wh en
EXTRAM= 1, the XRAM is selected.

The size of ERAM can be configured by XRS1-0 bit in AUXR register (default size is
1024 bytes).

20

Note: Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content i s indeterminate after power-up and
must then be initialized properly.

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

7.2 External Space

7.2.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD#, WR#, and ALE).
Figure 4 shows the structure of the external address bus. P0 carries address A7:0 while

P2 carries address A1 5:8. Data D 7:0 is multiple xe d with A7:0 on P0. Table 2 describes
the external memory interface signals.

Figure 4. External Data Memory Interface Structure

T89C51AC2

ALE

WR#

P2

P0

AD7:0

A15:8

Latch

A7:0

RAM

PERIPHERAL

A15:8

A7:0

D7:0
OERD#

WR

Table 2. External Data Memory Interface Signals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external
memory.

Address Latch Enable

ALE signals indicates that valid address information are available
on lines AD7:0.

Alternative

Function

P2.7:0

P0.7:0

-

RD# O

WR# O

Read

Read signal output to external data memory.

Write

Write signal output to external memory.

P3.7

P3.6

7.2.2 External Bus Cycles This section describes the bus cycles th e T89C51AC2 executes to read (see Figure 5),
and write data (see Figure 6) in the external data m emory.
External m emory cycle takes 6 CPU c lock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor­mation on X2 mode.

Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and
WR# signals from 3 to 15 CPU clock periods.

21

Rev. B – 19-Dec-01

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized
form and do not provide precise timing information. For bus cycle timing parameters
refer to the Section “AC Characteristics” of the T89C51AC2 datasheet.

Figure 5. External Data Read Waveforms

CPU Clock

ALE

RD#1

P0

P2

Notes: 1. RD# signal may be stretched using M0 bit in AUXR register.

P2

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

DPL or Ri D7:0

DPH or P22

Figure 6. External Data Write Waveforms

CPU Clock

ALE

WR#1

P0

P2

P2

DPL or Ri D7:0

DPH or P22

22

Notes: 1. WR# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

7.3 Dual Data Pointer The T89C51AC2 implements a second data pointer for speeding up code execution and

reducing code size in case of intens ive usage of external memory accesses.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR
addresses 83h and 84h that are the DPH and DPL addresses. Th e DPS bit in AUX R1
register (see Figure 5) is used to select whether DPTR is the data pointer 0 or the dat a
pointer 1 (see Figure 7).

Figure 7. Dual Data Pointer Implementation

DPL0
DPL1

DPTR0

DPTR1

DPH0
DPH1

0
1

DPS

0
1

DPL

AUXR1.0

DPH

DPTR

7.3.1 Application Software can take advantage of the additional data pointers to both increase speed and
reduce code size, f or example, block operations ( c opy, compare…) are well served by
using one data pointer as a “source” pointer and the other one a s a “destination” pointer.
Hereafter is an example of block m ove implementation u sing the two pointers and coded
in assembler. The l at est C compi ler t ak es also advantage of this feature by providin g
enhanced algorithm libraries.
The INC instruction is a short (2 bytes) and fast (6 machin e cycle) way to manipulate the
DPS bit in the AUX R1 register. However, note that the INC instruction does not directly
force the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move exam ple, only the fact that DPS is toggled in the proper sequence mat­ters, not its actual value. In other words, the block move routine works the same whether
DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is
added

Rev. B – 19-Dec-01

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers
movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE
incDPTR; increment SOURCE address
incAUXR1; switch data pointers
movx@DPTR,A; write the byte to DEST
incDPTR; increment DEST address
jnzmv_loop; check for NULL terminator

end_move:

23

7.4 Registers Table 3. PSW Register

PSW (S:8Eh)
Program Status Word Register.

76543210

CY AC F0 RS1 RS0 OV F1 P

AUXR (S:8Eh)
Auxiliary Register

Bit

Number

7CY

6AC

5F0User Definable Flag 0.

4-3 RS1:0

2OV

1F1User Definable Flag 1.

0P

Bit

Mnemonic Description

Carry Flag

Carry out from bit 1 of ALU operands.

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

Register Bank Select Bits

Refer to Table 1 for bitsdescription.

Overflow Flag

Overflow set by arithmetic operations.

Parity Bit

Set when ACC contains anoddnumber of 1’s.
Cleared when ACC contains an even number of 1’s.

Reset Value= 0000 0000b

Table 4. AUXR Register

24

T89C51AC2

76543210

- - M0 - XRS1 XRS0 EXTRAM A0

Bit

Number

7-6 -

5M0

4-

Bit

Mnemonic Description

Reserved

The valueread from these bits are indeterminate.Do not setthis bit.

Stretch MOVX control:

the RD/ and the WR/ pulse length isincreasedaccording to the value of M0.

M0 Pulse length in clock period

06
130

Reserved

The value readfrom this bit is indeterminate.Donot set this bit.

Rev. B – 19-Dec-01

T89C51AC2

AUXR1 (S:A2h)
Auxiliary Control Register 1.

Bit

Number

3-2 XRS1-0

1 EXTRAM

0A0

Bit

Mnemonic Description

ERAM size:

Accessiblesize of the ERAM

XRS1:0 ERAM size

0 0 256 bytes
0 1 512 bytes
1 0 768 bytes
1 1 1024 bytes (default)

Internal/External RAM (00h - FFh)

access usingMOVX@ Ri / @ DPTR
0 - Internal ERAM access using MOVX @ Ri / @ DPTR.
1 - External data memory access.

Disable/Enable ALE)

0 - ALE is emitted at a constant rateof 1/6 the oscillatorfrequency(or 1/3 if X2
mode is used)
1-ALEisactiveonlyduringaMOVXorMOVCinstruction.

Reset Value= X00X 1100b
Not bit addressable

Table 5. AUXR1 Register

76543210

- - ENBOOT - GF3 0 - DPS

Bit

Number

7-6 -

5 ENBOOT

4-

3GF3General Purpose Flag 3.

20

1-Reserved for Data Pointer Extension.

0DPS

Bit

Mnemonic Description

Reserved

The value readfrom these bits is indeterminate. Do not set these bits.

Enable Boot Flash

Set this bit for map the boot flash between F800h -FFFFh
Clearthis bit for disable bootflash.

Reserved

The value readfrom this bit is indeterminate.Donot set this bit.

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.

Data Pointer Select Bit

Set to select second dual data pointer: DPTR1.
Clear to select firstdualdata pointer:DPTR0.

Reset Value= XXXX 00X0b

Rev. B – 19-Dec-01

25

8. EEPROM Data

Memory

The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of
the XR AM /ERAM memory space and is selected by setting control b its in the EECO N
register. A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps: write data in the column
latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 up to 128 bytes (the page
size). When programming, only the data written in the colum n latch is programmed and
a ninth bit is used to obtain this feature. This provides the capability t o program t he
whole memory by by tes, by page or by a number of b ytes in a page. Indeed, each ninth
bit is set when the writing the corresponding byte in a row and all these ninth bits are
reset after the writing of the complete EEPROM row.

8.1 Write Data in the

column latches

Data is written b y byte to the column latches as for an external RAM memory. Out of the
11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7
are u sed for byte selection. Between two EEPROM programming sessions, a ll the
addresses in the column latches must stay on t he same page, meaning that the 4 MSB
must no be change d.

The following procedure is used to write to the column latches:

• Save and disable interrupt.

• Set bit EEE of EECO N regi ster

• Load DPTR with the address to write

• Store A regi ster with the data to be written

• Execute a MOVX @DPTR, A

• If needed loop the three last ins tructions until the end of a 128 bytes page

• Restore interrupt.

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

8.2 Programming The EEPROM programming consists on the following actions:

• writing one or more bytes of one page in the column latches. Normally, all by tes

must belong to the same page; if not, the first page address will be latched and the
others discarded.

• launching programming by writing the control seque nc e (50h followed by A0h) to the

EECON register.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

• The end of programming is indi ca ted by a hardware clear of the EEBUSY flag.

Note: The sequence 5xh and Axh m ust be executed without instructions between then other-

wise the programming is aborted.

8.3 Read Data The following procedure is used to read the data stored in the EEPROM memory:

• Save and disable interrupt

• Set bit EEE of EECO N regi ster

• Load DPTR with the address to read

• Execute a MOVX A, @DPTR

• Restore interrupt

26

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

8.4 Examples ;*F*************************************************************************

;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

MOV EECON, #02h; map EEPROM in XRAM space

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

MOV EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

MOV EECON, #050h

MOV EECON, #0A0h

ret

Rev. B – 19-Dec-01

27

8.5 Registers Table 6. EECON Register

EECON (S:0D2h)
EEPROM Control Register

76543210

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Bit

Bit Number

Mnemonic Description

7-4 EEPL3-0

3-

2-

1 EEE

0 EEBUSY

Programming Launch command bits

Write 5Xh followed by AXh to EEPL to launch the programming.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Enable EEPROM Space bit

SettomaptheEEPROMspaceduringMOVXinstructions(Writeinthecolumn
latches)
Clear to map the XRAM space during MOVX.

Programming Busy flag

Set by hardware when programming is in progress.
Cleared by hardwarewhenprogramming is done.
Can not be set or clearedbysoftware.

ResetValue=XXXX XX00b
Not bit addressable

28

T89C51AC2

Rev. B – 19-Dec-01

T89C51AC2

9. Program/Code

Memory

The T89C51AC2 implement 32 Kbytes of on-chip program/code memory. Figure 8
shows the partitioning of internal and external program/code memory spaces depending
on the product.

The FLASH memory increases EPROM and ROM functionality by in-circuit electrical
erasure and programming. Thanks to th e internal charge pump, t he high voltage needed
for p rogramming or erasi ng FLAS H cells is g enerated on-chip using the standard VDD
voltage. Th us, the FLA SH Memory can be program med using only on e voltage and
allows In-System Programming commonly known as ISP. Hardware programming mode
is also available using specific p ro gramm ing tool.

Figure 8. Program/Code Memory Organization

FFFFh

32 Kbytes

external
memory

8000h

7FFFh

32 Kbytes

internal

FLASH

7FFFh

32 Kbytes

external
memory

EA = 1

0000h

Note: If the program executes exclusively from on-chip code memory (not from external mem-

ory), beware of executing code from the upper byte of on-chip memory (7FFFh) and
thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code constant from
this location does not affect Ports 0 and 2.

0000h

EA = 0

9.1 External Code

Memory Access

9.1.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (PSEN#, and ALE ).
Figure 9 shows the structure of the external address bus. P0 carries address A7:0 while

P2 carries address A1 5:8. Data D 7:0 is multiple xe d with A7:0 on P0. Table 7 describes
the external memory interface signals.

Rev. B – 19-Dec-01

29

Figure 9. External Code Memory Interface Structure

T89C51AC2

ALE

P2

P0

AD7:0

A15:8

Latch

A7:0

FLASH

EPROM

A15:8

A7:0

D7:0
OEPSEN#

Table 7. External Code Memory Interface Si gnals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

PSEN# O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines
AD7:0.

Program Store Enable Output

This signal is activelow during external code fetchorexternal code read
(MOVC instruction).

Alternate

Function

P2.7:0

P0.7:0

-

-

9.1.2 External Bus Cycles T his section describes the bus cycles the T89C51AC2 executes to fetch code (s ee
Figure 10) in the external program/cod e memory.
External m emory cycle takes 6 CPU c lock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor­mation on X2 mode see s ec tion “Clock “.
For simplicity, the accom panying figure de picts the bus cycle waveforms in idealized
form and do not provide precise timing in formation.

For bus cycling parameters refer to the section "AC-DC parameters".

30

T89C51AC2

Rev. B – 19-Dec-01