Rainbow Electronics T5761 User Manual

Features

• Frequency Receiving Range of

= 868 MHz to 870 MHz or f0=902MHz to 928MHz

•

30 dB Image Rejection

• Receiving Bandwidth B

• Fully Integrated LC-VCO and PLL Loop Filter

• Very High Sensitivity with Power Matched LNA

• High System IIP3 (-16 dBm), System 1-dB Compression Point (-25 dBm)

• High Large-signal Capability at GSM Band

(Blocking -30 dBm at +20 MHz, IIP3 = -12 dBm at +20 MHz)

• 5 V to 20 V Automotive Compatible Data Interface

• Data Clock Available for Manchester- and Bi-phase-coded Signals

• Programmable Digital Noise Suppression

• Low Power Consumption Due to Configurable Polling

• Temperature Range -40°C to +105°C

• ESD Protection 2 kV HBM, All Pins

• Communication to Microcontroller Possible Via a Single Bi-directional Data Line

• Low-cost Solution Due to High Integration Level with Minimum External Circuitry

Requirements

= 600 kHz for Low Cost 90-ppm Crystals

UHF ASK/FSK Receiver

T5760/T5761

Description

The T5760/T5761 is a multi-chi p PLL recei ver device supplied in an SO20 pa ckage. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel’s PLL RF transmitter T5750. Its main applications are in the areas of telemetering, securi ty technology and keylessentry systems. It can be used in the frequency receiving range of f 870 MHz or f

= 902 MHz to 928 MHz for ASK or FSK data transmission. All the state-

ments made below refer to 868.3 MHz and 915.0 MHz applications. Figure 1. System Block Diagram

UHF ASK/FSK

Remote control transmitter

T5750

XTO

PLL

VCO

Power

amp.

Antenna

T5760/

T5761

Antenna

LNA VCO

UHF ASK/FSK

Remote control receiver

Demod.

IF Amp

PLL XTO

= 868 MHz to

Control

1...5

µC

Preliminary

Rev. 4561B–RKE–10/02

Figure 2. Block Diagram

CDEM

SENS

AVCC AGND DGND

DVCC

FSK/ASK-

demodulator

and data filter

Rssi Limiter out

RSSI IF

Amp.

4. Order

f0 = 950 kHz/

1 MHz

LPF

fg = 2.2 MHz

IF Amp.

Poly-LPF

fg = 7 MHz

Dem_out

Sensitivity-

reduction

Polling circuit

control logic

FE CLK

Standby logic

Loop-

filter

LC-VCO

interface

and

Data -

XTO

DATA

POLLING/_ON

DATA_CLK

IC_ACTIVE

XTAL

LNAREF

LNA_IN

LNAGND

LNA

:256

T5760/T5761

4561B–RKE–10/02

Pin Configuration

Figure 3. Pinning SO20

T5760/T5761

SENS

IC_ACTIVE

CDEM

AVCC

TEST 1

DATA

POLLING/_ON

DGND

DATA_CLK

TEST 4

T5760/

AGND

n.c.

LNAREF

LNA_IN

LNAGND

T5761

DVCC

XTAL

n.c.

TEST 3

TEST 2

Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor 2 IC_ACTIVE IC condition indicator: Low = sleep mode, High = active mode 3 CDEM Lower cut-off frequency data filter 4 AVCC Analog power supply 5 TEST 1 Test pin, during operation at GND 6 AGND Analog ground 7 n.c. Not connected, conne ct to GND 8 LNAREF High-frequency reference node LNA and mixer

9 LNA_IN RF input 10 LNAGND DC ground LNA and mixer 11 TEST 2 Do not connect during operating 12 TEST 3 Test pin, during operation at GND 13 n.c. Not connected, conne ct to GND 14 XTAL Crystal oscillator XTAL connection 15 DVCC Digital power supply 16 TEST 4 Test pin, during operation at DVCC 17 DATA_CLK Bit clock of data stream 18 DGND Digital ground 19 POLLING/_ON Selects polling or receiving mode; Low: receiving mode, High: polling mode 20 DATA Data output/configuration input

4561B–RKE–10/02

RF Front End The RF front end of the receiver is a low-IF heterodyne configuration that converts the

input signal into a 950 kHz/1 MHz IF signal with an image rejection of typical 30 dB. According to Figure 3 the front end consis ts of an LNA (Lo w Nois e Amp lifie r), LO (Lo cal Oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier.

The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated lo w noise LC- VCO (Voltage Co ntrolle d Oscillat or) and PLL-l oop filter . The XTO (crystal oscillator ) generates t he reference fr equenc y f VCO generate s two t imes t he mix er driv e freq uency f are generated with a divide by two circuit (f

= f

VCO

. The I/Q signals for the mixer

VCO

/2). f

is divided by a factor of 256

VCO

and feeds into a phase frequency detector and compared with f phase frequency detector is fed into an i ntegrat ed loop filte r and thereb y gener ates the control voltage for the VCO. If f

is determined, f

can be calculated using the follow-

XTO

ing formula: f

= fLO/128

XTO

The XTO is a on e-pin osci llator that op erates at the series resonance o f the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at Pin XTAL. According to Figure 4, the crystal should be connected to GND with a se ries capacitor C

. The value of that cap acitor is rec om-

mended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of C

The value of C value of f

should be optimized for the ind ivid ual boa rd layou t to a chiev e th e ex act

(the best way is to use a crystal with known load resonance frequency to

XTO

find the right value for this capacitor) and hereby of f

is normally necessary.

. When designing the system in

terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered.

. The integrated LC-

XTO

. The output of the

XTO

If a crystal with ±30 ppm adjus tment tolerance at 25 °C, ±50 ppm over temperature

-40°C to +105°C, ±10 ppm of total aging and a CM (motional capacitance) of 7 fF is used, an additional XTO pulling of ±30 ppm has to be added.

The resulting total LO tolerance of ±120 ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of ±120 ppm.

Figure 4. XTO Peripherals

The nominal frequency f frequency f

= fRF - f

using the following formula (low side injection):

DVCC

XTAL

n.c.

TEST 3

TEST 2

is determined by the RF input frequency fRF and the IF

T5760/T5761

4561B–RKE–10/02

T5760/T5761

To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is f frequencies, the filter is tuned by the crystal frequency f fixed relation between f

= fLO/915

The relation is designed to achieve the nominal IF frequency of f

868.3 MHz version. For the 915 MHz version an IF freque nc y of f The RF input either from an antenna or from an RF generator must be transformed to

the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrica l parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well as to 50 W or an antenna easier.

= 950 kHz. To achieve a good accurac y of the filter corner

and fLO.

. This means that there is a

XTO

= 950 kHz for the

= 1.0 MHz results.

Figure 33 shows a typical input matching network for f

= 868.3 MHz to 50 W. Figure 34

illustrates an according input matching for 868.3 MHz to an SAW. The input matchi ng network shown in Figure 33 is the reference network for the parameters given in the electrical character isti cs .

Analog Signal Processing

IF Filter The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF

filter. The IF center frequency is f and f

=1.0 MHz for fRF = 915 MHz. The nominal bandwidth is 600 kHz.

Limiting RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is

fed into the demodulator. The dynamic range of this amplifier is DR RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic ran ge of the RSSI am plifier is exceede d if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity.

In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier, because only the hard limited signal fr om a h igh gain limit ing ampl ifier is used by the demodulator.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage V

. V

Th_red

nected between Pin S ENS a nd G ND or V digital control logic. By this means it is possible to operate the receiver at a lower sensitivity.

is determined by the value of th e external res istor R

Th_red

= 950 kHz for applications where fRF = 868.3 MHz

= 60 dB. If the

RSSI

. R

. The output of the c om par at or is f ed into the

Sens

is con-

4561B–RKE–10/02

If R

is connected to GND, the receiver switches to full sensitivity. It is also possible to

Sens

connect the Pin SENS directly to GND to get the maximum sensitivity. If R

sensitivity is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced

Sens

, the maximum sensitivity by the signal-to-

Sens

noise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier.

Since different RF in put netw orks may ex hibit sli ghtly di fferent val ues for the LN A gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matchi ng is illustr ated in Figur e 33 and exhibi ts the best poss ible sens itivity and at the same time power matching at RF_IN.

can be connected to VS or GND via a mic rocontrolle r. The receiver can be

Sens

switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the R F input signal doe s not exceed the se lected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 5 is issued at Pin DATA to indicate that the receiver is still active (see Figure 32).

Figure 5. Steady L State Limited DATA Output Pattern

FSK/ASK Demodulator and Data Filter

DATA

DATA_min

DATA_L_max

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode.

In ASK mode an automatic thr eshold co ntrol circuit (A TC) is e mployed to set the dete ction reference voltage to a v alue w here a good s ignal to nois e ratio is achi eved. Th is circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data si gnal can be de tected p roperly, b ut better valu es are fo und f or many modulation schemes of the competing transmitter.

The FSK demodulator is intended to be used for an FSK dev iation of 10 kHz £ Df £ 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signal s) ex ceeds abou t 2 dB . This val ue is v alid for all mod ulati on sc hemes of a disturber signal.

The output signal of the demo dulator is filtered by the data filter befo re it is fed in to the digital signal processing circuit. The data filter improves the S/N r atio as its passband can be adopted to the cha racter istics of the da ta signal . The data filter c onsists of a 1 order high pass and a 2

nd-

order lowpass filter.

st-

The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula:

fcu_DF

-----------------------------------------------------------=

2 p´ 30 kW´ CDEM´

In self-polling mode , the data fil ter mu st settle very rapidly to ac hie ve a lo w cu r re nt consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand CDE M must b e large eno ugh to me et the dat a filter requirements according to the d ata signal. Reco mmended val ues for CDEM ar e given in th e electrical character isti cs .

The cut-off frequenc y of the lowpass fi lter is define d by the selecte d baud-rate ra nge (BR_Range). The BR_Range is defined in the OPMODE register (refer to chapter ‘Configuration o f the Receiv er’). The B R_Ra nge mu st be set in ac cordan ce to the u sed baud-rate.

T5760/T5761

4561B–RKE–10/02

T5760/T5761

The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V and V

= 66%. The sensitivity may be reduced by up to 2 dB in that condition.

DC_max

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t

). These limits are defined in the electrical characteristics. They should not be

ee_sig

exceeded to maintain full sensitivity of the receiver.

DC_min

=33%

Receiving Characteristics

The RF receiver T5760/T5761 c an be ope rated with a nd withou t a SAW fro nt-end fil ter. In a typical aut omo tiv e appl ication, a SAW fi lte r is u sed to ac hi ev e b ette r selectivity and large signal capab ility. T he rec eivi ng frequen cy r espo nse withou t a SAW fron t-end fil ter is illustrated in Figure 6 and Figu re 7. This exa mple relates to ASK m ode. FSK mode exhibits a simila r beha vi or. T he pl ots are p ri nte d r ela tively to the maximu m sensitivity. If a SAW filter is used, an i ns ertio n loss of about 3 dB must b e c onsidered, but the overall selectivity is much better.

When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it al so determine s the IF center fre quency. The tot al LO deviatio n is calculated, to be the sum of the deviat ion of the cry stal and the XT O deviatio n of the T5760/T5761. Low-cost crystals are specified to be within ±90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm worst case for a crystal with CM = 7 fF. I f a cr y stal of ±90 ppm is used, the total deviation is ± 12 0 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.

Figure 6. Narrow Band Receiving Frequency Response

0.0

-10.0

-20.0

4561B–RKE–10/02

-30.0

dP (dB)

-40.0

-50.0

-60.0

-4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0

df (MHz)

Figure 7. Wide Band Receiving Frequency Response

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

dP (dB)

-70.0

-80.0

-90.0

-100.0

-12.0 -9.0 -6.0 -3.0 0.0 3.0 6.0 9.0 12.0

df (MHz)

Polling Circuit and Control Logic

Basic Clock Cycle of the Digital Circuitry

The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path per iodicall y for a short time. Dur ing this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains ac tive and trans fers the d ata to the connec ted mi crocon troller . If there is no valid signal pr es en t, th e r ecei ve r is in sl ee p mo de most of the time r esul ting in low current consumpt ion . T hi s c ond iti on is c al led p oll in g m ode . A c on nec ted mi cro con tr oll er is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc.

Regarding the number of con nection wires to the microcontroll er, the receiver is ve ry flexible. It can be eith er operated by a sin gle bi-direction al line to save port s to the connected microcontroller or it can be operated by up to five uni-directional ports.

The complete timing of the digital circuitry and the analog filtering is derived from one clock. This cloc k cycle T

is derived from the crystal osc illator (XTO) in com bination

Clk

with a divide by 14 circuit. According to chapter ‘RF Front End’, the frequency of the crystal oscillator (f operating frequency of the local oscillator (f giving T

Clk

= 2.066 µs for fRF= 868.3 MHz and T

Clk

controls the following application-relevant parameters:

) is defined by the RF in put signa l (f

XTO

). The basic clock cycle i s T

= 1.961 µs for f

Clk

) which also defines th e

RFin

= 915 MHz.

Clk

= 14/f

XTO

• Timing of the polling circuit including bit check

• Timing of the analog and digital signal processing

• Timing of the register programming

• Frequency of the reset marker

• IF filter center frequency (f Most application s a re dom in ated by two transmissio n fr eq uen ci es : f

mainly used in USA , f T

-dependent param eters on this ele ctrica l charac teristi cs displ ay thr ee conditi ons for

Clk

Transmit

)

IF0

= 915 MHz is

Transmit

= 868.3 MHz in Europe. In order to e ase the usage of all

each parameter.

T5760/T5761

4561B–RKE–10/02

T5760/T5761

• Application USA (f

• Application Europe (f

• Other applications The electrical characteristic is given as a function of T

= 7.14063 MHz, T

XTO

= 6.77617 MHz, T

XTO

= 1.961 µs)

Clk

= 2.066 µs)

Clk

The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is define d in the OPMODE reg ister. T his cloc k cycl e T

is defined

XClk

by the following formulas for further reference: BR_Range = BR_Range0: T

BR_Range1: T BR_Range2: T BR_Range3: T

XClk XClk XClk XClk

= 8 ´ T = 4 ´ T = 2 ´ T = 1 ´ T

Clk Clk Clk Clk

Polling Mode According to Figure 11, the receiver stays in polling mode in a continuous cycle of three

different modes. In sleep mode the signal processi ng circuitry is disabled for the time period T all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T This period varies check by check as it is a statistical process. An average value for T

Bit-check

consumption is I The average curre nt co nsu mpt ion i n p o llin g mode is depende nt o n t he duty c y cle o f th e active mode and can be calculated as:

while consuming low current of IS=I

Sleep

. During the start-up perio d, T

Soff

is given in the electrical characteristics. During T

. The condition of the receiver is indicated on Pin IC_ACTIVE.

Son

Startup

and T

Bit-check

Startup

Bit-check

the current

Spoll

During T

SoffTSleepISon

--------------------------------------------------------------------------------------------------------------=

Sleep

SleepTStartupTBit-check

and T

Startup

tee the reception o f a tran sm itte d command the trans mi tte r must start the telegram wi th an adequate preburst. The required length of the preburst depends on the polling parameters T (T

Start_microcontroller

Bit-check

) to be tested.

, T

Sleep

). Thus, T

Startup

The following formula indicates how to calculate the preburst length. T

Preburst

³ T

Sleep

+ T

Startup

Sleep Mode The length of period T

the extension factor XSleep (according to Table 8), and the basic clock cycle T calculated to be:

= Sleep ´ X

Sleep

In US- and European applications, the maximum value of T is set to 1. The time reso lution is about 2 ms in tha t case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleep

Std

to’1’.

According to Tabl e 7, the hi gh es t reg is ter va lue o f s le ep sets th e re ce iv er i nto a p er manent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the O PMODE register. This function is desirable wher e several devices share a single data line and may also be used for microcontroller polling – via Pin POLLING/_ON, the receiver can be switched on and off.

Sleep

+()´+´

StartupTBit-check

the receiver i s no t sensi tive to a tra nsm itter s ignal . To gu aran-

, T

Bit-check

+ T

is defined by the 5-bit word Sleep of the OPMODE register,

Sleep

´ 1024 ´ T

and the start-up time of a connected mi crocontr oller

Bit-check

depends on the actual bit rate and the number of bits

+ T

Bit-check

Start_microcontroller

Clk

is about 60 ms if XSleep

Sleep

Clk

. It is

4561B–RKE–10/02

Figure 8. Polling Mode Flow Chart

Sleep mode:

All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low I

= I

Soff

= Sleep x X

Sleep

Start-up mode:

The signal processing circuits are enabled. After the start-up time (T all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => high

= I

Son

Startup

Bit-check mode:

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE => high I

= I

Son

Bit-check

Receiving mode:

The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or

POLLING/_ON.

Output level on Pin IC_ACTIVE => high I

= I

Son

Sleep

Bit check

OK ?

OFF command

x 1024 x T

YES

Clk

Startup

Sleep: 5-bit word defined by Sleep0 to

Sleep4 in OPMODE register

: Extension factor defined by

Sleep

XSleepStd

according to Table 9

: Basic clock cycle defined by fXTO

Clk

)

Startup

and Pin MODE

: Is defined by the selected baud rate

range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register.

: Depends on the result of the bit check

Bit-check

If the bit check is ok, T depends on the number of bits to be checked (N utilized data rate.

Bit-check

) and on the

Bit-check

If the bit check fails, the average time period for that check depends on the selected baud-rate range and

on T

. The baud-rate range is

Clk

defined by Baud0 and Baud1 in the OPMODE register.

Figure 9. Timing Diagram for Complete Successful Bit Check

( Number of checked Bits: 3 )

IC_ACTIVE

Bit check

Dem_out

Data_out (DATA)

Start-up

Start-up mode

T5760/T5761

1/2 Bit

Bit-check mode

Bit check ok

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Bit-check

Receiving mode

4561B–RKE–10/02

T5760/T5761

Bit-check Mode In bit-check mode the incoming data str eam is examine d to distingu ish between a va lid

signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where th e dis tances b etwe en 2 sig nal ed ges are continu ously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable.

Configuring the Bit Check

Assuming a modulation scheme tha t contains 2 edges per bi t, two time fra me checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N checks respectively. If N

in the OPMODE register. T his impli es 0, 6, 12 and 18 edge- to-edge

Bit-check

is set to a higher value, the receiv er is less likely to switch to receiv ing mode due to noise. In the presenc e of a valid tr ansmit ter signal, the bit check takes l e ss ti me if N time is not dependent on N

Bit-check

is set to a lower value. In polling mode, the bit-check

Bit-check

. Figure 9 sho ws an exa mple w here 3 bits a re test ed

successfully and the data signal is transferred to Pin DATA. According to Figure 10, the time window for the bit check is defined by two separate

time limits. If the edge-to-edge time t the upper bit-check limit T T

Lim_min

or tee exceeds T

Lim_max

is in between the lower bit-check limit T

Lim_min

and

, the check will be continued. If tee is smaller than

, the bit check will be terminated and the receiver

switches to sleep mode. Figure 10. Valid Time Window for Bit Check

1/f

Sig

Dem_out

Lim_min

Lim_max

For best noise immunity it is recomme nded to use a low span between T T

. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

Lim_max

Lim_min

and

preburst. A ‘11111...’ or a ‘10101...’ s equence in Manc hester or Bi-ph ase is a goo d choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ± 30% regarding the expected edge-to-edge time t

. Using pre-burst patterns that contain various edge-to-edge time periods, the bit-

check limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. T

= Lim_min ´ T

Lim_min

= (Lim_max -1) ´ T

Lim_max

XClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the

required T T

. The minimum edge-to-edge time tee (t

XClk

Lim_min

, T

Lim_max

and T

. The time resolution de fining T

XClk

DATA_L_min

, t

DATA_H_min

Lim_min

and T

Lim_max

) is defined according to the chapter ‘Receiving Mode’. The lower limit should be set to Lim_min ³10. The maximum value of the upper limit is Lim_max = 63.

If the calculated value for Lim_min is <19, it is recommende d to check 6 or 9 bits (N

) to prevent switching to receiving mode due to noise.

Bit-check

4561B–RKE–10/02

+ 24 hidden pages

Rainbow Electronics T5761 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual