Rainbow Electronics T48C862-R3 User Manual

Features

• Single Package Fully-integrated 4-bit Microcontroller with RF Transmitter

• Low Power Consumption in Sleep Mode (< 1 µA Typically)

• Flash Controller for Application Program Available

• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)

• 2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply

• -40°C to +125°C Operation Temperature

• SSO24 Package

• About Seven External Components

Microcontroller
with UHF

Description

The T48C862-R3 is a single package dual-chip circuit. It combines a UHF ASK/FSK
transmitter with a 4-bit mi crocontr oller. It suppor ts highly i ntegrated sol utions in car
access and tire pressure monitoring applications, as well as manifold applications in
the industrial and consumer segment. It is available for the frequency range of
429 MHz to 439 MHz with data rates up to 32 kbaud.

For further frequenc y ranges s uch a s 3 10 MHz to 3 30 MHz and 868 MHz to 928 MHz
separate data sheets are available.

The device contains a flash microcontroller.

Figure 1. Application Diagram

T48C862

Antenna

UHF ASK/FSK

Receiver

Micro-

controller

Keys

Micro-

controller

PLL-

Transmitter

ASK/FSK
Transmitter

T48C862-R3

Preliminary

Rev. 4554A–4BMCU–02/03

1

Pin Configuration

Figure 2. Pinning SSO24

XTAL

VS

GND

ENABLE

NRESET

BP63/T3I

BP20/NTE

BP23

BP41/T2I/VMI

BP42/T2O

BP43/SD/INT3

VSS

1
2
3
4
5
6
7
8
9
10
11
12

ANT1

24

ANT2

23

PA_ENABLE

22

CLK

21

BP60/T3O

20

OSC2

19

OSC1

18

BP50/INT6

17

BP52/INT1

16

BP53/INT1

15

BP40/SC/INT3

14

VDD

13

Pin Description: RF Part

Pin Symbol Function Configuration

1 XTAL Connection for crystal

1.5k

XTAL

VS

VS

1.2k

182 mA

2 VS Supply voltage ESD protection circuitry (see Figure 8)
3 GND Ground ESD protection circuitry (see Figure 8)
4 ENABLE Enable input

ENABLE

200k

2

T48C862-R3

4554A–4BMCU–02/03

Pin Description: RF Part (Continued)

Pin Symbol Function Configuration

21 CLK Clock output signal for microcontroller

The clock output fre quency is set by the
crystal to f

XTAL

/4.

T48C862-R3

VS

100

100

22 PA_ENABLE Switches on power amplifier, used for

ASK modulation

23
24

ANT2
ANT1

Emitter of antenna output stage
Open collector antenna output

PA_ENABLE

50k

20 mA

Pin Description: Microcontroller Part

Name Type Function Alternate Function Pin No.

V

DD

V

SS

BP20 I/O Bi-directional I/O line of Port 2.0 NTE-test mode enable, see also section "Master Reset" 7
BP40 I/O Bi-directional I/O line of Port 4.0 SC-serial clock or INT3 external interrupt input 14

BP41 I/O Bi-directional I/O line of Port 4.1

BP42 I/O Bi-directional I/O line of Port 4.2 T2O Timer 2 output 10
BP43 I/O Bi-directional I/O line of Port 4.3 S D ser ial data I/O or INT3-external interrupt input 11
BP50 I/O Bi-directional I/O line of Port 5.0 I NT 6 external interrupt input 17
BP52 I/O Bi-directional I/O line of Port 5.2 I NT 1 external interrupt input 16
BP53 I/O Bi-directional I/O line of Port 5.3 I NT 1 external interrupt input 15
BP60 I/O Bi-directional I/O line of Port 6.0 T3O Timer 3 output 20
BP63 I/O Bi-directional I/O line of Port 6.3 T3I Timer 3 input 6

OSC1 I Oscillator input

OSC2 O Oscillator output

NRESET I/O Bi-directional reset pin – 5

– Supply voltage – 13
– Circuit ground – 12

VMI voltage monitor input or T2I external clock input
Timer 2

4-MHz crystal input or 32-kHz crystal input or external
clock input or external trimming resistor input

4-MHz crystal output or 32-kHz crystal output or external
clock input

CLK

ANT1

ANT2

9

18

19

Uref=1.1V

Reset State

NA

NA
Input
Input

Input
Input

Input
Input
Input
Input
Input
Input

Input

Input

I/O

4554A–4BMCU–02/03

3

UHF ASK/FSK Transmitter Block

Features

• Integrated PLL Loop Filter

• ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/AN T2

• High Output Power (8 dBm) with Low Supply Current (9.0 mA)

• Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-

drain Output of the Modulating Microcontroller

• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

• Single Li-cell for Power Supply

• Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -4 0°C to +85°C/+125°C

• Single-ended Antenna Output with High Efficient Power Amplifier

• CLK Output for Clocking the Microcontroller

• One-chip Solution with Minimum External Circuitry

• 125°C Operation for Tire Pressure Systems

Description

The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to
32 kbaud. The transmitting frequency range is 310 MHz to 330 MHz. It can be used in both FSK and ASK systems.

4

T48C862-R3

4554A–4BMCU–02/03

Figure 3. Block Diagram

T48C862-R3

T48C862

CLK

PA_ENABLE

ANT2

ANT1

OSC2
OSC1

V

DD

V

SS

NRESET

BP20/NTE

BP23

BP10
BP13

BP21

BP22

Brown-out protect.

RESET

Voltage moni tor

External input

VMI

Port 1

n
o

i

t

c

2

e

t

r

r

i

o

d

P

a

t
a
D

f

4

PA

RC

oscillators

EEPROM

4 K x 8 bit

4-bit CPU core

Power up /

down

f

32

PFD

CP

LF

VCO

PLL

Crystal

oscillators

Clock management

clock input

RAM

256 x 4 bit

I/O bus

External

XTO

UTCM
Timer 1

interval- and

watchdog timer

Timer 2

8/12-bit timer

with modulator

SSI

Serial int erface

Timer 3

8-bit
timer / counter
with modulator

and demodulat or

ENABLE

VS

GND

XTAL

µC

T2I

T2O

SD
SC

T3O

T3I

4554A–4BMCU–02/03

Data direction +

alternate fu nction

Port 4

BP40

BP41

INT3

VMI

SC

T2I

BP42
T2O

BP43
INT3
SD

Data direction +
interrupt control

Port 5

BP51
INT6

BP52

BP50

INT1

INT6

BP53

INT1

Data direction +
alternate function

Port 6

BP60
T3O

BP63

T3I

EEPROM

2 x 32 x 16 bit

5

General Desc ription This fully-integrated PLL transmitter that allows particularly simple, low-cost RF minia-

ture transmitters to be assembled. The VCO is locked to 32 f
crystal is needed for a 315 MHz transmitter. All other PLL and VCO peripheral elements
are integrated.

The XTO is a series res onance oscillator so that only one capac itor together with a
crystal connected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs maximum <1 ms until the PLL is
locked and the CLK ou tput is sta ble. A wait time of ³ 1 ms until the CLK is used for the
microcontroller and the PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly
independent from t he load imped ance. The del ivered ou tput power is controlle d via the
connected load impedance.

This output configuration enables a simple matching to any kind of antenna or to 50 W. A
high power efficiency of h =P
an optimized load impedance of Z

out

/(I

S,PAVS

Load

) of 40% for the power amplifier results when

= (255 + j192) W is used at 3 V supply voltage.

, thus, a 9.8438 MHz

XTAL

Functional Description

If ENABLE = L and PA_ENABLE = L, the circuit is in standby mode consuming only a
very small amount o f current s o that a li thium cell u sed as po wer supply can work for
several years.

With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE
remains L, only the PLL and the XT O are r unn ing and the CLK si gn al is del iver ed to the
microcontroller. The VCO locks to 32 times the XTO frequency.

With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power
amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off,
which is used to perform the ASK modulation.

ASK Transmission The PLL transmit ter bl oc k is a ct iv ated by ENA BL E = H. PA_ENABLE m us t r em ain L for

t ³ 1 ms, then the CLK signal c an be taken to clock the microcontroller and the output
power can be modulated by means of pin PA_ENABLE. After transmission,
PA_ENABLE is switched to L and the microcontroller switches back to internal clocking.
The PLL transmitter block is switched back to standby mode with ENABLE = L.

FSK Transmission The PL L t ra ns mit ter bl ock is a ct iv ated by ENABL E = H. PA_ENAB LE m us t r em ain L for

t ³ 1 ms, then the CLK signal can be take n to clock the microco ntroller and the power
amplifier is sw itch ed on with PA_ENA BLE = H. The chip is then re ady f or F SK mo dula­tion. The microcontroller starts to switch on and off the capacitor between the XTAL load
capacitor and GND with an open-drain output port, thus changing the reference
frequency of the PLL. If the switch is clo sed, the output frequenc y is lower than if the
switch is open. After tran smis sion PA_ENABL E is swi tched to L and the micro contr oller
switches back to internal clockin g. The PLL transm itter block is switc hed back to
standby mode with ENABLE = L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when
the following tolerances are considered.

6

T48C862-R3

4554A–4BMCU–02/03

Figure 4. Tolerances of Frequency Modulation

~

V

S

C

XTAL

~

Stray1

CMLMR

Crystal equivalent circuit

C

0

T48C862-R3

C

Stray2

S

C

4

C

5

C

Switch

Using C
capacitances on each side of the crystal of C
capacitance of the crystal of C

=8.2pF ±5%, C5= 10 pF ±5%, a switch port with C

4

= 3.2 pF ±10% and a crystal with CM= 13 fF ±10%, an

0

Stray1=CStray2

=3pF ±10%, stray

Switch

= 1 pF ±1 0%, a paralle l

FSK deviation of ±21.5 kHz typical with wo rst case tolerances of ±16.25 kHz to
±28.01 kHz results .

CLK Output An output CLK signal is provided for a connected microcontroller, the delivered signal is

CMOS compatible if the load capacitance is lower than 10 pF.

Clock Pulse Take Over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s

M4xCx9x has the special feature of starting with an integrated RC-oscillator to switch on
the PLL transmitter block with ENABLE = H, and after 1 ms to assume the clock signal
of the transmission IC, so the message can be sent with crystal accuracy.

Output Matching and Power Setting

The output power is set by the l oad impe dance o f the ante nna. Th e maximum output
power is achieved with a load impe dance of Z
low resistive path to V

to deliver the DC current.

S

= (255 + j192) W. There must be a

Load,opt

The delivered current pulse of the power amplifier is 9 mA and the maximum output
power is deliver ed to a resistive load of 400 W if the 1.0 pF output capacitanc e of th e
power amplifier is compensated by the load impedance.

An optimum load impedance of:
Z

=400W || j/(2 ´p1.0 pF) = (255 + j192) W thus results for the maximum output

Load

power of 8 dBm.

4554A–4BMCU–02/03

The load impedance is def ine d as th e im ped anc e s ee n from the PL L tr ans m itte r blo ck’s
ANT1, ANT2 into the ma tching network . Do not confus e this la rge si gnal load imped­ance with a small signal input impedance delivered as input characteristic of RF
amplifiers and me asured fr om the appl icatio n into the IC i nstead of from the IC into th e
application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 400 W where the
parallel imaginary part should be kept constant.

Output power measurement can be done with the cir cuit shown in Figure 5. Note that
the component values must be changed to compensate the individual board parasitics
until the PLL transmitter block has the right load impedance Z

= (255 + j192) W.

Load,opt

Also the damping of the cable used to measure the output power must be calibrated.

7

Figure 5. Output Power Measurement

V

S

C1 = 1n

= 33n

L

~

ANT1

Z

ANT2

~

1

C2 = 2.2p

Lopt

Z = 50 W

Power
meter

R

in

50 W

Application Circuit For the supply-voltage blocking capacitor C

(see Figure 6 and Figure 7). C
amplifier where C
series); for C

typically is 22 pF/NP0 and C2 is 10.8 pF/NP0 (18 pF + 27 pF in

1

two capacitors in series should be used to achieve a better tolerance

2

value and to hav e the possibil ity to realize the Z
capacitors.

C

forms together with the pins of PLL transmitter block and the PCB board wires a

1

series resonance lo op that supp resses the 1
PCB is important. Normally the best suppression is achieved when C
as possible to the pins ANT1 and ANT2.

The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the
loop antenna is too high.

L

(50 nH to 100 nH) can be printed on PCB. C4 should be selected so the XTO runs on

1

the load resonance frequency of the cr ystal. Normally, a value of 12 pF results for a
15 pF load-capacitance crystal.

and C2 are used to match the loop antenna to the power

1

, a value of 68 nF/X7R is recommended

3

Load,opt

st

harmonic, thus, the position of C1 on the

by using standard valued

is placed as close

1

8

T48C862-R3

4554A–4BMCU–02/03

Figure 6. ASK Application Circuit

T48C862-R3

VS

C4

XTAL

VS

XTAL

VS

C3

GND

ENABLE

L1

241

ANT1

23

ANT2

22

PA_ENABLE

21

CLK

C1

Loop

Antenna

C2

PLL

VCO

LF

CP

PFD

32

PA

f

4

f

XTO

2

3

4

Power up/down

4554A–4BMCU–02/03

NRESET

BP63/T3I

BP20/NTE

BP23

BP41/T2I/VMI

BP42/T2O

BP43/SD/
INT3

VSS

10

11

12

5

6

7

8

9

BP60/T3O

20

OSC2

19

OSC1

18

BP50/INT6

17

BP52/INT1

16

BP53/INT1

15

BP40/SC/INT3

14

VDD

13

S1

S2

S3

VS

9

Figure 7. FSK Application Circuit

VS

C4

C5

XTAL

VS

XTAL

VS

C3

GND

ENABLE

L1

241

ANT1

23

ANT2

22

PA_ENABLE

21

CLK

C1

Loop

Antenna

C2

PLL

VCO

LF

CP

PFD

32

PA

f

4

f

XTO

2

3

4

Power up/down

10

NRESET

5

BP63/T3I

BP20/NTE

BP41/T2I/VMI

BP42/T2O

BP43/SD/
INT3

6

7

BP23

8

9

10

11

VSS

12

T48C862-R3

BP60/T3O

20

OSC2

19

OSC1

18

BP50/INT6

17

BP52/INT1

16

BP53/INT1

15

BP40/SC/INT3

14

VDD

13

S1

S2

S3

VS

4554A–4BMCU–02/03

Figure 8. ESD Protection Circuit

VS

T48C862-R3

ANT1

CLK PA_ENABLE

GND

ANT2

XTAL ENABLE

Absolute Maximum Ratings

Parameters Symbol Min. Max. Unit

Supply voltage V
Power dissipation P
Junction temperature T
Storage temperature T
Ambient temperature T

tot

stg

amb

S

j

-55 +125 °C

-55 +125 °C

5V
100 mW
150 °C

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

thJA

170 K/W

Electrical Characteristics

VS = 2.0 V to 4.0 V, T
Typical values are given at V

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Supply current Power down,

Supply current Power up, PA off, VS= 3 V

Supply current Power up, V

Output power VS= 3.0 V, T

4554A–4BMCU–02/03

= -40°C to +125°C, unless otherwise specified.

amb

= 3.0 V and T

S

V

ENABLE

V

PA-ENABLE

V

PA-ENABLE

= 25°C. All parameters are referred to GND (Pin 7).

amb

< 0.25 V , -40°C to +85°C

< 0.25 V , -85°C to +125°C
< 0.25 V , 25°C

(100% correlation tested)

ENABLE

ENABLE

> 1.7 V, V

S

> 1.7 V, V

amb

V

V

f = 315 MHz, Z

PA-ENAB LE

= 3.0 V

PA-ENAB LE

=25°C

= (255 + j192) W

Load

<0.25V

>1.7V

I

S_Off

I

S

I

S_T r ansmit

P

Ref

350

7

<10

3.7 4.8 mA

911.6mA

6.0 8.0 10.5 dBm

nA
µA
nA

11

Electrical Characteristics (Continued)

VS = 2.0 V to 4.0 V, T
Typical values are given at V

= -40°C to +125°C, unless otherwise specified.

amb

= 3.0 V and T

S

= 25°C. All parameters are referred to GND (Pin 7).

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Output power v ariation for the full
temperature range

Output power v ariation for the full
temperature range

Achievable output-power range Selectable by load impedance P
Spurious emission f

T

= -40°C to +85°C

amb

= 3.0 V

V

S

= 2.0 V

V

S

= -40°C to +125°C

T

amb

V

= 3.0 V

S

= 2.0 V

V

S

= P

P

Out

CLK

Ref

= f0/128

+ DP

Ref

DP
DP

DP
DP

Out_typ

Ref
Ref

Ref
Ref

-1.5

-4.0

-2.0

-4.5

dB
dB

dB
dB

08.0dBm

Load capacitance at Pin CLK = 10 pF
fO ± 1´ f

± 4 ´ f

f

O

CLK

CLK

-55

-52

dBc
dBc

other spurious are lower

Oscillator frequency XTO
(= phase comparator frequency)

f

= f0/32

XTO

= resonant frequency of the

f

XTAL

XTAL, C

£ 10 fF, load capacitance

M

selected accordingly
T

= -40°C to +85°C

amb

= -40°C to +125°C

T

amb

f

XTO

-30

-40

f

XTAL

+30
+40

ppm

ppm
PLL loop bandwidth 250 kHz
Phase noise of phase

comparator

Referred to f
25 kHz distance to carrier

PC

= f

XT0,

-116 -110 dBc/Hz

In loop phase noise PLL 25 kHz distance to carrier -86 -80 dBc/Hz
Phase noise VCO at 1 MHz

at 36 MHz
Frequency range of VCO f
Clock output frequen cy (CMOS

microcontroller compatible)
Voltage swing at Pin CLK C

£ 10 pF V

Load

VCO

0h

V

310 330 MHz

VS´ 0.8

0l

-94

-125

/128 MHz

f

0

V

-90

-121

´ 0.2

S

dBc/Hz
dBc/Hz

V

V
Series resonance R of the c rystal Rs 110 W
Capacitive load at Pin XT0 7pF
FSK modulation frequency rate Duty cycle of the modulation signal =

50%

ASK modulation frequency rate Duty cycle of the modulation signal =

50%

ENABLE input Low level input voltage

High level input voltage
Input current high

PA_ENA BLE input Low level input voltage

High level input voltage
Input current high

V

Il

V

Ih

I

In

V

Il

V

Ih

I

In

032kHz

032kHz

0.25

1.7
20

0.25

1.7

5

V
V

µA

V
V

µA

12

T48C862-R3

4554A–4BMCU–02/03

Microcontroller Block

T48C862-R3

Features

• 4-Kbyte ROM, 256 x 4-bit RAM

• EEPROM Programmable Options

• Read Protection fo r the EEPROM Program Memory

• 16 Bi-directional I/Os

• Up to Seven External/Internal Interrupt Sources

• Eight Hardware and Software Interrupt Priorities

• Multifunction Timer/Counter

- IR Remote Control Carrier Generator

- Biphase-, Manchester- and Pulse-width Modulator and Demodulator

- Phase Control Function

• Programmable System Clock with Prescaler and Five Different Clock Sources

• Very Low Sleep Current (< 1 µA)

• 2 × 512-bBit EEPROM Data Memory

• 256 × 4-bi t RAM Data Memory

• Synchronous Serial Interface (2-wire, 3-wire)

• Watchdog, POR and Brown-out Function

• Voltage Monitoring Inclusive Lo_BAT Detect

Description The microcontroller is designed with EEPROM cel ls so it can be progr ammed several

times. To offer full compatibility with each ROM version, the I/O configuration is stored
into a separate internal EEPROM block during programming. The configuration is down­loaded to the I/Os with every power-on reset.

Introduction The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrol-

lers. Instead of ROM it contains EEPRO M, RAM, parallel I/O ports, two 8-bit
programmable multifunction timer/counters, voltage supervisor, interval timer with
watchdog function an d a soph isticated on-chip c lock gene ration wi th integrat ed RC-,
32-kHz and 4-MHz crystal oscillators.

Differences between T48C862-R3 and ATAR862 Microcontrollers

Program Memory The program memory of the devices is realized as an EEPROM. The memory size for

user programs is 40 96 bytes. It is pro grammed as 258 ´ 16 bytes blocks of data. the
implement LOCK-bit function is user-selectable and protects the device from unautho­rized read-out of the program memory.

Configuration Memory An additional area of 3 2 bytes of the EE PROM is u sed to s tore inform ation abou t the

hardware configuration. All the options that are selectable for the ROM versions are
available to the user. T his i nc lud es not o nly th e di fferen t port op tio ns but a lso th e pos s i­bilities to select different capacitors for OSC1 and OSC2, the option to enable or disable
the hardlock for the watchdog, the option to select OSC2 instead of OSC1 as external
clock input and the option to enable the external clock monitor as a reset source.

Data Memory The microcontroller block contains an internal data EEPROM that is organized as two

pages of 32 ´ 16-bit. To be compatible with the ROM parts, the page used has to be
defined within the application software by writing the 2-wire interface (T WI) command
"09h" to the EEPROM. This command ha s no effect for the microcont roller block , if it is
left inside the HEX-file for the ROM version. Also for compatibility reasons, the access to
the EEPROM is handled via the MCL (serial interface) as in the corresponding ROM
parts.

13

4554A–4BMCU–02/03

Reset Function During each reset (power-on or brown-out), the I/O configuration is deleted and

reloaded with the data from the configuration memory. This leads to a slightly different
behavior compare d to the ROM v ersions . Both devi ces switc h their I/O s to input dur ing
reset but the ROM part has the mask selected pull-up or pull-down resistors active while
the MTP has them removed until the download is finished.

Microcontroller Architecture General Description

The microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is base d on the Harvard architec ture with physically separated
program memory (ROM) an d data memory (RAM ). Three independen t buses, the
instruction bus, the memory bus and the I/O bus, are used for parallel communication
between ROM, RAM and peripherals. This enhances program execution speed by
allowing both inst ructio n pre fetchi ng, and a si multan eous commu nicat ion to the on -chip
peripheral circuitry. The extremely powerful integr ated interrupt controller with associ­ated eight prioritized interrupt levels supports fast and efficient processing of hardware
events. The mic rocontroller i s designed fo r the high-leve l programming language
qFORTH. The core inclu des both an expressio n and a return stac k. This architect ure
enables high-level language programming without any loss of efficiency or code density.

Figure 9. Microcontroller Core

MARC4 CORE

CCR

X

Y
SP
RP

RAM

256 x 4-bit

TOS

ALU

Reset

Clock

System

clock

Sleep

Reset

Program

memory

Instruction

bus

Instruction
decoder

Interrupt

controller

PC

Memory bus

I/O bus

On-chip peripheral modules

Components of Microcontroller Core

The core contai ns ROM, RAM, ALU, prog ram cou nter, RAM ad dress r egiste rs, instr uc­tion decoder and interrupt controller. The following sections describe each functional
block in more detail.

Program Memory The program memor y (EEPROM) is prog rammable with the c ustomer applicat ion

program during the fabrication of the microcontroller. The EEPROM is addressed by a
12-bit wide pr ogram counter , thus predefi ning a maximu m program ban k size of
4-Kbytes. The lowest user program memory address segment is taken up by a
512 bytes Zero page which contains predefined start addresses for interrupt service rou­tines and special subroutines accessible with single byte instructions (SCALL).

14

T48C862-R3

4554A–4BMCU–02/03

T48C862-R3

The corresponding memory map is shown in Figur e 4. Look-up tab les of consta nts can
also be held in ROM and are accessed via the microcontrollers’ built-in table instruction.

Figure 10. ROM Map of the Microcontroller Block

1F8h

FFFh

7FFh

1FFh
000h

EEPROM

(4 K x 8 bit)

Zero page

1F0h
1E8h
1E0h

page

SCALL addresses

020h
018h
010h

008h
000h

1E0h
1C0h

180h

140h
100h
0C0h
080h

040h

008h
000h

INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0

$RESET

$AUTOSLEEP

RAM The microcontroller block contains a 256 x 4-bit wide static random access memory

(RAM), which is used for the expression stack. The return stack and data memory are
used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM
address registers SP, RP, X and Y.

Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All

arithmetic, I/O and memory reference operations take their operands, and return their
results to the expression stack. The microcontroller performs the operations with the top
of stack items (TOS and TOS-1). The TOS register contains the top eleme nt of the
expression stack and works in the same way as an accumulator. This stack is also used
for passing parameters between subroutines and as a scratch pad area for temporary
storage of data.

Return Stack The 12-bit wide return stack is ad dr es se d by the re tu rn s tac k p oin ter ( RP ) . It i s us ed for

storing return ad dresses of subr outines, interrupt r outines and for keeping l oop index
counts. The return stack can also be used as a temporary storage area.

The microcontroller instruction set supports the exchange of data between the top ele­ments of the expression stack and the return stack. The two stacks within the RAM have
a user definable location and maximum depth.

4554A–4BMCU–02/03

15

Figure 11. RAM Map

FCh

X
Y

RAM

(256 x 4-bit)

Autosleep

FFh

Global
variables

Expression stack

30

TOS
TOS-1
TOS-2

4-bit

SP

SP

RAM address register:

RP

04h

00h

TOS-1

Expression
stack

Return
stack

07h
03h

Global
v

variables

Return stack

011

RP

12-bit

Registers The microcontroll er ha s se ven p rogramm able regis ters a nd o ne co nditio n cod e reg ister

(seeFigure 12).

Program Counter (PC) The program co unter is a 12-b it regis ter whic h conta ins th e addres s of the next in stru c-

tion to be fetched from the EEPROM. Instructions currently being executed are decoded
in the instruction decoder to determine the internal micro-operations. For linear code (no
calls or branches), the prog ram counte r is increm ented with every instructio n cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address . The program co unter is also used with the tab le instruc tion
to fetch 8-bit wide EEPROM constants.

Figure 12. Programming Mode l

PC

11

RP

SP

X

Y

7

7

7

TOS

C

CCR

--

0

Program counter

0

00

Return stack pointer

0

Expression stack pointer

0

RAM address register (X)

07

RAM address register (Y)

03

Top of stack register

03

B

Condition code register

I

Interrupt enable
Branch
Reserved
Carry / borrow

16

T48C862-R3

4554A–4BMCU–02/03

T48C862-R3

RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.

These registers allow access to any of the 256 RAM nibbles.

Expression Stack Pointer (SP) The stack poi nter conta ins the add ress of the next-to-t op 4-bit it em (TOS-1 ) of the

expression stack. The pointer is automatically pre-incremented if a nibble is moved onto
the stack or post-decremented if a nibble is removed from the stack. Every post -decre­ment operation moves the item (TOS-1) to the TOS register before the SP is
decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate
the start address of the expression stack area.

Return Stack Pointer (RP) The return stack pointer points to the top ele ment of the 12-bit wide return stack. T he

pointer automatically pre-increments if an element is moved onto the stack, or it post­decrements if an element is removed from the stack. The return stack pointer incre­ments and decrements in steps of 4. This means that every time a 12-bit element is
stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH
compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial­ized via >RP FCh.

RAM Address Registers (X and Y)

Top of Stack (TOS) The top of stack register is the ac cumulator of the microcontroller block. All arith-

Condition Code Register (CCR)

Carry/Borrow (C) The car ry /bor row flag indicates that the bor rowi ng o r c arr ying out of arithmetic logic unit

Branch (B) The branch flag co ntrol s the con di tio nal progr a m br an ch ing . S hou ld the br anc h flag has

Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt rou-

The X and Y registers are used to add ress any 4-bit item in the RAM. A fetch ope ratio n
moves the addressed nibble onto the TOS. A store operation moves the TOS to the
addressed RAM location. By using either the pre-increment or post-decrement address­ing mode arrays in the RAM can be compared, filled or moved.

metic/logic, memo ry refere nce and I /O opera tions us e this r egister. T he TOS register
receives data from the ALU, EEPROM, RAM or I/O bus.

The 4-bit wide condition code register contains the branch, the carry and the interrupt
enable flag. The se bits ind icate the curren t stat e of the CPU . The CCR flags are se t or
reset by ALU oper ations. The i nstructions SET_BCF, T OG_BF, CCR! and DI allow
direct manipulation of the condition code register.

(ALU) occurred during the last arithmetic operation. During shift and rotate operations,
this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.

been set by a previous instruction, a conditional branch will cause a jump. This flag is
affected by arithmetic, logic, shift, and rotate operations.

tines with the excepti on of the no n-maska ble rese t. After a rese t or while ex ecuting th e
DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core will
not accept any further interrupt requests until the interrupt enable flag has been set
again by either executing an EI or SLEEP instruction.

4554A–4BMCU–02/03

17

ALU The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top

two elements of the expression stack (TOS and TOS-1) and returns the result to the
TOS. The ALU operations affects the carry/borrow and branch flag in the condition code
register (CCR).

Figure 13. ALU Zero-address Operations

RAM

SP

TOS-1
TOS-2
TOS-3
TOS-4

TOS

ALU

CCR

I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-

cation between the c ore a nd th e on -chip per ipher als ta ke place via th e I/O bu s a nd th e
associated I/O control. With the microcontroller IN and OUT instructions, the I/O bus
allows a direct read or wr it e ac ces s to o ne o f th e 16 pr im ar y I/O ad dr es se s. Mor e abo ut
the I/O access to the on -chip perip herals is described in the sec tion “Perip heral Mod­ules”. The I/O bus is interna l and is not accessible by the customer on the final
microcontroller device, but it is used as the interface for the mic rocontroller emulation
(see also the section “Emulation”).

Instruction Set The microcontroller instruction set is optimized for the high level programming language

qFORTH. Many microc ontroll er instr uctions are qFO RTH wo rds. Th is ena bles th e com­piler to generate a fast and compact program code. The CPU has an instruction pipeline
allowing the controlle r to prefetc h an inst ructio n from EE PROM at the sam e time as the
present instruction is being e xecuted. The microc ontroller is a zer o-address machine,
the instructions contain only the operation to be performed and no source or destination
address fields. The operations are implicitly performed on the data placed on the stack.
There are one- and two- byte instructio ns which are exec uted within 1 to 4 machine
cycles. A microcontroller machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one byte long and are executed in a
single machine cycle. For more info rm ation re fer to the “MARC4 Pro grammer’s Guide”.

Interrupt Structure The microcontroller can handle interrupts with eight different priority levels. They can be

generated from the internal and external inter rupt sources or by a software interrupt
from the CPU itself. Each interrupt level has a hard-wired priority and an associated vec­tor for the service routine in the EEPROM (see Table 1). The programmer can postpone
the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An inter­rupt occurrence will still be registered, but the interrupt routine only started after the
I-flag is set. All interrupts can be masked, and the priority individually software config­ured by programming the appropriate control register of the interrupting module (see
section “Peripheral Modules”).

18

T48C862-R3

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T48C862-R3

Interrupt Processing For processing the eight interrupt levels, the microcontroller includes an interrupt con-

troller with two 8-bit wide interrupt pending and interrupt active registers. The interrupt
controller samples all interrupt requests during every non-I/O instruction cycle and
latches these in the in terrupt pe nding regi ster. If no hi gher pri ority int errupt is present in
the interrupt active register, it signals the CPU to interrupt the current program execu­tion. If the interrupt enable bit is set, the processor enters an interrupt acknowledge
cycle. During this cycle a short call (SCALL) instruction to the service routine is exe­cuted and the curr ent PC is sa ved on the re turn stack . An interru pt service routine is
completed with the RTI instruction. This instruction resets the corresponding bits in the
interrupt pending/a ctive regis ter and f etches the ret urn a ddress from the retur n st ack to
the program counter. Whe n the interrupt ena ble flag is rese t (triggering of in terrupt rou­tines is disabled), th e executi on of new int errupt ser vice r outine s is inh ibited but n ot the
logging of the interrupt requests in the interrupt pending register. The execution of the
interrupt is delayed until the inte rrupt enable flag is set again. Note that interrupts are
only lost if an interrupt request occurs while the corresponding bit in the pending register
is still set (i.e., the interrupt service routine is not yet finished).

It should be noted that automatic stacking of the RBR is not carried out by the hardware
and so if ROM banking is used, the RBR must be stacked on the expression stack by
the application program and res tored before the RTI. After a mast er reset (power-o n,
brown-out or watchdog reset), the interru pt enable flag and the inter rupt pending and
interrupt active register are all reset.

Interrupt Latency The interrupt latency is the time from the occur rence of the interrupt to the interrupt

service routine being activated. This is extremely short (taking between 3 to 5 machine
cycles depending on the state of the core).

Figure 14. Interrupt Handling

INT7

7

6

5

4

3

Priority level

2

1

0

Main /

Autosleep

INT5

INT5 active

INT3

INT3 active

INT7 active

RTI

INT2

RTI

INT2 pending

SWI0

INT2 active

INT0 pending

RTI

RTI

INT0 active

RTI

Main /

Autosleep

4554A–4BMCU–02/03

Time

19

Table 1. Interrupt Priority

Interrupt Priority ROM Addr ess Interrupt Opcode Function

INT0 Lowest 040h C8h (SCALL 040h) Software interrupt (SWI0)
INT1 | 080h D0h (SCALL 080h)
INT2 | 0C0h D8h (SCALL 0C0h) Timer 1 interrupt
INT3 | 100h E8h (SCALL 100h)
INT4 | 140h E8h (SCALL 140h) Timer 2 in terrupt

INT5 | 180h F0h (SCALL 180h) Timer 3 interrupt
INT6
INT7 Highest 1E0h FCh (SCALL 1E0h) Voltage monitor (VM) interrupt

| 1C0h F8h (SCALL 1C0h)

External hardware interrupt, any edge at BP52 or
BP53

SSI interrupt or ex te rnal hardw are in terrupt at B P 40
or BP43

External hardware interrupt, at an y edge at BP5 0 or
BP51

Table 2. Hardware Interrupts

Interrupt Mask

Interrupt

INT1 P5CR
INT2 T1M T1IM Timer 1

INT3 SISC SIM SSI buffer full/empty or BP40/BP43 interrupt
INT4 T2CM T2IM Timer 2 compare match/overflow

T3CM1

INT5

INT6 P5CR
INT7 VCM VIM External/internal voltag e mon itoring

T3CM2

T3C

P52M1, P52M2
P53M1, P53M2

T3IM1
T3IM2

T3EIM

P50M1, P50M2
P51M1, P51M2

Interrupt SourceRegister Bit

Any edge at BP52
any edge at BP53

Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)

Any edge at BP50,
any edge at BP51

Software Interrupts The programmer ca n generate interrupts by using the software interrupt ins truction

(SWI), which is supporte d in qFO RTH by pre defined m acros na med SW I0...SW I7. Th e
software triggered inte rrupt operates exactly like any hardw are triggered interrupt. The
SWI instruction takes the top two elements from the expression stack and writes the cor­responding bits via the I/O bus to th e i nter rup t pending register. T heref or e, by us in g th e
SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for
later execution.

Hardware Interrupts In the microcontroller block, there are eleven hardware interrupt s ources with seven

different levels. Each source can be masked individually by mask bits in the correspond­ing control registers. An overview of the possible h ardware configurations is shown in
Table 3.

20

T48C862-R3

4554A–4BMCU–02/03

T48C862-R3

Master Reset The master reset forces the CPU into a well-defined condition. It is unmaskable and is

activated independent of the current program state. It can be triggered by either initial
supply power-up, a short collapse of the power supply, brown-out detection circuitry,
watchdog time-out, or an external input clock supervisor stage (see Figure 15). A master
reset activation will rese t the i nterr upt enab le fl ag, the in ter rupt pe ndi ng r egis ter and th e
interrupt active regi ster. Durin g the power- on reset pha se, the I/O bus contr ol signals
are set to reset m ode, th ereby , init ializi ng al l on- chip periphe rals . All b i-di rection al por ts
are set to input mode

Attention: During any reset phase, the BP20/NTE input is driven towards V
additional internal strong pull-up transistor. This pin must not be pulled down to V

by an

DD

SS

dur-

ing reset by any external circuitry representing a resistor of less than 150 kW.
Releasing the reset res ults in a sh ort call inst ructi on (opc ode C1h) to the R OM add ress

008h. This activates the initializ ation routine $RESET which in turn has to initia lize all
necessary RAM variables, stack pointers and peripheral configuration registers (see
Table 6).

Figure 15. Reset Configuration

V

DD

Pull-up

CL

NRST

Reset

timer

res
CL=SYSCL/4

Power-on

reset

Brown-out

detection

Watch-

res

dog

Internal

reset

V

DD

V

SS

V

DD

V

SS

CWD

Po we r-on Reset and Brown-out Detection

4554A–4BMCU–02/03

Ext. clock

supervisor

ExIn

The microcontrolle r bloc k has a ful ly in tegr ate d po wer -on r eset an d br own -o ut de tect io n
circuitry. For reset generation no external components are needed.

These circuits ensure that the core is held in the reset state until the minimum operating
supply voltage has been reached. A reset condition will also be generated should the
supply voltage drop momentarily below the minimum operating l evel except when a
power-down mode is activated (the core is in SLEEP mode and the peripheral clock is
stopped). In this power-down mode the brown-out detection is disabled.

Two values for the brown-out voltage threshold are programmable via the BOT-bit in the
SC-register.

21

A power-on reset pulse i s generat ed by a VDD rise across the default BOT voltage level
(1.7 V). A brown-out reset pulse is generated when V

falls below the br own-o ut volt -

DD

age threshold. T wo values for t he brown-o ut volt age thres hold are programma ble via
the BOT-bit in the SC-register. When the controller runs in the upper supply voltage
range with a high system clock fr equency, the high threshold must be used. When it
runs with a lower system c lock freq uency , the lo w thresho ld and a wider su pply v oltag e
range may be chosen. F or further details , see the e lectrical speci fication and the SC­register description for BOT programming.

Figure 16. Brown-out Detection

V

DD

2.0 V

1.7 V

t

CPU

Reset

CPU

Reset

BOT = '1'

BOT = '0'

d

t

d

t

t

d

td= 1.5 ms (typically)

BOT = 1, low brown-out voltage threshold 1.7 V (is reset value).
BOT = 0, high brown-out voltage threshold 2.0 V.

Watchdog Reset The watchdog’s function can be enabled at the WDC-register and triggers a reset with

every watchdog counter overflow. To suppress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog register address (CWD). The
CPU reacts in exactly the same manner as a reset stimulus from any of the above
sources.

External Clock Supervisor The external input clock su per v isor func tion c an be enab led if the ex te rn al inpu t cl oc k is

selected within the CM- and SC-reg isters of the clock module . Th e CPU reacts in
exactly the same manner as a reset stimulus from any of the above sources.

Voltage Monitor The voltage monitor consists of a comparator with internal voltage reference. It is used

to supervise the supply voltage or an external voltage at the VMI-pin. The comparator
for the supply voltage has three internal programmable thresholds one lower threshold
(2.2 V), one middle threshold (2.6 V) and one higher threshold (3.0 V). For external volt­ages at the VMI-pin, the comparator threshold is set to V
indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this thresh­old. An interrupt can be g enerated wh en the V MS-b it is set or res et to de tect a risin g or
falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit
(VIM) is reset in the VMC-register.

= 1.3 V. The VMS-bit

BG

22

T48C862-R3

4554A–4BMCU–02/03

Figure 17. Voltage Monitor

BP41/
VMI

VMC :

Voltage monitor

IN

VM2

VM1 VM0 VIM

T48C862-R3

V

DD

OUT

INT7

Voltage Monitor Control/Status Register

VMST :

- - res

VMS

Primary register address: "F"hex

Bit 3Bit 2Bit 1Bit 0

VMC: Write VM2 VM1 VM0 VIM Reset value: 1111b

VMST: R ead – – reserved VMS Reset value: xx11b

VM2: Voltage monitor Mode bit 2
VM1: Voltage monitor Mode bit 1
VM0: Voltage monitor Mode bit 0

VM2 VM1 VM0 Function

1 1 1 Disable voltage monitor
110
101Not allowed
100

011

010

001
000Not allowed

External (VIM-input), internal reference threshold (1.3 V), interrupt
with negative slope

External (VMI-input), internal reference threshold (1.3 V), interrupt
with positive slope

Internal (supply voltage), high threshold (3.0 V), interrupt with
negative slope

Internal (supply voltage), middle threshold (2.6 V), interrupt with
negative slope

Internal (supply voltage), low threshold (2.2 V), interrupt with
negative slope

4554A–4BMCU–02/03

VIM Voltage Interrupt Mask bit

VIM = 0, voltage monitor interrupt is enabled
VIM = 1, voltage monitor interrupt is disabled

VMS Voltage Monitor Status bit

VMS = 0, the voltage at the comparator input is below V
VMS = 1, the voltage at the comparator input is above V

Ref

Ref

23

Figure 18. Internal Supply Voltage Supervisor

Low threshold

VMS = 1

V

DD

3.0 V

2.6 V

2.2 V

Middle threshold
High threshold

Low threshold
Middle threshold
High threshold

VMS = 0

Figure 19. External Input Voltage Supervisor

VMI

Negative slope

VMS = 1

1.3 V
VMS = 0

Positive slope

Internal reference level

Interrupt positive slope

VMS = 1
VMS = 0

Interrupt negative slope

t

Clock Generation

Clock Module The T48C862-R3 contains a clock module with 4 different internal oscillator types: two

RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins
OSC1 and OSC2 are the inter face to co nnect a crys tal eith er to the 4-M Hz, or to the
32-kHz crystal oscillator. OSC1 can be used as input for external clocks or to connect an
external trimming resistor for the RC-oscillator 2. All necessary circuitry, except the crys­tal and the trimming resistor, is integrated on-chip. One of these oscillator types or an
external input clock can be selected to generate the system clock (SYSCL).

24

T48C862-R3

In applications that do not r equire exact timing, it is possible to use the fully integrated
RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency
tolerance is better than ± 50%. The RC-oscillator 2 is a trimmable oscillator whereby the
oscillator frequency can be trimmed with an external resistor attached between OSC1
and V

. In this configuration, the RC-oscillator 2 frequency can be maintained stable

DD

with a tolerance of ± 15% over the full operating temperature and voltage range.
The clock module is programmable via software with the clock management register

(CM) and the system configuration register (SC). The requir ed oscillator c onfiguration
can be selected with the OS1-bit and the OS0-bit in the SC-register. A programmable
4-bit divider stage allows the adjustment of the system clock speed. A special feature of
the clock management is that an external oscillator may be used and switched on and
off via a port pin for the power-down mode. Before the external clock is switched off, the
internal RC-oscillator 1 must be s elected with the CCS-bit and then the SLEE P mode
may be activated. In this state an interrupt can wake up the controller with the RC-oscil­lator, and the external oscillator can be activated and selected by software. A
synchronization stage avoids too short clock periods if the clock source or the clock
speed is changed. If an external input clock is selected, a supervisor circuit monitors the
external input and gen er ate s a har dwa re reset if the external cl ock s ou rc e f ail s or dr ops
below 500 kHz for more than 1 ms.

4554A–4BMCU–02/03

Figure 20. Clock Module

T48C862-R3

OSC1

OSC2

*

*

*

Configurable

Osci

n

Oscou

t

Ext. clock

ExI

n

RC oscillator2

R

Trim

4-MHz oscillator

Osci

n

Oscou

t

32-kHz oscillator

Osci

n

Oscou

t

BOT - - - OS1 OS0

SC:

ExOu

t

Stop

RCOut2

Stop

4Out

Stop

32Out

RC

oscillator 1

RCOut1
ControlStop

Osc­Stop

IN1

Cin

IN2

Sleep
WDL

NSTOP CCS CSS1 CSS0CM:

/2 /2 /2 /2

Divide

r

Cin/16

32

kHz

Table 3. Clock Modes

Clock Source for SYSCL

Mode OS1 OS0

1 1 1 RC-oscillator 1 (internal) External input clock C

RC-oscillator 2 with

2 0 1 RC-oscillator 1 (internal)

external trimming

resistor
3 1 0 RC-oscillator 1 (internal) 4-MHz oscillator C
4 0 0 RC-oscillator 1 (internal) 32-kHz oscillator 32 kHz

Clock Source

SYSCL

SUBCL

for SUBCLCCS = 1 CCS = 0

/16

in

C

/16

in

/16

in

Oscillator Circuits and External Clock Input Stage

RC-oscillator 1 Fully Integrated

The clock module generates two output clocks. One is the system clock (SYSCL) and
the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals
and the SUBCL can supply only the peripherals with cloc ks. The modes for clock
sources are programmable with the OS1-bit and OS0-bit in the SC-register and the
CCS-bit in the CM-regi ste r.

The microcontroller block se ries consi sts of fou r different in ternal os cillators: t wo RC­oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external
clock input stage.

For timing insensitive applications, it is possible to use the fully integrated RC
oscillator 1. It operates without any external components and saves additional costs.
The RC-oscillator 1 center frequency tolerance is better than ±50% over the full temper­ature and voltage r ange. The basic center fr equency of the RC-oscilla tor 1 is
f

» 3.8 MHz. The RC oscillator 1 is selected by default after power-on reset.

O

4554A–4BMCU–02/03

25

Figure 21. RC-oscillator 1

RC

oscillator 1

RcOut1

Stop

Control

RcOut1

Osc-Stop

External Input Clock The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it

meets the specified duty cycle, rise and fall times and input level s. Additionally, the
external clock stage conta ins a superv isory circuit for the input clock . The supervi sor
function is controlled via the OS1, OS0-bit in the SC-register and the CCS-bit in the CM­register. If the external input clock is missing for more than 1 ms and CCS = 0 is set in
the CM-register, the supervisory circuit generates a hardware reset.

Figure 22. External Input Clock

RC-oscillator 2 with External Trimming Resistor

Ext.

Clock

or

Ext.

Clock

OSC1

OSC2

Ext. input clock

ExOut

ExIn

Stop

Clock monitor

RcOut1

Osc-Stop

CCS

Res

OS1 OS0 CCS Supervisor Reset Output (Res)

110 Enable
111 Disable
x 0 x Disable

The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator fre­quency can be tri mmed with an exte rnal resistor betw een OSC1 and V

. In this

DD

configuration, the RC-oscillator 2 frequency can be maintained stable with a tolerance of
±10% over the full operating temperature and a voltage range V

from 2.5 V to 6.0 V.

DD

For example:
An output frequency at the RC-oscill ator 2 of 2 MHz can be obtai ned by connecting a
resistor R

= 360 kW (see Figure 23).

ext

26

T48C862-R3

4554A–4BMCU–02/03

T48C862-R3

Figure 23. RC-oscillator 2

V

DD

R

ext

OSC1

OSC2

4-MHz Oscillator The microcontroller block 4-MHz oscillato r options need a crystal or ceramic r esonator

connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscilla­tor circuitry is integrated, except the actual crystal, resonator, C3 and C4.

Figure 24. 4-MHz Crystal Oscillator

RC

oscillator 2

R

Trim

RcOut2

Stop

RcOut2

Osc-Stop

OSC1

XTAL
4 MHz

OSC2

*

Configurable

Figure 25. Ceramic Resonator

C3

OSC1

OSC2

C4

*

Configurable

Cer.
Res

*

C1

*

C2

*

C1

*

C2

Oscin

4-MHz

oscillator

Oscout

Oscin

oscillator

Oscout

4-MHz

4Out

Stop

4Out

Stop

4Out

Osc-Stop

4Out

Osc-Stop

32-kHz Oscillator Some appli catio ns requ ire long- term tim e kee ping o r lo w res olution t iming . In thi s c ase,

an on-chip, low power 32-kHz cr ystal oscillator can be use d to generate both the
SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. Th e
32-kHz crystal oscillator can not be stopped while the power-down mode is in operation.

27

4554A–4BMCU–02/03

Figure 26. 32-kHz Crystal Oscillator

OSC1

XTAL

32 kHz

OSC2

*

Configurable

*

C1

*

C2

Oscin

32-kHz

oscillator

Oscout

32Out

32Out

Clock Management The clock management register controls the system clock divider and synchronization

stage. Writing to this register triggers the synchronization cycle.

Clock Management Register (CM)

Bit 3Bit 2Bit 1Bit 0

CM: NSTOP CCS CSS1 CSS0 Reset value: 1111b

Auxiliary register address: "3"hex

NSTOP Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode

CCS Core Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external
clock source or the internal RC-oscillator 2 with the external resistor at OSC1
generates SYSCL dependent on the setting of OS0 and OS1 in the system
configuration register

CSS1 Core Speed Select 1
CSS0 Core Speed Select 0

CSS1 CSS0 Divider Note

0016
118Reset value
104
012

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T48C862-R3

4554A–4BMCU–02/03

T48C862-R3

System Configuration Register (SC)

Primary register address: "3"hex

Bit 3Bit 2Bit 1Bit 0

SC: write BOT --- OS1 OS0 Reset value: 1x11b

BOT Brown-Out Threshold

BOT = 1, low brown-out voltage threshold (1.7 V)
BOT = 0, high brown-out voltage threshold (2.0 V)

OS1 Oscillator Select 1

OS0 Oscillator Select 0

Mode OS1 OS0 Input for SUBCL Selecte d Oscillators

111 C
201 C
310 C

400 32 kHz

Note: If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.

16 RC-oscillator 1 and external input clock

in/

/16 RC-oscillator 1 and RC-oscillator 2

in

/16 RC-oscillator 1 and 4-MHz crystal oscillator

in

RC-oscillator 1 and 32-kHz crystal
oscillator

Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system

power consumption in applications where the microcontroller is not fully utilized. In this
mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruc­tion. This instruction sets the interrupt enable bit (I) in the condition code register to
enable all interrup ts and stops the core. Durin g the sleep mode the periphe ral modules
remain active and are able to gene rate interrupt s. The microco ntroller exits the s leep
mode by carrying out any interrupt or a reset.

The sleep mode c an only be kept whe n none of th e interr upt pend ing or ac tive re gister
bits are set. The application of the $AUTOSLEEP routine ensures the correct function of
the sleep mode. For standard applications use the $AUTOSLEEP r outine to enter the
power-down mode. Using the S LE EP in str uc tion i ns tea d of th e $A UTO SLE E P follo win g
an I/O instruction requ ires to ins ert 3 non-I/O inst ructi on cyc les (for exam ple N OP N OP
NOP) between the IN or OUT command and the SLEEP command.

The total power consumption is directly proportional to the active time of the microcon­troller. For a rough estimation of the expected average system current consumption, the
following formula should be used:

I

(VDD,f

total

IDD depends on VDD and f

syscl

) = I

syscl

+ (IDD ´ t

Sleep

active/ttotal

)

4554A–4BMCU–02/03

29

The microcontroller block has various power-down modes. During the sleep mode the
clock for the microcontroller block core is stopped. With the NSTOP-bit in the clock man­agement register (CM), it is programmable if the clock for the on-chip peripherals is
active or stopped during the s leep m ode. If the cloc k fo r the co re an d the perip herals is
stopped, the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it
is selected it runs continuously independent of the NSTOP-bit. If the oscillator is stopped
or the 32-kHz oscillator is selected, power consumption is extremely low.

Table 4. Power-down Modes

RC-oscillator 1

Brown-

CPU

Mode

Active RUN NO Active RUN RUN YES

Power-

down

SLEEP SLEEP YES STOP STOP RUN STOP

Note: 1. Osc-Stop = SLEEP and NSTOP and WDL

Core

SLEEP NO Active RUN RUN YES

Osc-

Stop

(1)

out

Function

RC-oscillator 2

4-MHz

Oscillator

32-kHz

Oscillator

External

Input

Clock

Peripheral Modules

Addressing Peripheral s Accessing the peripheral modules takes place via the I/O bus (see Figure 21). The IN or

OUT instructions allow direct addressing of up to 16 I/O modul es. A dual register
addressing scheme has be en ado pted to ena ble dir ect a ddressi ng of the prim ary regi s­ter. To address the auxiliary register, the access must be switched with an auxiliary
switching m odul e. Thus , a si ngle IN (or OU T) to the module address will read (or write
into) the module primar y register . Accessin g the auxili ary registe r is perform ed with the
same instruction preceded by writing the module address into the auxiliary switching
module. Byte wide regist ers are accessed by multiple IN- (or OUT-) instructions. For
more complex peripheral modules, with a larger number of registers, extended address­ing is used. In this case, a bank of up to 16 subport registers are indirectly addressed
with the subport address. The first OUT-instruction writes the subport address to the sub
address register, the second IN- or OUT-instruction reads data from or writes data to the
addressed subport.

30

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4554A–4BMCU–02/03