Rainbow Electronics SCAN92LV090 User Manual

February 2005

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

General Description

The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of

The receiver threshold is less than common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels.

This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test

1V.

100 mV over a±1V

access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST).

Features

n IEEE 1149.1 (JTAG) Compliant n Bus LVDS Signaling n Low power CMOS design n High Signaling Rate Capability (above 100 Mbps) n 0.1V to 2.3V Common Mode Range for V

100 mV Receiver Sensitivity

n Supports open and terminated failsafe on port pins n 3.3V operation n Glitch free power up/down (Driver & Receiver disabled) n Light Bus Loading (5 pF typical) per Bus LVDS load n Designed for Double Termination Applications n Balanced Output Impedance n Product offered in 64 pin LQFP package and BGA

package

n High impedance Bus pins on power off (V

= 200mV

= 0V)

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN

Simplified Functional Diagram

10124201

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Connection Diagrams

SCAN92LV090

Top View

Order Number SCAN92LV090VEH

See NS Package Number VEH064DB

10124202

Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A

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10124216

Pinout Description

Pin Name TQFP Pin # BGA Pin # Input/Output Descriptions

DO+/RI+ 27, 31, 35, 37, 41,

45, 47, 51, 55

DO−/RI− 26, 30, 34, 36, 40,

44, 46, 50, 54

2, 6, 12, 18, 20, 22,

58, 60, 62

RO 3, 7, 13, 19, 21, 23,

59, 61, 63

17 H1 I Receiver Enable TTL Input (Active Low).

DE 16 G2 I Driver Enable TTL Input (Active High).

GND 4, 5, 9, 14, 25, 56 B1, B4, D3, E1, F2,

10, 15, 24, 57, 64 A1, A5, F1, F3, H4 Power VCCfor digital circuitry (must connect to VCCon PC

AGND 28, 33, 43, 49, 53 A8, C5, D7, F5, G7 Power Ground for analog circuitry (must connect to GND

TRST

29, 32, 42, 48, 52 A6, B7, C8, H6, H8 Power Analog VCC(must connect to VCCon PC board).

39 F8 I Test Reset Input to support IEEE 1149.1 (Active

TMS 38 E7 I Test Mode Select Input to support IEEE 1149.1

TCK 1 B2 I Test Clock Input to support IEEE 1149.1

TDI 8 D1 I Test Data Input to support IEEE 1149.1

TDO 11 E2 O Test Data Output to support IEEE 1149.1

A7, B8, C6, D5, D8,

E6, F7, G5, G6

B5, B6, C7, D6, E5,

E8, F6, G8, H7

A2, A4, C3, C4, D2,

E3, G3, G4, H3

A3, B3, C1, C2, D4,

E4, F4, G1, H2

I/O True Bus LVDS Driver Outputs and Receiver Inputs.

I/O Complimentary Bus LVDS Driver Outputs and

Receiver Inputs.

I TTL Driver Input.

O TTL Receiver Output.

Power Ground for digital circuitry (must connect to GND on

PC board). These pins connected internally.

board). These pins connected internally.

on PC board). These pins connected internally.

These pins connected internally.

Low)

SCAN92LV090

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Absolute Maximum Ratings

(Notes 2, 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/

SCAN92LV090

Distributors for availability and specifications.

Supply Voltage (V

) 4.0V

Junction Temperature +150˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature

(Soldering, 4 sec.) 260˚C

Enable Input Voltage

(DE, RE)

Driver Input Voltage (D

) −0.3V to (VCC+0.3V)

−0.3V to (VCC+0.3V)

Recommended Operating Conditions

Receiver Output Voltage

) −0.3V to (VCC+0.3V)

OUT

Bus Pin Voltage (DO/RI

ESD (HBM 1.5 kΩ, 100 pF)

) −0.3V to +3.9V

4.5 kV

Driver Short Circuit Duration momentary

Receiver Short Circuit Duration momentary

Maximum Package Power Dissipation at 25˚C

LQFP 1.74 W

Supply Voltage (V

) 3.0 3.6 V

Receiver Input Voltage 0.0 2.4 V

Operating Free Air Temperature −40 +85 ˚C

Maximum Input Edge Rate

(Note 6)(20% to 80%) ∆t/∆V

Data 1.0 ns/V

Control 3.0 ns/V

Min Max Units

Derate LQFP Package 13.9 mW/˚C

DC Electrical Characteristics

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

∆V

OSD

CMR

Output Differential Voltage

RL=27Ω, Figure 1 DO+/RI+,

DO−/RI−

240 300 460 mV

VODMagnitude Change 27 mV

Offset Voltage 1.1 1.3 1.5 V

Offset Magnitude Change

Driver Output High Voltage

Driver Output Low Voltage

Output Short Circuit Current (Note 10)

Voltage Output High (Note 11)

RL=27Ω

VOD= 0V, DE = VCC, Driver outputs shorted together

VID= +300 mV IOH= −400 µA R

OUT

Inputs Open V

Inputs Terminated,

=27Ω

0.95 1.1 V

VCC−0.2 V

−0.2 V

510mV

1.4 1.65 V

|36| |65| mA

Voltage Output Low IOL= 2.0 mA, VID= −300 mV 0.05 0.075 V

Receiver Output Dynamic Current (Note

10)

Input Threshold High DE = 0V, VCM= 1.5V DO+/RI+,

Input Threshold Low −100 mV

Receiver Common Mode Range

Input Current DE = 0V, RE = 2.4V,

= 300mV, V

= −300mV, V

OUT=VCC

OUT

−1.0V −110 |75|

= 1.0V |75|

DO−/RI−

VIN= +2.4V or 0V

= 0V, VIN= +2.4V or 0V −20

110 mA

+100 mV

|VID|/2 2.4 −

−25

1 +25 µA

1 +20 µA

71.7˚C/W

10.9˚C/W

|/2

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