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201910BG95M3
Users Manual
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Quectel Wireless Solutions 201910BG95M3 Users Manual

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BG95 Hardware Design
LPWA Module Series
Rev. BG95_Hardware_Design_V1.0
Date: 2019-05-15
Status: Preliminary
www.quectel.com
LPWA Module Series
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BG95_Hardware_Design 1 / 80
About the Document
History
Revision Date Author Description
LPWA Module Series
1.0 2019-05-15
Lim PENG/
Garey XIE
Initial
BG95_Hardware_Design 2 / 80
LPWA Module Series
Contents
About the Document ................................................................................................................................ 2
Contents .................................................................................................................................................... 3
Table Index ............................................................................................................................................... 5
Figure Index .............................................................................................................................................. 7
1 Introduction ....................................................................................................................................... 8
1.1. Safety Information .................................................................................................................... 9
2 Product Concept ............................................................................................................................. 13
2.1. General Description ................................................................................................................ 13
2.2. Key Features .......................................................................................................................... 15
2.3. Functional Diagram ................................................................................................................ 18
2.4. Evaluation Board .................................................................................................................... 19
3 Application Interfaces ..................................................................................................................... 20
3.1. Pin Assignment ...................................................................................................................... 21
3.2. Pin Description ....................................................................................................................... 22
3.3. Operating Modes .................................................................................................................... 29
3.4. Power Saving ......................................................................................................................... 30
3.4.1. Airplane Mode .............................................................................................................. 30
3.4.2. Power Saving Mode (PSM).......................................................................................... 31
3.4.3. Extended Idle Mode DRX (e-I-DRX) ............................................................................ 32
3.4.4. Sleep Mode* ................................................................................................................ 32
3.4.4.1. UART Application .............................................................................................. 32
3.5. Power Supply ......................................................................................................................... 33
3.5.1. Power Supply Pins ....................................................................................................... 33
3.5.2. Decrease Voltage Drop ............................................................................................... 34
3.5.3. Monitor the Power Supply ............................................................................................ 35
3.6. Turn on and off Scenarios ...................................................................................................... 35
3.6.1. Turn on Module Using the PWRKEY Pin ..................................................................... 35
3.6.2. Turn off Module ............................................................................................................ 37
3.6.2.1. Turn off Module Using the PWRKEY Pin ........................................................... 37
3.6.2.2. Turn off Module Using AT Command ................................................................ 38
3.7. Reset the Module ................................................................................................................... 38
3.8. (U)SIM Interface ..................................................................................................................... 40
3.9. USB Interface ......................................................................................................................... 42
3.10. UART Interfaces ..................................................................................................................... 44
3.11. PCM* and I2C* Interfaces ......................................................................................................
47
3.12. Network Status Indication ....................................................................................................... 48
3.13. STATUS ................................................................................................................................. 49
3.14. Behaviors of RI* ..................................................................................................................... 49
3.15. USB_BOOT Interface ............................................................................................................. 50
3.16. ADC Interfaces ....................................................................................................................... 51
BG95_Hardware_Design 3 / 80
LPWA Module Series
3.17. GPIO Interfaces ...................................................................................................................... 52
4 GNSS Receiver ................................................................................................................................ 54
4.1. General Description ................................................................................................................ 54
4.2. GNSS Performance ................................................................................................................ 54
4.3. Layout Guidelines ................................................................................................................... 55
5 Antenna Interfaces .......................................................................................................................... 56
5.1. Main Antenna Interface .......................................................................................................... 56
5.1.1. Pin Definition ................................................................................................................ 56
5.1.2. Operating Frequency ................................................................................................... 56
5.1.3. Reference Design of RF Antenna Interface ................................................................. 57
5.1.4. Reference Design of RF Layout ................................................................................... 58
5.2. GNSS Antenna Interface ........................................................................................................ 60
5.3. Antenna Installation ................................................................................................................ 61
5.3.1. Antenna Requirements ................................................................................................ 61
5.3.2. Recommended RF Connector for Antenna Installation ................................................ 62
6 Electrical, Reliability and Radio Characteristics .......................................................................... 64
6.1. Absolute Maximum Ratings .................................................................................................... 6
4
6.2. Power Supply Ratings ............................................................................................................ 64
6.3. Operation and Storage Temperatures .................................................................................... 65
6.4. RF Output Power .................................................................................................................... 65
6.5. RF Receiving Sensitivity ......................................................................................................... 66
6.6. Electrostatic Discharge ........................................................................................................... 67
7 Mechanical Dimensions.................................................................................................................. 69
7.1. Mechanical Dimensions of the Module ................................................................................... 69
7.2. Recommended Footprint ........................................................................................................ 71
7.3. Design Effect Drawings of the Module .................................................................................... 72
8 Storage, Manufacturing and Packaging ........................................................................................ 73
8.1. Storage ................................................................................................................................... 73
8.2. Manufacturing and Soldering .................................................................................................. 74
8.3. Packaging ............................................................................................................................... 75
9 Appendix A References .................................................................................................................. 77
10 Appendix B GPRS Coding Schemes ............................................................................................. 80
11 Appendix C GPRS Multi-slot Classes ............................................................................................
81
12 Appendix D EDGE Modulation and Coding Schemes .................................................................. 83
BG95_Hardware_Design 4 / 80
LPWA Module Series
Table Index
TABLE 1: VERSION SELECTION FOR BG95 SERIES MODULE ................................................................... 13
TABLE 2: FREQUENCY BANDS AND GNSS TYPES OF BG95 SERIES MODULE ...................................... 13
TABLE 3: KEY FEATURES OF BG95 SERIES MODULES ............................................................................. 16
TABLE 4: DEFINITION OF I/O PARAMETERS ................................................................................................ 22
TABLE 5: PIN DESCRIPTION ........................................................................................................................... 23
TABLE 6: OVERVIEW OF OPERATING MODES ............................................................................................ 30
TABLE 7: VBAT AND GND PINS ...................................................................................................................... 34
TABLE 8: PIN DEFINITION OF PWRKEY ........................................................................................................ 36
TABLE 9: PIN DEFINITION OF RESET_N ....................................................................................................... 38
TABLE 10: PIN DEFINITION OF (U)SIM INTERFACE ..................................................................................... 40
TABLE 11: PIN DEFINITION OF USB INTERFACE ......................................................................................... 42
TABLE 12: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................ 44
TABLE 13: PIN DEFINITION OF DEBUG UART INTERFACE......................................................................... 45
TABLE 14: PIN DEFINITION OF GNSS UART INTERFACE ........................................................................... 45
TABLE 15: LOGIC LEVELS OF DIGITAL I/O ................................................................................................... 45
TABLE 16: PIN DEFINITION OF PCM AND I2C INTERFACES ...................................................................... 47
TABLE 17: PIN DEFINITION OF NETLIGHT .................................................................................................... 48
TABLE 18: WORKING STATE OF NETLIGHT ................................................................................................. 48
TABLE 19: PIN DEFINITION OF STATUS ....................................................................................................... 49
TABLE 20: DEFAULT BEHAVIORS OF RI ....................................................................................................... 50
TABLE 21: PIN DEFINITION OF USB_BOOT INTERFACE............................................................................. 50
TABLE 22: PIN DEFINITION OF ADC INTERFACE ......................................................................................... 51
TABLE 23: CHARACTERISTICS OF ADC INTERFACES ................................................................................ 52
TABLE 24: PIN DEFINITION OF GPIO INTERFACES ..................................................................................... 52
TABLE 25: LOGIC LEVELS OF GPIO INTERFACES ...................................................................................... 53
TABLE 26: GNSS PERFORMANCE ................................................................................................................. 54
TABLE 27: PIN DEFINITION OF MAIN ANTENNA INTERFACE ..................................................................... 56
TABLE 28: BG95 OPERATING FREQUENCY ................................................................................................. 56
TABLE 29: PIN DEFINITION OF GNSS ANTENNA INTERFACE .................................................................... 60
TABLE 30: GNSS FREQUENCY ...................................................................................................................... 60
TABLE 31: ANTENNA REQUIREMENTS ......................................................................................................... 61
TABLE 32: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 64
TABLE 33: POWER SUPPLY RATINGS .......................................................................................................... 64
TABLE 34: OPERATION AND STORAGE TEMPERATURES ......................................................................... 65
TABLE 35: BG95 RF OUTPUT POWER ........................................................................................................... 66
TABLE 36: BG95 CONDUCTED RF RECEIVING SENSITIVITY ..................................................................... 66
TABLE 37: ELECTROSTATIC DISCHARGE CHARACTERISTICS (25ºC, 45% RELATIVE HUMIDITY) ....... 68
TABLE 38: RECOMMENDED THERMAL PROFILE PARAMETERS .............................................................. 74
TABLE 39: REEL PACKAGING ........................................................................................................................ 76
TABLE 40: RELATED DOCUMENTS ............................................................................................................... 77
TABLE 41: TERMS AND ABBREVIATIONS ..................................................................................................... 77
BG95_Hardware_Design 5 / 80
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TABLE 42: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 80
TABLE 43: GPRS MULTI-SLOT CLASSES ...................................................................................................... 81
TABLE 44: EDGE MODULATION AND CODING SCHEMES .......................................................................... 83
BG95_Hardware_Design 6 / 80
LPWA Module Series
Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 18
FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 21
FIGURE 3: SLEEP MODE APPLICATION VIA UART ...................................................................................... 33
FIGURE 4: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ..................................................... 34
FIGURE 5: STAR STRUCTURE OF THE POWER SUPPLY ........................................................................... 35
FIGURE 6: TURN ON THE MODULE USING DRIVING CIRCUIT ................................................................... 36
FIGURE 7: TURN ON THE MODULE USING KEYSTROKE ........................................................................... 36
FIGURE 8: TIMING OF TURNING ON MODULE ............................................................................................. 37
FIGURE 9: TIMING OF TURNING OFF MODULE ........................................................................................... 38
FIGURE 10: TIMING OF RESET MODULE ...................................................................................................... 39
FIGURE 11: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 39
FIGURE 12: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 39
FIGURE 13: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 41
FIGURE 14: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR 41
FIGURE 15: REFERENCE CIRCUIT OF USB INTERFACE ............................................................................ 43
FIGURE 16: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 46
FIGURE 17: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 46
FIGURE 18: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC ................................... 47
FIGURE 19: REFERENCE CIRCUIT OF THE NETWORK STATUS INDICATOR .......................................... 48
FIGURE 20: REFERENCE CIRCUIT OF STATUS ........................................................................................... 49
FIGURE 21: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 51
FIGURE 22: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................ 58
FIGURE 23: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ..................................................................... 58
FIGURE 24: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB ................................................. 59
FIGURE 25: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE
GROUND) .................................................................................................................................................. 59
FIGURE 26: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE
GROUND) .................................................................................................................................................. 59
FIGURE 27: REFERENCE CIRCUIT OF GNSS ANTENNA INTERFACE ....................................................... 61
FIGURE 28: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 62
FIGURE 29: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 63
FIGURE 30: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) .......................................................... 63
FIGURE 31: MODULE TOP AND SIDE DIMENSIONS .................................................................................... 69
FIGURE 32: MODULE BOTTOM DIMENSIONS (BOTTOM VIEW) ................................................................. 70
FIGURE 33: RECOMMENDED FOOTPRINT (TOP VIEW) .............................................................................. 71
FIGURE 34: TOP VIEW OF THE MODULE ...................................................................................................... 72
FIGURE 35: BOTTOM VIEW OF THE MODULE .............................................................................................. 72
FIGURE 36: RECOMMENDED REFLOW SOLDERING THERMAL PROFILE ............................................... 74
FIGURE 37: TAPE DIMENSIONS ..................................................................................................................... 75
FIGURE 38: REEL DIMENSIONS ..................................................................................................................... 76
BG95_Hardware_Design 7 / 80
LPWA Module Series
1 Introduction
This document defines BG95 module and describes its air interface and hardware interfaces which are
connected with customers’ applications.
This document can help customers quickly understand the interface specifications, electrical and
mechanical details, as well as other related information of BG95. To facilitate its application in different
fields, reference design is also provided for customers’ reference. Associated with application notes and
user guides, customers can use the module to design and set up mobile applications easily.
BG95_Hardware_Design 8 / 80
LPWA Module Series
1.1. Safety Information
The following safety precautions must be observed during all phases of the operation, such as usage,
service or repair of any cellular terminal or mobile incorporating BG95. Manufacturers of the cellular
terminal should send the following safety information to users and operating personnel, and incorporate
these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for
customers’ failure to comply with these precautions.
Full attention must be given to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If the device offers an Airplane Mode, then it should be
enabled prior to boarding an aircraft. Please consult the airline staff for more
restrictions on the use of wireless devices on boarding the aircraft.
Wireless devices may cause interference on sensitive medical equipment, so
please be aware of the restrictions on the use of wireless devices when in
hospitals, clinics or other healthcare facilities.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, please remember using emergency call. In order to make or receive a
call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as your phone or other cellular terminals. Areas with
potentially explosive atmospheres include fueling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust or metal powders, etc.
BG95_Hardware_Design 9 / 80
LPWA Module Series
1.2. FCC Certification Requirements.
According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a
mobile device.
And the following conditions must be met:
1. This Modular Approval is limited to OEM installation for mobile and fixed applications only. The antenna
installation and operating configurations of this transmitter, including any applicable source-based time-
averaging duty factor, antenna gain and cable loss must satisfy MPE categorical Exclusion Requirements
of 2.1091.
2. The EUT is a mobile device; maintain at least a 20 cm separation between the EUT and the user’s
body and must not transmit simultaneously with any other antenna or transmitter.
3.A label with the following statements must be attached to the host end product: This device contains
FCC ID: XMR201910BG96M3.
4.To comply with FCC regulations limiting both maximum RF output power and human exposure to RF
radiation, maximum antenna gain (including cable loss) must not exceed:
❒ GSM850:≤8.571 dBi
❒ GSM1900:≤10.030dBi
❒ Catm LTE Band2/25:≤11.000dBi
❒ Catm LTE Band4/66:≤8.000dBi
❒ Catm LTE Band5/26:≤12.541dBi
❒ Catm LTE Band12/85:≤11.798dBi
❒ Catm LTE Band13:≤12.214dBi
❒ Catm LTE Band14:≤12.272 dBi
❒ NB LTE Band2/25:≤11.000dBi
❒ NB LTE Band4/66:≤8.000dBi
❒ NB LTE Band5/26:≤12.541dBi
❒ NB LTE Band12/85:≤11.798dBi
❒ NB LTE Band13:≤12.214dBi
❒ BNLTE Band14:≤12.272 dBi
BG95_Hardware_Design 10 / 80
LPWA Module Series
❒NB LTE Band71:≤11.687 dBi
5. This module must not transmit simultaneously with any other antenna or transmitter
6. The host end product must include a user manual that clearly defines operating requirements and
conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is
required to satisfy the SAR requirements of FCC Part 2.1093
If the device is used for other equipment that separate approval is required for all other operating
configurations, including portable configurations with respect to 2.1093 and different antenna
configurations.
For this device, OEM integrators must be provided with labeling instructions of finished products.
Please refer to KDB784748 D01 v07, section 8. Page 6/7 last two paragraphs:
A certified modular has the option to use a permanently affixed label, or an electronic label. For a
permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2
Certification (labeling requirements) above). The OEM manual must provide clear instructions
explaining to the OEM the labeling requirements, options and OEM user manual instructions that are
required (see next paragraph).
For a host using a certified modular with a standard fixed label, if (1) the module’s FCC ID is not visible
when installed in the host, or (2) if the host is marketed so that end users do not have straightforward
commonly used methods for access to remove the module so that the FCC ID of the module is visible;
then an additional permanent label referring to the enclosed module:“Contains Transmitter Module
FCC ID: XMR201910BG96M3” or “Contains FCC ID: XMR201910BG96M3” must be used. The host
OEM user manual must also contain clear instructions on how end users can find and/or access the
module and the FCC ID.
BG95_Hardware_Design 11 / 80
LPWA Module Series
The final host / module combination may also need to be evaluated against the FCC Part 15B criteria
for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device.
The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the
user that changes or modifications not expressly approved by the party responsible for compliance
could void the user's authority to operate the equipment. In cases where the manual is provided only in
a form other than paper, such as on a computer disk or over the Internet, the information required by
this section may be included in the manual in that alternative form, provided the user can reasonably be
expected to have the capability to access information in that form.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) This device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the manufacturer could void the user’s authority to
operate the equipment.
BG95_Hardware_Design 12 / 80
LPWA Module Series
2 Product Concept
2.1. General Description
BG95 is a series of embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication
module. It provides data connectivity on LTE-FDD/GPRS/EGPRS networks, and supports half-duplex
operation in LTE networks. It also provides GNSS
application demands.
1)
and voice 2) functionality to meet customers’ specific
Table 1: Version Selection for BG95 Series Module
Version Cat M1 VoLTE
BG95-M1
BG95-M2*
BG95-M3*
BG95-N1*
BG95-M4 4)
BG95-M5 4)
BG95-MF 4)
Y Y N N N Y
Y Y Y N N Y
Y Y Y Y N Y
N N Y N N Y
Y Y Y N N Y
Y Y Y N N Y
Y Y Y N Y Y
Cat NB2
NB1
3)
/
GSM
Table 2: Frequency Bands and GNSS Types of BG95 Series Module
Wi-Fi
Positioning
GNSS
(Optional)
Module Supported Bands LTE Bands Power Class GNSS (Optional)
Cat M1 Only:
LTE-FDD:
BG95-M1
BG95_Hardware_Design 13 / 80
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26*/B27/
B28/B66/B85
Power Class 5 (20dBm)
GPS,
GLONASS, BeiDou,
Galileo
BG95-M2*
BG95-M3*
BG95-N1*
Cat M1:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26*/
B27/B28/B66/B85
Cat NB2:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26*/B28/B66/
B71/B85
Cat M1:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26*/B27/
B28/B66/B85
Cat NB2:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26*/
B28/B66/B71/B85
EGPRS:
850/900/1800/1900MHz
Cat NB2
Only:
LTE FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26*/
B28/B66/B71/B85
Power Class 5 (20dBm)
Power Class 5 (20dBm)
Power Class 5 (20dBm)
LPWA Module Series
GPS,
GLONASS, BeiDou,
Galileo
GPS,
GLONASS, BeiDou,
Galileo
GPS,
GLONASS, BeiDou,
Galileo
BG95-M4 4)
BG95-M5 4)
Cat M1:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26/B27/
B28/B31/B66/B72/B73/B85
Cat NB2:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26/B28/B31/
B66/B72/B73/B85
Cat M1:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26/B27/
B28/B66/B85
Cat NB2:
LTE-FDD:
Power Class 5 (20dBm)
Power Class 3 (23dBm)
GPS,
GLONASS, BeiDou,
Galileo
GPS,
GLONASS, BeiDou,
Galileo
BG95_Hardware_Design 14 / 80
BG95-MF 4)
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26/B28/B66/
B71/B85
Cat M1:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B14/B18/B19/B20/B25/B26/B27/
B28/B66/B85
Cat NB2:
LTE-FDD:
B1/B2/B3/B4/B5/B8/B12/B13/
B18/B19/B20/B25/B26/
B28/B66/B71/B85
Wi-Fi (For Positioning Only):
2.4GHz/5GHz
Power Class 5 (20dBm)
LPWA Module Series
GPS,
GLONASS, BeiDou,
Galileo
NOTES
1)
1.
GNSS function is optional.
2)
2.
BG95 series module supports VoLTE (Voice over LTE) under LTE Cat M1 and CS voice under
GSM.
3)
3.
LTE Cat NB2 is backward compatible with LTE Cat NB1.
4)
4.
BG95-M4/-M5/-MF are still under planning. Therefore, details of them are currently not included
and will be added in a future release of this document.
5. “*” means under development.
With a compact profile of 23.6mm × 19.9mm × 2.2mm, BG95 can meet almost all requirements for M2M
applications such as smart metering, tracking system, security, wireless POS, etc.
BG95 is an SMD type module which can be embedded into applications through its 102 LGA pads. It
supports internet service protocols like TCP, UDP and PPP. Extended AT commands have been
developed for customers to use these internet service protocols easily.
2.2. Key Features
The following table describes the detailed features of BG95 series modules.
BG95_Hardware_Design 15 / 80
Table 3: Key Features of BG95 Series Modules
Features Details
BG95-M1/-M2/-N1:
Supply voltage: 2.4V~4.8V
Power Supply
Typical supply voltage: 3.3V
BG95-M3:
Supply voltage: 3.3V~4.3V
Typical supply voltage: 3.8V
Class 5 (20dBm±2dB) for LTE-FDD bands
Class 4 (33dBm±2dB) for GSM850
Class 4 (33dBm±2dB) for EGSM900
Class 1 (30dBm±2dB) for DCS1800
Transmitting Power
Class 1 (30dBm±2dB) for PCS1900
Class E2 (27dBm±3dB) for GSM850 8-PSK
Class E2 (27dBm±3dB) for EGSM900 8-PSK
Class E2 (26dBm±3dB) for DCS1800 8-PSK
Class E2 (26dBm±3dB) for PCS1900 8-PSK
LPWA Module Series
LTE Features
GSM Features
Internet Protocol
Features*
Support LTE Cat M1 and LTE Cat NB2
Support 1.4MHz RF bandwidth for LTE Cat M1
Support 200KHz RF bandwidth for LTE Cat NB2
Support SISO in DL direction
Cat M1: Max. 589Kbps (DL)/1.12Mbps (UL)
Cat NB2: Max. 136Kbps (DL)/150Kbps (UL)
GPRS:
Support GPRS multi-slot class 33 (33 by default)
Coding scheme: CS-1, CS-2, CS-3 and CS-4
Max. 107Kbps (DL), Max. 85.6Kbps (UL)
EDGE:
Support EDGE multi-slot class 33 (33 by default)
Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
Downlink coding schemes: CS 1-4 and MCS 1-9
Uplink coding schemes: CS 1-4 and MCS 1-9
Max. 296Kbps (DL), Max. 236.8Kbps (UL)
Support PPP/TCP/UDP/SSL/TLS/FTP(S)/HTTP(S)/NITZ/PING/MQTT/
CoAP protocols
Support PAP (Password Authentication Protocol) and CHAP (Challenge
Handshake Authentication Protocol) protocols which are usually used for
PPP connections
Text and PDU mode
SMS
Point to point MO and MT
SMS cell broadcast
BG95_Hardware_Design 16 / 80
SMS storage: ME by default
(U)SIM Interface Support 1.8V USIM/SIM card
Audio Feature* Support one digital audio interface: PCM interface
Compliant with USB 2.0 specification (slave only)
Support operations at low-speed and full-speed
USB Interface
Used for AT command communication, data transmission, GNSS NMEA
output, software debugging and firmware upgrade
Support USB serial drivers for Windows 7/8/8.1/10, Linux 2.6/3.x (3.4 or
later)/4.1~4.15, Android 4.x/5.x/6.x/7.x/8.x/9.x
Main UART:
Used for data transmission and AT command communication
115200bps baud rate by default
The default frame format is 8N1 (8 data bits, no parity, 1 stop bit)
Support RTS and CTS hardware flow control
UART Interfaces
Debug UART:
Used for software debugging and log output
Support 115200bps baud rate
GNSS UART:
Used for GNSS data and NMEA sentences output
115200bps baud rate by default
LPWA Module Series
AT Commands
3GPP TS 27.007 and 3GPP TS 27.005 AT commands, as well as Quectel
enhanced AT commands
Network Indication One NETLIGHT pin for network connectivity status indication
Antenna Interfaces
Physical Characteristics
Temperature Range
Including main antenna (ANT_MAIN) and GNSS antenna (ANT_GNSS)
interfaces
Size: (23.6±0.15)mm × (19.9±0.15)mm × (2.2±0.2)mm
Weight: approx. 2.15g
1)
2)
Operation temperature range: -35°C ~ +75°C
Extended temperature range: -40°C ~ +85°C
Storage temperature range: -40°C ~ +90°C
Firmware Upgrade USB interface, DFOTA*
RoHS All hardware components are fully compliant with EU RoHS directive
NOTES
1. “*” means under development.
1)
2.
Within operation temperature range, the module is 3GPP compliant.
2)
3.
Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
BG95_Hardware_Design 17 / 80
LPWA Module Series
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like
P
might reduce in their value and exceed the specified tolerances. When the temperature returns to
out
the normal operating temperature levels, the module will meet 3GPP specifications again.
2.3. Functional Diagram
The following figure shows a block diagram of BG95 and illustrates the major functional parts.
Power management
Baseband
Radio frequency
Peripheral interfaces
VBAT_RF
VBAT_BB
PWRKEY
RESET_N
PMIC
PA
(GSM)
Control
Tx
ANT_MAIN
(ASM)
Rx
Transceiver/PA/switch
IQ Control
ANT_GNSS
SAW
LNA
GNSS
Baseband
ADC1
ADC0
VDD_EXT
19.2 M XO
USB
eSIM
(U)SIM PCM*
UARTs
I2C*
GPIOs
STATUS NETLIGHT
Figure 1: Functional Diagram
BG95_Hardware_Design 18 / 80
LPWA Module Series
NOTES
1. eSIM function is optional. If eSIM is selected, then the external (U)SIM cannot be used
simultaneously.
2. RESET_N will be supported in the next hardware design version.
3. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a
time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next
hardware design version.
4. “*” means under development.
2.4. Evaluation Board
In order to help customers to develop applications conveniently with BG95, Quectel supplies the
evaluation board (EVB), USB to RS-232 converter cable, USB data cable, earphone, antenna and other
peripherals to control or test the module. For more details, please refer to document [1].
BG95_Hardware_Design 19 / 80
LPWA Module Series
3 Application Interfaces
BG95 is equipped with 102 LGA pads that can be connected to customers’ cellular application platforms.
The following sub-chapters will provide detailed description of interfaces listed below:
Power supply
(U)SIM interface
USB interface
UART interfaces
PCM* and I2C* interfaces
Status indication
USB_BOOT interface
ADC interfaces
GPIO interfaces
NOTE
“*” means under development.
BG95_Hardware_Design 20 / 80
3.1. Pin Assignment
The following figure shows the pin assignment of BG95.
LPWA Module Series
PS M_I ND*
ADC 1
GND
PCM _C LK*
PCM _SY NC*
PCM _I N*
PCM _OU T*
USB_VBUS
USB_DP
USB_DM
RESERVED
RESERVED
RESERVED
RESERVED
PW RKEY
GPIO 16
RESET_N
W_DI SA BLE# *
GND
62
GND
61
ANT _M AIN
60
GND
59
GND
RESERVED
58
RESERVED
56
GND
55
GND
54
1
1)
2
82 81
80 79
3
4
5
6
7
GPIO 64
63
64
102 101
83
84
100
99
8
GPIO 65
9
85
65
65
10
GPIO 66
11
12
13
86
66
67
87
68
88
14
2)
15
16
3)
17
89 90
69
91 92
71
70
72
18
RESERVED
VB AT_ RF
VB AT_ RF
53
98
97
96
95
94
93
52
51
78
77
76
USB_BOOT
75
74
73
GND
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
ANT _G NSS
GND
USIM_GND
USIM_CLK
USIM_DATA
USIM_RST
USIM_VDD
USIM_PRESENCE*
I2C_SDA*
I2C_SCL*
RI
DCD
RTS
CTS
TXD
RXD
VB AT_ BB
VB AT_ BB
19
AP _R EAD Y*
PO WER USB UART
20
ST ATU S
NETLIGHT
21
22
DBG_RXD
(U)SIM
23
DBG_TXD
24 57
1)
ADC 0
PCM
25
GPIO 25
26
30
DTR
GPIO 26
GNSS _UART_T XD
GN SS_U ART _R XD
ANT
GND
VDD _EX T
GND
RESERVED
OTHE RS
31
29
28
27
Figure 2: Pin Assignment (Top View)
BG95_Hardware_Design 21 / 80
LPWA Module Series
NOTES
1)
1.
ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface
at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the
next hardware design version.
2)
2.
PWRKEY output voltage is 1.5V because of the diode drop in the Qualcomm chipset. PWRKEY
should never be pulled down to GND permanently.
3. 3) RESET_N will be supported in the next hardware design version.
4. Keep all RESERVED pins and unused pins unconnected.
5. GND pins should be connected to ground in the design.
6. “*” means under development.
3.2. Pin Description
The following tables show the pin definition and description of BG95.
Table 4: Definition of I/O Parameters
Type Description
AI Analog Input
AO Analog Output
DI Digital Input
DO Digital Output
IO Bidirectional
OD Open Drain
PI Power Input
PO Power Output
BG95_Hardware_Design 22 / 80
LPWA Module Series
Table 5: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
BG95-M1/-M2/-N1:
Vmax=4.8V
Vmin=2.4V
Power supply
VBAT_BB 32, 33 PI
for the module’s
baseband part
Vnorm=3.3V
BG95-M3:
Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V
BG95-M1/-M2/-N1:
Vmax=4.8V
Vmin=2.4V
Power supply
VBAT_RF 52, 53 PI
for the module’s
RF part
Vnorm=3.3V
BG95-M3:
Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V
1.8V output
VDD_EXT 29 PO
power supply
for external
circuit
Vnorm=1.8V
I
max=50mA
O
Power supply for
external GPIO’s
pull-up circuits.
If unused, keep this
pin open.
3, 31, 48,
50, 54, 55,
58, 59, 61,
GND
62, 67~74,
Ground
79~82,
89~91,
100~102
Turn on/off
Pin Name Pin No. I/O Description DC Characteristics Comment
The output voltage is
1.5V because of the
diode drop in the
Qualcomm chipset.
PWRKEY 1) 15 DI
Turn on/off the
module
Vnorm=1.5V
V
max=0.45V
IL
PWRKEY should
BG95_Hardware_Design 23 / 80
LPWA Module Series
never be pulled down
to GND permanently.
Reset
Pin Name Pin No. I/O Description DC Characteristics Comment
RESET_N will be
RESET_N 2) 17 DI
Reset the
module
V
max=0.45V
IL
supported in the next
hardware design
version.
Status Indication
Pin Name Pin No. I/O Description DC Characteristics Comment
Indicate the
STATUS 20 DO
module’s
operation
status
Indicate the
NETLIGHT 21 DO
module’s
network activity
status
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
USB Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
Vmax=5.25V
USB_VBUS 8 PI USB detection
Vmin=3.0V
Vnorm=5.0V
USB_DP 9 IO
USB differential
data bus (+)
Compliant with USB
2.0 standard
specification.
USB_DM 10 IO
USB differential
data bus (-)
Require differential
impedance of 90Ω.
(U)SIM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
V
min=-0.3V
USIM_
PRESENCE*
42 DI
USIM_VDD 43 PO
(U)SIM card
insertion
detection
Power supply
for (U)SIM card
USIM_RST 44 DO Reset signal of V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
Vmax=1.9V
Vmin=1.7V
max=0.45V
OL
1.8V power domain.
If unused, keep this
pin open.
Only 1.8V (U)SIM
card is supported.
BG95_Hardware_Design 24 / 80
LPWA Module Series
(U)SIM card VOHmin=1.35V
V
min=-0.3V
IL
V
max=0.6V
IL
USIM_DATA 45 IO
USIM_CLK 46 DO
Data signal of
(U)SIM card
Clock signal of
(U)SIM card
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
Specified
USIM_GND 47
ground for
(U)SIM card
Main UART Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
V
min=-0.3V
Data terminal
DTR 30 DI
ready (sleep
mode control)
RXD 34 DI Receive data
TXD 35 DO Transmit data
CTS 36 DO Clear to send
RTS 37 DI
DCD 38 DO
Request to
send
Data carrier
detection
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
RI 39 DO
Ring indication
signal
V
max=0.45V
OL
V
min=1.35V
OH
Debug UART Interface
BG95_Hardware_Design 25 / 80
LPWA Module Series
Pin Name Pin No. I/O Description DC Characteristics Comment
V
min=-0.3V
DBG_RXD 22 DI Receive data
V
V
V
DBG_TXD 23 DO Transmit data
V
V
IL
max=0.6V
IL
min=1.2V
IH
max=2.0V
IH
max=0.45V
OL
min=1.35V
OH
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
GNSS UART Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
GNSS_UART_
TXD
GNSS_UART_
RXD
V
max=0.45V
27 DO Transmit data
28 DI Receive data
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
PCM Interface*
Pin Name Pin No. I/O Description DC Characteristics Comment
PCM_CLK* 4 DO
PCM clock
output
PCM frame
PCM_SYNC* 5 DO
synchronization
output
PCM_IN* 6 DI PCM data input
PCM_OUT* 7 DO
PCM data
output
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain. If unused, keep this
pin open.
1.8V power domain. If unused, keep this pin open.
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
I2C Interface*
Pin Name Pin No. I/O Description DC Characteristics Comment
I2C serial clock.
I2C_SCL* 40 OD
Used for
external codec.
External pull-up
resistor is required.
1.8V only.
If unused, keep this
BG95_Hardware_Design 26 / 80
LPWA Module Series
pin open.
External pull-up
I2C serial data.
I2C_SDA* 41 OD
Used for
external codec.
resistor is required.
1.8V only.
If unused, keep this
pin open.
Antenna Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
ANT_MAIN 60 IO
ANT_GNSS 49 AI
Main antenna
interface
GNSS antenna
interface
GPIO Interfaces
Pin Name Pin No. I/O Description DC Characteristics
V
max=0.45V
OL
V
min=1.35V
General-
GPIO16 16 IO
purpose input/
output interface
General-
GPIO25 25 IO
purpose input/
output interface
General-
GPIO26 26 IO
purpose input/
output interface
General-
GPIO64 64 IO
purpose input/
output interface
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
50Ω impedance
50Ω impedance.
If unused, keep this
pin open.
Comment
1.8V power domain. If unused, keep this pin open.
1.8V power domain. If unused, keep this pin open.
1.8V power domain. If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
BG95_Hardware_Design 27 / 80
LPWA Module Series
V
max=0.45V
OL
General-
GPIO65 65 DO
purpose input/
output interface
General-
GPIO66 66 DO
purpose input/
output interface
VOHmin=1.35V
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
ADC Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
General
purpose analog
ADC0 3) 24 AI
to digital
converter
interface
Voltage range:
0.3V to 1.8V
ADC0 and ADC1
cannot be used
simultaneously.
BG95 supports using
of only one ADC
interface at a time:
either ADC0 or
General
purpose analog
ADC1 3) 2 AI
to digital
converter
interface
Voltage range:
0.3V to 1.8V
ADC1. Currently only
ADC0 is enabled,
and ADC1 will be
enabled in the next
hardware design
version
Other Interface Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
If unused, keep this
pin open.
PSM_IND* 4) 1 DO
Power saving
mode indicator
V
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
Pulled up by default.
When it is in low
voltage level, the
module can enter
into airplane mode.
W_DISABLE#* 18 DI
Airplane mode
control
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
If unused, keep this
pin open.
BG95_Hardware_Design 28 / 80
LPWA Module Series
V
min=-0.3V
IL
VILmax=0.6V
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep this
pin open.
1.8V power domain.
If unused, keep this
pin open.
AP_READY* 19 DI
USB_BOOT 75 DI
Application
processor sleep
state detection
Force the
module to enter
into emergency
download mode
RESERVED Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
11~14, 51,
RESERVED
56, 57, 63,
76~78,
83~88,
Reserved
Keep these pins
open.
92~99
NOTES
1)
1.
The output voltage of PWRKEY is 1.5V because of the diode drop in the Qualcomm chipset, and
PWRKEY should never be pulled down to GND permanently.
2)
2.
RESET_N will be supported in the next hardware design version.
3)
3.
ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at
a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next
hardware design version.
4)
4.
When PSM is enabled, the function of PSM_IND* pin will be activated after the module is rebooted.
When PSM_IND* is in high voltage level, the module is in normal operation state, when it is in low
voltage level, the module is in PSM.
5. Keep all RESERVED pins and unused pins unconnected.
6. “*” means under development.
3.3. Operating Modes
The table below briefly summarizes the various operating modes of BG95.
BG95_Hardware_Design 29 / 80
Table 6: Overview of Operating Modes
Mode Details
LPWA Module Series
Normal
Operation
Extended Idle
Mode DRX
(e-I-DRX)
Airplane Mode
Minimum
Functionality
Mode
Sleep Mode*
Power Saving
Mode
(PSM)
Connected
Idle
Network has been connected. In this mode, the power consumption
may vary with the network setting and data transfer rate.
Software is active. The module remains registered on network, and it
is ready to send and receive data.
BG95 module and the network may negotiate over non-access stratum signaling the
use of e-I-DRX for reducing power consumption, while being available for mobile
terminating data and/or network originated procedures within a certain delay
dependent on the DRX cycle value. AT+CFUN=4 or W_DISABLE#* pin can set the module into airplane mode. In this
case, RF function will be invalid.
AT+CFUN=0 can set the module into a minimum functionality mode without removing
the power supply. In this case, both RF function and (U)SIM card will be invalid.
In this mode, the current consumption of the module will be reduced to a lower level.
During this mode, the module can still receive paging message, SMS and TCP/UDP
data from the network normally.
BG95 module may enter into Power Saving Mode to further reduce its power
consumption. PSM is similar to power-off, but the module remains registered on the
network and there is no need to re-attach or re-establish PDN connections.
Power OFF
Mode
In this mode, the power management unit shuts down the power supply. Software is
not active. The serial interfaces are not accessible. But the operating voltage
(connected to VBAT_RF and VBAT_BB) remains applied.
NOTES
1. During e-I-DRX, it is recommended to use UART interface for data communication, as the use of USB
interface will increase power consumption.
2. “*” means under development.
3.4. Power Saving
3.4.1. Airplane Mode
When the module enters into airplane mode, the RF function does not work, and all AT commands
correlative with RF function will be inaccessible. This mode can be set via the following ways.
BG95_Hardware_Design 30 / 80
LPWA Module Series
Hardware:
W_DISABLE#* is pulled up by default. Driving it to low level will let the module enter into airplane mode.
Software: AT+CFUN=<fun> provides choice of the functionality level, through setting <fun> into 0, 1 or 4.
AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.  AT+CFUN=1: Full functionality mode (by default).  AT+CFUN=4: Airplane mode. RF function is disabled.
NOTES
1. Airplane mode control via W_DISABLE#* is disabled in firmware by default. It can be enabled by
AT+QCFG="airplanecontrol" command which is still under development. Details about the command will be provided in document [2].
2. The execution of AT+CFUN command will not affect GNSS function.
3. “*” means under development.
3.4.2. Power Saving Mode (PSM)
BG95 module can enter into PSM for reducing its power consumption. The mode is similar to power-off,
but the module remains registered on the network and there is no need to re-attach or re-establish PDN
connections. So BG95 in PSM cannot immediately respond users’ requests.
When the module wants to use the PSM it shall request an Active Time value during every Attach and
TAU procedures. If the network supports PSM and accepts that the module uses PSM, the network
confirms usage of PSM by allocating an Active Time value to the module. If the module wants to change
the Active Time value, e.g. when the conditions are changed in the module, the module consequently
requests the value it wants in the TAU procedure.
If PSM is supported by the network, then it can be enabled via AT+CPSMS command.
Either of the following methods will wake up the module from PSM:
Drive PWRKEY pin to low level will wake up the module.
When the T3412_Ext timer expires, the module will be woken up automatically.
The Main UART data will wake up the module and the function is under development.
NOTE
Please refer to document [2] for details about AT+CPSMS command.
BG95_Hardware_Design 31 / 80
LPWA Module Series
3.4.3. Extended Idle Mode DRX (e-I-DRX)
The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX
for reducing its power consumption, while being available for mobile terminating data and/or network
originated procedures within a certain delay dependent on the DRX cycle value.
Applications that want to use e-I-DRX need to consider specific handling of mobile terminating services or
data transfers, and in particular they need to consider the delay tolerance of mobile terminated data.
In order to negotiate the use of e-I-DRX, the UE requests e-I-DRX parameters during attach procedure
and RAU/TAU procedure. The EPC may reject or accept the UE request for enabling e-I-DRX. In case the
EPC accepts e-I-DRX, the EPC based on operator policies and, if available, the e-I-DRX cycle length
value in the subscription data from the HSS, may also provide different values of the e-I-DRX parameters
than what was requested by the UE. If the EPC accepts the use of e-I-DRX, the UE applies e-I-DRX
based on the received e-I-DRX parameters. If the UE does not receive e-I-DRX parameters in the
relevant accept message because the EPC rejected its request or because the request was received by
EPC not supporting e-I-DRX, the UE shall apply its regular discontinuous reception.
If e-I-DRX is supported by the network, then it can be enabled by AT+CEDRXS=1 command.
NOTE
Please refer to document [2] for details about AT+CEDRXS command.
3.4.4. Sleep Mode*
BG95 is able to reduce its current consumption to a lower value during the sleep mode. The following
sub-chapters describe the power saving procedure of BG95 module.
3.4.4.1. UART Application
If the host communicates with module via UART interface, the following preconditions can let the module
enter into sleep mode.
Execute AT+QSCLK=1 command to enable sleep mode.
Drive DTR to high level.
The following figure shows the connection between the module and the host.
BG95_Hardware_Design 32 / 80
LPWA Module Series
Figure 3: Sleep Mode Application via UART
When BG95 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for
details about RI behavior.
Driving the host DTR to low level will wake up the module.
AP_READY* will detect the sleep state of the host (can be configured to high level or low level
detection). Please refer to AT+QCFG="apready" command in document [2] for details.
NOTE
“*” means under development.
3.5. Power Supply
3.5.1. Power Supply Pins
BG95 provides the following four VBAT pins for connection with an external power supply. There are two
separate voltage domains for VBAT.
Two VBAT_RF pins for module’s RF part.
Two VBAT_BB pins for module’s baseband part.
The following table shows the details of VBAT pins and ground pins.
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LPWA Module Series
Table 7: VBAT and GND Pins
Pin Name Pin No. Description Module Min. Typ. Max. Unit
BG95-M1/-M2/-N1 2.4 3.3 4.8 V
BG95-M3 3.3 3.8 4.3 V
BG95-M1/-M2/-N1 2.4 3.3 4.8 V
BG95-M3 3.3 3.8 4.3 V
VBAT_RF 52, 53
VBAT_BB 32, 33
Power supply for the
module’s RF part
Power supply for the
module’s baseband
part
3, 31, 48, 50,
54, 55, 58,
59, 61, 62,
GND
67~74,
Ground - - - -
79~82,
89~91,
100~102
3.5.2. Decrease Voltage Drop
BG95-M1/-M2/-N1: The power supply range of BG95-M1/-M2/-N1 is from 2.4V to 4.8V. Please make
sure that the input voltage will never drop below 2.4V.
BG95-M3: The power supply range of the BG95-M3 is from 3.3V to 4.3V. Please make sure that the
input voltage will never drop below 3.3V.
The following figure shows the voltage drop during burst transmission in 2G network of BG95-M3 module.
The voltage drop will be less in LTE Cat M1 and/or LTE Cat NB2 networks.
Burst
Transmission
VB AT
Drop
Min.3.3V
Burst
Transmission
Ripple
Figure 4: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a
multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is
recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and
place these capacitors close to VBAT pins. The main power supply from an external application has to be
BG95_Hardware_Design 34 / 80
LPWA Module Series
a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB
trace should be no less than 0.5mm, and the width of VBAT_RF trace should be no less than 2mm. In
principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to get a stable power source, it is suggested to use a TVS with low leakage current
and suitable reverse stand-off voltage, and also it is recommended to place it as close to the VBAT pins as
possible. The following figure shows the star structure of the power supply.
VB AT
D1
TVS
C1
100uF
+
C2
100nF
33pF
C3
C4
10pF
C5
100uF
+
C6 C7 C8
100nF
33pF
VB AT_ RF
VB AT_ BB
10pF
Module
Figure 5: Star Structure of the Power Supply
3.5.3. Monitor the Power Supply
AT+CBC* command can be used to monitor the VBAT_BB voltage value. For more details, please refer
to document [2].
NOTE
“*” means under development.
3.6. Turn on and off Scenarios
3.6.1. Turn on Module Using the PWRKEY Pin
The following table shows the pin definition of PWRKEY.
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LPWA Module Series
Table 8: Pin Definition of PWRKEY
Pin Name Pin No. Description DC Characteristics Comment
The output voltage is
PWRKEY 15 Turn on/off the module
Vnorm=1.5V
V
max=0.45V
IL
1.5V because of the
diode drop in the
Qualcomm chipset.
When BG95 is in power off mode, it can be turned on to normal mode by driving the PWRKEY pin to a low
level for a duration between 500ms and 1000ms. It is recommended to use an open drain/collector driver
to control the PWRKEY. A simple reference circuit is illustrated in the following figure.
PWRKEY
500ms~10 00ms
4.7K
Turn on pulse
10nF
47K
Figure 6: Turn on the Module Using Driving Circuit
Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike
may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
Figure 7: Turn on the Module Using Keystroke
The turn on scenario is illustrated in the following figure.
BG95_Hardware_Design 36 / 80
LPWA Module Series
NOTE
VBAT
PWRKEY
RESET _N
STATUS (DO)
USB
UART
50 0m s~10 00 m s
VIL≤0.45V
Inactive
Inactive
TBD
Typ. 2s
Act ive
Typ. 2s
Act ive
Figure 8: Timing of Turning on Module
NOTES
1. Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less
than 30ms.
2. PWRKEY is internally pulled up to an internal voltage in the Qualcomm chipset, and its output voltage
is the internal voltage minus a diode drop in the chipset. Therefore, the expected output voltage of
PWRKEY is 1.5V.
3. PWRKEY should never be pulled down to GND permanently.
3.6.2. Turn off Module
Either of the following methods can be used to turn off the module:
Normal power down procedure: Turn off the module using the PWRKEY pin.
Normal power down procedure: Turn off the module using AT+QPOWD command.
3.6.2.1. Turn off Module Using the PWRKEY Pin
Driving the PWRKEY pin to a low level voltage for a duration between 650ms and 1500ms, the module
will execute power-down procedure after the PWRKEY is released.
BG95_Hardware_Design 37 / 80
The power-down scenario is illustrated in the following figure.
VBA T
LPWA Module Series
PWRKEY
STATUS
Module Status
650ms~150 0ms
≤0.45V
V
IL
RUNNING
TBD
Power-down procedure
OFF
Figure 9: Timing of Turning off Module
3.6.2.2. Turn off Module Using AT Command
It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the
module via PWRKEY pin.
Please refer to document [2] for details about AT+QPOWD
command.
3.7. Reset the Module
RESET_N is used to reset the module and will be supported in the next hardware design version. The
module can be reset by driving RESET_N to a low level voltage for a duration between 2s and 3.8s.
Table 9: Pin Definition of RESET_N
Pin Name Pin No. Description DC Characteristics Comment
RESET_N will be supported in
RESET_N 17 Reset the module VILmax=0.45V
The reset scenario is illustrated in the following figure.
the next hardware design
version.
BG95_Hardware_Design 38 / 80
LPWA Module Series
VBA T
RESET_N
Module Status
≥2s
Running
≤3.8s
VIL≤0.45V
Rese tting
Restart
Figure 10: Timing of Reset Module
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N pin.
RESET_N
2s~3.8s
4.7K
Reset pulse
47K
Figure 11: Reference Circuit of RESET_N by Using Driving Circuit
S2
RESET_N
TVS
Close to S2
Figure 12: Reference Circuit of RESET_N by Using Button
BG95_Hardware_Design 39 / 80
LPWA Module Series
NOTE
Please assure that there is no large capacitance on RESET_N pin.
3.8. (U)SIM Interface
The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. BG95 supports 1.8V (U)SIM card
only.
Table 10: Pin Definition of (U)SIM Interface
Pin Name Pin No. I/O Description Comment
USIM_
PRESENCE*
USIM_VDD 43 PO Power supply for (U)SIM card
42 DI (U)SIM card insertion detection
Only 1.8V (U)SIM card is
supported.
USIM_RST 44 DO Reset signal of (U)SIM card
USIM_DATA 45 IO Data signal of (U)SIM card
USIM_CLK 46 DO Clock signal of (U)SIM card
USIM_GND 47 Specified ground for (U)SIM card
BG95 supports (U)SIM card hot-plug via the USIM_PRESENCE* pin. The function supports low level and
high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET*
command for details.
The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.
BG95_Hardware_Design 40 / 80
LPWA Module Series
Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector
If (U)SIM card detection function is not needed, please keep USIM_PRESENCE* unconnected. A
reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following
figure.
Figure 14: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector
In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the
criteria below in (U)SIM circuit design:
Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace
length as less than 200mm as possible.
Keep (U)SIM card signals away from RF and VBAT traces.
BG95_Hardware_Design 41 / 80
LPWA Module Series
Assure the ground between the module and the (U)SIM card connector short and wide. Keep the
trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.
Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as
close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can
be connected to the system ground directly.
To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground. USIM_RST should also be ground shielded.
In order to offer good ESD protection, it is recommended to add a TVS diode array with parasitic
capacitance not exceeding 15pF. In order to facilitate debugging, it is recommended to reserve
series resistors for the (U)SIM signals of the module. The 33pF capacitors are used for filtering
interference of GSM 900MHz. Please note that the (U)SIM peripheral circuit should be close to the
(U)SIM card connector.
The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.
NOTE
“*” means under development.
3.9. USB Interface
BG95 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0
specification and supports low-speed (1.5Mbps) and full-speed (12Mbps) modes. The USB interface is
used for AT command communication, data transmission, software debugging and firmware upgrade.
The following table shows the pin definition of USB interface.
Table 11: Pin Definition of USB Interface
Pin Name Pin No. I/O Description Comment
USB_VBUS 8 PI USB connection detection Typically 5.0V
USB_DP 9 IO USB differential data bus (+)
USB_DM 10 IO USB differential data bus (-)
Require differential impedance of
90Ω
GND 3 Ground
For more details about USB 2.0 specification, please visit http://www.usb.org/home
.
BG95_Hardware_Design 42 / 80
LPWA Module Series
The USB interface is recommended to be reserved for firmware upgrade in customers’ designs. The
following figure shows a reference circuit of USB interface.
Figure 15: Reference Circuit of USB Interface
A common mode choke L1 is recommended to be added in series between the module and customer’s
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 2pF.
Keep the ESD protection components as close to the USB connector as possible.
NOTE
BG95 module can only be used as a slave device.
BG95_Hardware_Design 43 / 80
LPWA Module Series
3.10. UART Interfaces
The module provides three UART interfaces: Main UART, Debug UART and GNSS UART interfaces.
Features of them are illustrated below:
The Main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,
230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. It is used for data
transmission and AT command communication, and supports RTS and CTS hardware flow control.
The default frame format is 8N1 (8 data bits, no parity, 1 stop bit).
The Debug UART interface supports a fixed baud rate of 115200bps, and is used for software
debugging and log output.
The GNSS UART interface supports 115200bps baud rate by default, and is used for GNSS data and
NMEA sentences output.
The following tables show the pin definition of the three UART interfaces.
Table 12: Pin Definition of Main UART Interface
Pin Name Pin No. I/O Description Comment
DTR 30 DI
RXD 34 DI Receive data 1.8V power domain
TXD 35 DO Transmit data 1.8V power domain
CTS 36 DO Clear to send 1.8V power domain
RTS 37 DI Request to send 1.8V power domain
DCD 38 DO Data carrier detection 1.8V power domain
RI 39 DO Ring indication signal 1.8V power domain
Data terminal ready.
Sleep mode control
1.8V power domain
NOTE
AT+IPR command can be used to set the baud rate of the Main UART interface, and AT+IFC command
can be used to set the hardware flow control (hardware flow control is disabled by default). Please refer to
document [2] for more details about these AT commands.
BG95_Hardware_Design 44 / 80
LPWA Module Series
Table 13: Pin Definition of Debug UART Interface
Pin Name Pin No. I/O Description Comment
DBG_RXD 22 DI Receive data 1.8V power domain
DBG_TXD 23 DO Transmit data 1.8V power domain
Table 14: Pin Definition of GNSS UART Interface
Pin Name Pin No. I/O Description Comment
GNSS_UART_TXD 27 DO Transmit data 1.8V power domain
GNSS_UART_RXD 28 DI Receive data 1.8V power domain
The logic levels of UART interfaces are described in the following table.
Table 15: Logic Levels of Digital I/O
Parameter Min. Max. Unit
VIL -0.3 0.6 V
VIH 1.2 2.0 V
VOL 0 0.45 V
VOH 1.35 1.8 V
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design of the Main UART interface:
BG95_Hardware_Design 45 / 80
LPWA Module Series
VDD_EXT
RI
DCD
CTS
RTS
DTR
TXD
RXD
0.1uF
120K
51K
VCCA VCCB
10K
OE
A1
A2
Translator
A3
A4
A5
A6
A7
A8
GND
B1
B2
B3
B4
B5
B6
B7
B8
0.1uF
51K
VDD_MCU
RI_MCU
DCD_MCU
CTS_MCU
RTS_MCU
DTR_MCU
TXD_MCU
RXD_MCU
Figure 16: Reference Circuit with Translator Chip
Please visit http://www.ti.com
for more information.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to that of solid line section, in terms of both module input and output circuit designs, but
please pay attention to the direction of connection.
Figure 17: Reference Circuit with Transistor Circuit
NOTE
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
BG95_Hardware_Design 46 / 80
LPWA Module Series
3.11. PCM* and I2C* Interfaces
BG95 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following
table shows the pin definition of the two interfaces which can be applied on audio codec design.
Table 16: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No. I/O Description Comment
PCM_CLK* 4 DO PCM clock output 1.8V power domain
PCM_SYNC* 5 DO
PCM frame synchronization
output
1.8V power domain
PCM_IN* 6 DI PCM data input 1.8V power domain
PCM_OUT* 7 DO PCM data output 1.8V power domain
I2C_SCL* 40 OD I2C serial clock Require external pull-up to 1.8V
I2C_SDA* 41 OD I2C serial data Require external pull-up to 1.8V
The following figure shows a reference design of PCM and I2C interfaces with an external codec IC.
Figure 18: Reference Circuit of PCM Application with Audio Codec
NOTE
“*” means under development.
BG95_Hardware_Design 47 / 80
LPWA Module Series
3.12. Network Status Indication
BG95 provides one network status indication pin: NETLIGHT. The pin is used to drive a network status
indication LED. The following tables describe the pin definition and logic level changes of NETLIGHT in
different network activity status.
Table 17: Pin Definition of
NETLIGHT
Pin Name Pin No. I/O Description Comment
NETLIGHT 21 DO
Indicate the module’s network activity
status
1.8V power domain
Table 18: Working State of
NETLIGHT
Pin Name Logic Level Changes Network Status
Flicker slowly (200ms High/1800ms Low) Network searching
Flicker slowly (1800ms High/200ms Low) Idle
NETLIGHT
Flicker quickly (125ms High/125ms Low) Data transfer is ongoing
Always high Voice calling
A reference circuit is shown in the following figure.
Figure 19: Reference Circuit of the Network Status Indicator
BG95_Hardware_Design 48 / 80
LPWA Module Series
3.13. STATUS
The STATUS pin is used to indicate the operation status of BG95 module. It will output high level when
the module is powered on.
The following table describes the pin definition of STATUS.
Table 19: Pin Definition of STATUS
Pin Name Pin No. I/O Description Comment
STATUS 20 DO Indicate the module’s operation status 1.8V power domain
The following figure shows a reference circuit of STATUS.
Figure 20: Reference Circuit of STATUS
3.14. Behaviors of RI*
AT+QCFG="risignaltype","physical" command can be used to configure RI behavior.
No matter on which port URC is presented, URC will trigger the behavior of RI pin.
The default behaviors of RI are shown as below.
BG95_Hardware_Design 49 / 80
LPWA Module Series
Table 20: Default Behaviors of RI
State Response
Idle RI keeps in high level.
URC RI outputs 120ms low pulse when new URC returns.
The default RI behaviors can be configured flexibly by AT+QCFG=“urc/ri/ring” command. For more details about AT+QCFG*, please refer to document [2].
NOTES
1. URC can be outputted from UART port, USB AT port and USB modem port, through configuration via
AT+QURCCFG command. The default port is USB AT port.
2. “*” means under development.
3.15. USB_BOOT Interface
BG95 provides a USB_BOOT pin. During development or factory production, USB_BOOT can force the
module to boot from USB port for firmware upgrade.
Table 21: Pin Definition of USB_BOOT Interface
Pin Name Pin No. I/O Description Comment
USB_BOOT 75 DI
Force the module to enter into
emergency download mode
The following figure shows a reference circuit of USB_BOOT interface.
1.8V power domain.
Active high.
If unused, keep it open.
BG95_Hardware_Design 50 / 80
LPWA Module Series
Figure 21: Reference Circuit of USB_BOOT Interface
NOTE
It is recommended to reserve the above circuit design during application design.
3.16. ADC Interfaces
The module provides two analog-to-digital converter (ADC) interfaces but only one ADC interface can be
used for each time. AT+QADC=0 command can be used to read the voltage value on the ADC being used. For more details about the AT command, please refer to document [2].
In order to improve the accuracy of ADC voltage values, the trace of ADC should be surrounded by
ground.
Table 22: Pin Definition of ADC Interface
Pin Name Pin No. Description
ADC0 24
ADC0 and ADC1 cannot be used simultaneously. Currently only
ADC0 is enabled, and ADC1 will be enabled in the next hardware
ADC1 2
design version.
The following table describes the characteristics of ADC interfaces.
BG95_Hardware_Design 51 / 80
LPWA Module Series
Table 23: Characteristics of ADC Interfaces
Parameter Min. Typ. Max. Unit
ADC0/ADC1 Voltage Range 0.3 1.8 V
ADC0/ADC1 Resolution 64.979 uV
ADC0/ADC1 Sampling Rate 4.8 MHz
NOTES
1. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at
a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next
hardware design version.
2. ADC input voltage must not exceed 1.8V.
3. It is prohibited to supply any voltage to ADC pin when VBAT is removed.
4. It is recommended to use resistor divider circuit for ADC application, and the divider resistor accuracy
should be no less than 1%.
3.17. GPIO Interfaces
The module provides six general-purpose input and output (GPIO) interfaces. AT+QCFG=
command can be used to configure corresponding GPIO pin’s status. For more details about the AT
command, please refer to document [2].
Table 24: Pin Definition of GPIO Interfaces
Pin Name Pin No. Description
GPIO16 16 General-purpose input and output interface
GPIO25 25 General-purpose input and output interface
GPIO26 26 General purpose input and output interface
"gpio"*
GPIO64 64 General purpose input and output interface
GPIO65 65 General purpose input and output interface
GPIO66 66 General purpose input and output interface
BG95_Hardware_Design 52 / 80
The following table describes the characteristics of GPIO interfaces.
LPWA Module Series
Table 25: Logic Levels of GPIO Interfaces
Parameter Min. Max. Unit
VIL -0.3 0.6 V
VIH 1.2 2.0 V
VOL 0 0.45 V
VOH 1.35 1.8 V
NOTE
“*” means under development.
BG95_Hardware_Design 53 / 80
LPWA Module Series
4 GNSS Receiver
4.1. General Description
BG95 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of
Qualcomm (GPS, GLONASS, BeiDou and Galileo).
BG95 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via
USB interface by default.
By default, BG95 GNSS engine is switched off. It has to be switched on via AT command. For more
details about GNSS engine technology and configurations, please refer to document [3].
4.2. GNSS Performance
The following table shows the GNSS performance of BG95.
Table 26: GNSS Performance
Parameter Description Conditions Typ. Unit
Cold start Autonomous TBD dBm
Sensitivity
(GNSS)
TTFF
(GNSS)
Reacquisition Autonomous TBD dBm
Tracking Autonomous TBD dBm
Cold start
@open sky
Warm start
@open sky
Autonomous TBD s
XTRA enabled TBD s
Autonomous TBD s
XTRA enabled TBD s
BG95_Hardware_Design 54 / 80
LPWA Module Series
Autonomous TBD s
XTRA enabled TBD s
Autonomous
@open sky
TBD m
Accuracy
(GNSS)
Hot start
@open sky
CEP-50
NOTES
1. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep
on positioning for 3 minutes.
2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can
fix position again within 3 minutes after loss of lock.
3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes
position within 3 minutes after executing cold start command.
4.3. Layout Guidelines
The following layout guidelines should be taken into account in customers designs.
Maximize the distance between GNSS antenna and main antenna.
Digital circuits such as (U)SIM card, USB interface, camera module, display connector and SD card
should be kept away from the antennas.
Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar
isolation and protection.
Keep 50Ω characteristic impedance for the ANT_GNSS trace.
Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information.
BG95_Hardware_Design 55 / 80
LPWA Module Series
5 Antenna Interfaces
BG95 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an
impedance of 50Ω.
5.1. Main Antenna Interface
5.1.1. Pin Definition
The pin definition of main antenna interface is shown below.
Table 27: Pin Definition of Main Antenna Interface
Pin Name Pin No. I/O Description Comment
ANT_MAIN 60 IO Main antenna interface 50Ω characteristic impedance
5.1.2. Operating Frequency
Table 28: BG95 Operating Frequency
3GPP Band Transmit Receive Unit
LTE-FDD B1 1920~1980 2110~2170 MHz
LTE-FDD B2, PCS1900 1850~1910 1930~1990 MHz
LTE-FDD B3, DCS1800 1710~1785 1805~1880 MHz
LTE-FDD B4 1710~1755 2110~2155 MHz
LTE-FDD B5, GSM850 824~849 869~894 MHz
LTE-FDD B8, EGSM900 880~915 925~960 MHz
LTE-FDD B12 699~716 729~746 MHz
BG95_Hardware_Design 56 / 80
LPWA Module Series
LTE-FDD B13 777~787 746~756 MHz
LTE-FDD B14
1)
788~798 758~768 MHz
LTE-FDD B18 815~830 860~875 MHz
LTE-FDD B19 830~845 875~890 MHz
LTE-FDD B20 832~862 791~821 MHz
LTE-FDD B25 1850~1915 1930~1995 MHz
LTE-FDD B26* 814~849 859~894 MHz
LTE-FDD B27
1)
807~824 852~869 MHz
LTE-FDD B28 703~748 758~803 MHz
LTE-TDD B66 1710~1780 2110~2200 MHz
LTE-TDD B71
2)
663~698 617~652 MHz
LTE-TDD B85 698~716 728~746 MHz
NOTES
1)
1.
LTE-FDD B14 and B27 are supported by Cat M1 only.
2)
2.
LTE-FDD B71 is supported by Cat NB2 only.
3. “*” means under development.
5.1.3. Reference Design of RF Antenna Interface
A reference design of main antenna pad is shown as below. A π-type matching circuit should be reserved
for better RF performance, and the π-type matching components (R1/C1/C2) should be placed as close
to the antenna as possible. The capacitors are not mounted by default.
BG95_Hardware_Design 57 / 80
LPWA Module Series
Figure 22: Reference Circuit of RF Antenna Interface
5.1.4. Reference Design of RF Layout
For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the distance between signal layer and reference ground (H), and the clearance between RF trace and
ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic
impedance control. The following are reference designs of microstrip line or coplanar waveguide line with
different PCB structures.
Figure 23: Microstrip Line Design on a 2-layer PCB
BG95_Hardware_Design 58 / 80
LPWA Module Series
Figure 24: Coplanar Waveguide Line Design on a 2-layer PCB
Figure 25: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)
BG95_Hardware_Design 59 / 80
LPWA Module Series
In order to ensure RF performance and reliability, the following principles should be complied with in RF
layout design:
Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω.
The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
The distance between the RF pins and the RF connector should be as short as possible, and all the
right angle traces should be changed to curved ones.
There should be clearance area under the signal pin of the antenna connector or solder joint.
The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).
For more details about RF layout, please refer to document [4].
5.2. GNSS Antenna Interface
The following tables show the pin definition and frequency specification of GNSS antenna interface.
Table 29: Pin Definition of GNSS Antenna Interface
Pin Name Pin No. I/O Description Comment
ANT_GNSS 49 AI GNSS antenna interface 50Ω impedance
Table 30: GNSS Frequency
Type Frequency Unit
GPS 1575.42±1.023 MHz
GLONASS 1597.5~1605.8 MHz
Galileo 1575.42±2.046 MHz
BeiDou 1561.098±2.046 MHz
A reference design of GNSS antenna interface is shown as below.
BG95_Hardware_Design 60 / 80
LPWA Module Series
Figure 27: Reference Circuit of GNSS Antenna Interface
NOTES
1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
5.3. Antenna Installation
5.3.1. Antenna Requirements
The following table shows the requirements on main antenna and GNSS antenna.
Table 31: Antenna Requirements
Antenna Type Requirements
Frequency range: 1559MHz ~1609MHz
Polarization: RHCP or linear
VSWR: < 2 (Typ.)
GNSS 1)
Passive antenna gain: > 0dBi
Active antenna noise figure: < 1.5dB
Active antenna gain: > 0dBi
Active antenna embedded LNA gain: < 17dB
VSWR: ≤ 2
LTE/GSM
BG95_Hardware_Design 61 / 80
Efficiency: > 30%
Max Input Power (W): 50
Input Impedance (Ω): 50
LPWA Module Series
Cable Insertion Loss: < 1dB
2)
(LTE B5/B8/B12/B13/B14
/B18/B19/B20/B26*/B27 2)/B28/B71 3)/ B85,
GSM850/EGSM900)
Cable Insertion Loss: < 1.5dB
(LTE B1/B2/B3/B4/B25/B66, DCS1800/PCS1900)
NOTES
1)
1.
It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use
of active antenna may generate harmonics which will affect the GNSS performance.
2)
2.
LTE-FDD B14 and B27 are supported by Cat M1 only.
3)
3.
LTE-FDD B71 is supported by Cat NB2 only.
4. “*” means under development.
5.3.2. Recommended RF Connector for Antenna Installation
If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector
provided by HIROSE.
Figure 28: Dimensions of the U.FL-R-SMT Connector (Unit: mm)
U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.
BG95_Hardware_Design 62 / 80
LPWA Module Series
Figure 29: Mechanicals of U.FL-LP Connectors
The following figure describes the space factor of mated connector.
Figure 30: Space Factor of Mated Connector (Unit: mm)
For more details, please visit http://www.hirose.com
.
BG95_Hardware_Design 63 / 80
LPWA Module Series
6 Electrical, Reliability and Radio
Characteristics
6.1. Absolute Maximum Ratings
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.
Table 32: Absolute Maximum Ratings
Parameter Min. Max. Unit
VBAT_BB -0.5 6.0 V
VBAT_RF -0.3 6.0 V
USB_VBUS -0.3 5.5 V
Voltage at Digital Pins -0.3 2.3 V
6.2. Power Supply Ratings
Table 33: Power Supply Ratings
Parameter Description Conditions Module Min. Typ. Max. Unit
The actual input
VBAT
I
Peak supply Maximum power BG95-M3 1.8 2.0 A
VBAT
BG95_Hardware_Design 64 / 80
VBAT_BB/
VBAT_RF
voltages must stay
between the minimum
and maximum values.
BG95-M1/
BG95-M2/
BG95-N1
BG95-M3 3.3 3.8 4.3 V
2.4 3.3 4.8 V
LPWA Module Series
current (during
transmission slot)
control level on
EGSM900
BG95-M1/
USB_VBUS USB detection
BG95-M2/
BG95-N1/
3.0 5.0 5.25 V
BG95-M3
6.3. Operation and Storage Temperatures
The operation and storage temperatures of the module are listed in the following table.
Table 34: Operation and Storage Temperatures
Parameter Min. Typ. Max. Unit
Operation Temperature Range 1) -35 +25 +75 ºC
Extended Temperature Range 2) -40 +85 ºC
Storage Temperature Range -40 +90 ºC
NOTES
1)
1.
Within operation temperature range, the module is 3GPP compliant.
2)
2.
Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters
like Pout might reduce in their value and exceed the specified tolerances. When the temperature
returns to the normal operating temperature levels, the module will meet 3GPP specifications again.
6.4. RF Output Power
The following table shows the RF output power of BG95.
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LPWA Module Series
Table 35: BG95 RF Output Power
Frequency Max. Min.
LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B14 1)/B18/B19/B20/B25/
B26*/B27
1)
/B28/B66/B71
2)
/B85
20dBm±2dB <-39dBm
GSM850/EGSM900 33dBm±2dB 5dBm±5dB
DCS1800/PCS1900 30dBm±2dB 0dBm±5dB
GSM850/EGSM900 (8-PSK) 27dBm±3dB 5dBm±5dB
DCS1800/PCS1900 (8-PSK) 26dBm±3dB 0dBm±5dB
NOTES
1)
1.
LTE-FDD B14 and B27 are supported by Cat M1 only.
2)
2.
LTE-FDD B71 is supported by Cat NB2 only.
3. “*” means under development.
6.5. RF Receiving Sensitivity
The following table shows the conducted RF receiving sensitivity of BG95.
Table 36: BG95 Conducted RF Receiving Sensitivity
Network Band Primary Diversity
Cat M1/3GPP Cat NB2 1)/3GPP
LTE-FDD B1
TBD/-102.7 TBD/-107.5
LTE-FDD B2 TBD /-100.3 TBD/-107.5
LTE-FDD B3 TBD /-99.3 TBD/-107.5
LTE
LTE-FDD B4 TBD /-102.3 TBD/-107.5
Supported
Not
Supported
LTE-FDD B5 TBD /-100.8 TBD/-107.5
LTE-FDD B8 TBD /-99.8 TBD/-107.5
Sensitivity (dBm)
LTE-FDD B12 TBD /-99.3 TBD/-107.5
BG95_Hardware_Design 66 / 80
LPWA Module Series
LTE-FDD B13 TBD /-99.3 TBD/-107.5
LTE-FDD B14 TBD /-99.3 /
LTE-FDD B18 TBD /-102.3 TBD/-107.5
LTE-FDD B19 TBD /-102.3 TBD/-107.5
LTE-FDD B20 TBD /-99.8 TBD/-107.5
LTE-FDD B25 TBD /-100.3 TBD/-107.5
LTE-FDD B26* TBD /-100.3 TBD/-107.5
LTE-FDD B27 TBD /-100.8 /
LTE-FDD B28 TBD /-100.8 TBD/-107.5
LTE-FDD B66 TBD TBD/-107.5
LTE-FDD B71 / TBD/-107.5
LTE-FDD B85 TBD TBD/-107.5
Network Band Primary Diversity
GSM
GSM850/EGSM900
Supported
DCS1800/PCS1900 TBD/-102
Not
Supported
NOTES
1. 1) LTE Cat NB2 receiving sensitivity without repetitions.
2. “*” means under development.
Sensitivity (dBm)
GSM/3GPP
TBD/-102
6.6. Electrostatic Discharge
The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject
to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and
packaging procedures must be applied throughout the processing, handling and operation of any
application that incorporates the module.
The following table shows the electrostatic discharge characteristics of BG95 module.
BG95_Hardware_Design 67 / 80
LPWA Module Series
Table 37: Electrostatic Discharge Characteristics (25ºC, 45% Relative Humidity)
Tested Points Contact Discharge Air Discharge Unit
VBAT, GND TBD TBD kV
Main/GNSS Antenna
Interfaces
TBD TBD kV
BG95_Hardware_Design 68 / 80
LPWA Module Series
7 Mechanical Dimensions
This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm,
and the tolerances for dimensions without tolerance values are ±0.05mm.
7.1. Mechanical Dimensions of the Module
Pin 1
23.60±0.15
19.90±0.15
Figure 31: Module Top and Side Dimensions
2.2±0.2
BG95_Hardware_Design 69 / 80
LPWA Module Series
19.90±0.15
7.15
7.45
1.00
23.60±0.15
0.20
1.00
8.50
1.10
1.00
5.10
0.55
0.85
1.95
1.70
1.10
1.70
1.00
0.20
1.90
Pin 1
1.10
1.00
1.70
0.55
0.70
1.15
0.50
0.20
0.20
40x1.0
40x1.0
Figure 32: Module Bottom Dimensions (Bottom View)
62x0.7
62x1.15
BG95_Hardware_Design 70 / 80
7.2. Recommended Footprint
9.18 9.18
7.45 7.15
1.00
1.00
Pin 1
1.10
1.95
19.90±0.15
0.55
2.55 2.55
LPWA Module Series
1.10
5.10
0.20
0.20
23.60±0.15
0.15
1.90
1.10
0.50
0.20
0.70
1.15
62x1.15
1.70
0.85
1.70
1.70
4.25
5.95
62x0.7
0.55
0.85
1.00
0.85
0.85
1.00
4.25
5.95
40x1.0
1.00
40x1.0
8.50
11.0311.03
7.657.65
5.955.95
4.254.25
9.60 9.70
0.20
Figure 33: Recommended Footprint (Top View)
NOTES
1. For easy maintenance of the module, please keep about 3mm between the module and other
components on the host PCB.
2. All reserved pins must be kept open.
3. For stencil design requirements of the module, please refer to document [5].
BG95_Hardware_Design 71 / 80
7.3. Design Effect Drawings of the Module
LPWA Module Series
Figure 34: Top View of the Module
Figure 35: Bottom View of the Module
NOTE
These are renderings of BG95 module. For authentic appearance, please refer to the module that you
receive from Quectel.
BG95_Hardware_Design 72 / 80
LPWA Module Series
8 Storage, Manufacturing and
Packaging
8.1. Storage
BG95 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below.
1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH.
2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other
high temperature processes must be:
Mounted within 168 hours at the factory environment of ≤30ºC/60%RH.
Stored at <10%RH.
3. Devices require baking before mounting, if any circumstance below occurs.
When the ambient temperature is 23ºC±5ºC and the humidity indication card shows the humidity
is >10% before opening the vacuum-sealed bag.
Device mounting cannot be finished within 168 hours at factory conditions of ≤30ºC/60% RH.
4. If baking is required, devices may be baked for 8 hours at 120ºC±5ºC.
NOTE
As the plastic package cannot be subjected to high temperature, it should be removed from devices
before high temperature (120ºC) baking. If shorter baking time is desired, please refer to
IPC/JEDECJ-STD-033 for baking procedure.
BG95_Hardware_Design 73 / 80
LPWA Module Series
8.2. Manufacturing and Soldering
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the
thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please
refer to document [5].
It is suggested that the peak reflow temperature is 238~245ºC, and the absolute maximum reflow
temperature is 245ºC. To avoid damage to the module caused by repeated heating, it is strongly
recommended that the module should be mounted after reflow soldering for the other side of PCB has
been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and
related parameters are shown below.
Temp. (°C)
Reflow Zone
Max slope: 2~3°C/sec
245
C
Cooling down slope: 1~4°C/sec
238
220
200
B
D
Soak Zone
150
A
100
Max slope: 1~3°C/sec
Figure 36: Recommended Reflow Soldering Thermal Profile
Table 38: Recommended Thermal Profile Parameters
Factor Recommendation
Soak Zone
Max slope 1 to 3°C/sec
Soak time (between A and B: 150°C and 200°C) 60 to 120 sec
BG95_Hardware_Design 74 / 80
LPWA Module Series
Reflow Zone
Max slope 2 to 3°C/sec
Reflow time (D: over 220°C) 40 to 60 sec
Max temperature 238°C ~ 245°C
Cooling down slope 1 to 4°C/sec
Reflow Cycle
Max reflow cycle 1
8.3. Packaging
BG95 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until
the devices are ready to be soldered onto the application.
The reel is 330mm in diameter and each reel contains 250 modules. The following figures show the
packaging details, measured in mm.
Figure 37: Tape Dimensions
BG95_Hardware_Design 75 / 80
LPWA Module Series
DETAIL:A
6
PS
DETAIL:A
Figure 38: Reel Dimensions
Table 39: Reel Packaging
Model Name MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs
BG95 250pcs
Size: 370mm × 350mm × 56mm
N.W: 0.61kg
G.W: 1.35kg
Size: 380mm × 250mm × 365mm
N.W: 2.45kg
G.W: 6.28kg
BG95_Hardware_Design 76 / 80
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9 Appendix A References
Table 40: Related Documents
SN Document Name Remark
[1] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide
[2] Quectel_BG95_AT_Commands_Manual BG95 AT Commands Manual
[3] Quectel_BG95_GNSS_AT_Commands_Manual BG95 GNSS AT Commands Manual
[4] Quectel_RF_Layout_Application_Note RF Layout Application Note
[5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide
Table 41: Terms and Abbreviations
Abbreviation Description
AMR Adaptive Multi-rate
bps Bits Per Second
CHAP Challenge Handshake Authentication Protocol
CS Coding Scheme
CTS Clear To Send
DFOTA Delta Firmware Upgrade Over The Air
DL Downlink
DTR Data Terminal Ready
DTX Discontinuous Transmission
e-I-DRX Extended Idle Mode Discontinuous Reception
EPC Evolved Packet Core
BG95_Hardware_Design 77 / 80
ESD Electrostatic Discharge
FDD Frequency Division Duplex
FR Full Rate
GMSK Gaussian Minimum Shift Keying
GSM Global System for Mobile Communications
HSS Home Subscriber Server
I/O Input/Output
Inorm Normal Current
LED Light Emitting Diode
LPWA Module Series
LNA Low Noise Amplifier
LTE Long Term Evolution
MO Mobile Originated
MS Mobile Station (GSM engine)
MT Mobile Terminated
PAP Password Authentication Protocol
PCB Printed Circuit Board
PDU Protocol Data Unit
PPP Point-to-Point Protocol
PSM Power Saving Mode
RF Radio Frequency
RHCP Right Hand Circularly Polarized
Rx Receive
SISO Single Input Single Output
SMS Short Message Service
TDD Time Division Duplexing
BG95_Hardware_Design 78 / 80
TX Transmitting Direction
UL Uplink
UE User Equipment
URC Unsolicited Result Code
(U)SIM (Universal) Subscriber Identity Module
Vmax Maximum Voltage Value
Vnorm Normal Voltage Value
Vmin Minimum Voltage Value
VIHmax Maximum Input High Level Voltage Value
LPWA Module Series
VIHmin Minimum Input High Level Voltage Value
VILmax Maximum Input Low Level Voltage Value
VILmin Minimum Input Low Level Voltage Value
VImax Absolute Maximum Input Voltage Value
VImin Absolute Minimum Input Voltage Value
VOHmax Maximum Output High Level Voltage Value
VOHmin Minimum Output High Level Voltage Value
VOLmax Maximum Output Low Level Voltage Value
VOLmin Minimum Output Low Level Voltage Value
VSWR Voltage Standing Wave Ratio
BG95_Hardware_Design 79 / 80
LPWA Module Series
10 Appendix B GPRS Coding Schemes
Table 42: Description of Different Coding Schemes
Scheme
Code Rate
USF
Pre-coded USF
Radio Block excl.USF and BCS
BCS
Tail
Coded Bits
Punctured Bits
Data Rate Kb/s
CS-1 CS-2 CS-3 CS-4
1/2 2/3 3/4 1
3 3 3 3
3 6 6 12
181 268 312 428
40 16 16 16
4 4 4 -
456 588 676 456
0 132 220 -
9.05 13.4 15.6 21.4
BG95_Hardware_Design 80 / 80
LPWA Module Series
11 Appendix C GPRS Multi-slot Classes
Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot
classes are product dependent, and determine the maximum achievable data rates in both the uplink and
downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots,
while the second number indicates the amount of uplink timeslots. The active slots determine the total
number of slots the GPRS device can use simultaneously for both uplink and downlink communications.
The description of different multi-slot classes is shown in the following table.
Table 43: GPRS Multi-slot Classes
Multislot Class Downlink Slots Uplink Slots Active Slots
1 1 1 2
2 2 1 3
3 2 2 3
4 3 1 4
5 2 2 4
6 3 2 4
7 3 3 4
8 4 1 5
9 3 2 5
10 4 2 5
11 4 3 5
12 4 4 5
13 3 3 NA
14 4 4 NA
BG95_Hardware_Design 81 / 80
LPWA Module Series
15 5 5 NA
16 6 6 NA
17 7 7 NA
18 8 8 NA
19 6 2 NA
20 6 3 NA
21 6 4 NA
22 6 4 NA
23 6 6 NA
24 8 2 NA
25 8 3 NA
26 8 4 NA
27 8 4 NA
28 8 6 NA
29 8 8 NA
30 5 1 6
31 5 2 6
32 5 3 6
33 5 4 6
BG95_Hardware_Design 82 / 80
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12 Appendix D EDGE Modulation and
Coding Schemes
Table 44: EDGE Modulation and Coding Schemes
Coding Schemes
CS-1 GMSK / 9.05kbps 18.1kbps 36.2kbps
CS-2 GMSK / 13.4kbps 26.8kbps 53.6kbps
CS-3 GMSK / 15.6kbps 31.2kbps 62.4kbps
CS-4 GMSK / 21.4kbps 42.8kbps 85.6kbps
MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps
MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps
MCS-3 GMSK A 14.8kbps 29.6kbps 59.2kbps
MCS-4 GMSK C 17.6kbps 35.2kbps 70.4kbps
MCS-5 8-PSK B 22.4kbps 44.8kbps 89.6kbps
MCS-6 8-PSK A 29.6kbps 59.2kbps 118.4kbps
Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot
MCS-7 8-PSK B 44.8kbps 89.6kbps 179.2kbps
MCS-8 8-PSK A 54.4kbps 108.8kbps 217.6kbps
MCS-9 8-PSK A 59.2kbps 118.4kbps 236.8kbps
BG95_Hardware_Design 83 / 80
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