Table Index ............................................................................................................................................... 8
Figure Index ............................................................................................................................................ 10
Support 3GPP R8 DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA
Support QPSK, 16-QAM and 64-QAM modulation
DC-HSDPA: Max 42Mbps (DL)
HSUPA: Max 5.76Mbps (UL)
WCDMA: Max 384Kbps (DL)/Max 384Kbps (UL)
GSM Features
Internet Protocol Features
SMS
GPRS:
Support GPRS multi-slot class 33 (33 by default)
Coding scheme: CS-1, CS-2, CS-3 and CS-4
Max 107Kbps (DL)/Max 85.6Kbps (UL)
EDGE:
Support EDGE multi-slot class 33 (33 by default)
Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
Downlink coding schemes: CS 1-4 and MCS 1-9
Uplink coding schemes: CS 1-4 and MCS 1-9
Max 296Kbps (DL)/Max 236.8Kbps (UL)
Support TCP/UDP/PPP/FTP/HTTP/NTP/PING/QMI/NITZ/CMUX*/HTTPS*/
SMTP/MMS*/FTPS*/SMTPS*/SSL*/FILE* protocols
Support PAP (Password Authentication Protocol) and CHAP (Challenge
Handshake Authentication Protocol) protocols which are usually used for
PPP connections
Text and PDU mode
Point to point MO and MT
SMS cell broadcast
SMS storage: ME by default
(U)SIM Interface Support USIM/SIM card: 1.8V, 3.0V
Support one digital audio interface: PCM interface
GSM: HR/FR/EFR/AMR/AMR-WB
Audio Features
WCDMA: AMR/AMR-WB
LTE: AMR/AMR-WB
Support echo cancellation and noise suppression
EC25_Hardware_Design 19 / 112
PCM Interface
USB Interface
UART Interfaces
LTE Standard Module Series
EC25 Hardware Design
Used for audio function with external codec
Support 16-bit linear data format
Support long frame synchronization and short frame synchronization
Support master and slave modes, but must be the master in long frame
synchronization
Compliant with USB 2.0 specification (slave only); the data transfer rate can
reach up to 480Mbps
Used for AT command communication, data transmission, GNSS NMEA
output, software debugging, firmware upgrade and voice over USB
Support USB serial drivers for: Windows 7/8/8.1/10, Windows CE
5.0/6.0/7.0*, Linux 2.6/3.x/4.1~4.14, Android 4.x/5.x/6.x/7.x/8.x/9.x, etc.
Main UART:
Used for AT command communication and data transmission
Baud rates reach up to 921600bps, 115200bps by default
Support RTS and CTS hardware flow control
Debug UART:
Used for Linux console and log output
115200bps baud rate
SD Card Interface Support SD 3.0 protocol
SGMII Interface
Wireless Connectivity
Interfaces
Support 10M/100M/1000M Ethernet work mode
Support maximum 150Mbps (DL)/50Mbps (UL) for 4G network
Support a low-power SDIO 3.0 interface for WLAN and UART/PCM
interface for Bluetooth*
Rx-diversitySupport LTE/WCDMA Rx-diversity
GNSS Features
AT Commands
Network Indication
Antenna Interfaces
Physical Characteristics
Gen8C Lite of Qualcomm
Protocol: NMEA 0183
Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT
commands
Two pins including NET_MODE and NET_STATUS to indicate network
connectivity status
Including main antenna interface (ANT_MAIN), Rx-diversity antenna
interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS)
Size: (29.0±0.15)mm × (32.0±0.15)mm × (2.4±0.2)mm
Weight: approx. 4.9g
Operation temperature range: -35°C ~ +75°C
Temperature Range
Extended temperature range: -40°C ~ +85°C
Storage temperature range: -40°C~ +90°C
1)
2)
Firmware Upgrade USB interface or DFOTA*
RoHS All hardware components are fully compliant with EU RoHS directive
EC25_Hardware_Design 20 / 112
LTE Standard Module Series
EC25 Hardware Design
NOTES
1)
1.
Within operation temperature range, the module is 3GPP compliant.
2)
2.
Within extended temperature range, the module remains the ability to establish and maintain a
voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There
are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like
P
might reduce in their value and exceed the specified tolerances. When the temperature returns to
out
normal operation temperature levels, the module will meet 3GPP specifications again.
3. “*” means under development.
2.3. Functional Diagram
The following figure shows a block diagram of EC25 and illustrates the major functional parts.
Power management
Baseband
DDR+NAND flash
Radio frequency
Peripheral interfaces
EC25_Hardware_Design 21 / 112
LTE Standard Module Series
EC25 Hardware Design
ANT_MAINANT_DIVANT_GNSS
VBAT_RF
VBAT_BB
PWRKEY
RESET_N
ADCs
STATUS
APT
PMIC
VDD_EXT
SAW
Tx
Control
19.2 M
PAM
Duplex
PA
PRxDRx
Transceiver
IQCont rol
XO
USB (U)SIMPCMUARTsI2C
SAW
LNA
Switch
SAW
SDRAM
Baseband
SGMII
NAND
DDR2
WLANSDBT*
GPIOs
Figure 1: Functional Diagram
NOTE
“*” means under development.
2.4. Evaluation Board
In order to help customers develop applications with EC25, Quectel supplies an evaluation board (EVB),
USB to RS-232 converter cable, earphone, antenna and other peripherals to control or test the module.
EC25_Hardware_Design 22 / 112
LTE Standard Module Series
EC25 Hardware Design
3Application Interfaces
3.1. General Description
EC25 is equipped with 80 LCC pads plus 64 LGA pads that can be connected to cellular application
platform. Sub-interfaces included in these pads are described in detail in the following chapters:
Power supply
(U)SIM interface
USB interface
UART interfaces
PCM and I2C interfaces
SD card interface
ADC interfaces
Status indication
SGMII interface
Wireless connectivity interfaces
USB_BOOT interface
EC25_Hardware_Design 23 / 112
EC25 Hardware Design
3.2. Pin Assignment
The following figure shows the pin assignment of EC25 module.
LTE Standard Module Series
Figure 2: Pin Assignment (Top View)
NOTES
1)
1.
means that these pins cannot be pulled up before startup.
2)
2.
PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset.
3)
3.
means these interface functions are only supported on Telematics version.
4. Pads 37~40, 118, 127 and 129~139 are used for wireless connectivity interfaces, among which pads
118, 127 and 129~138 are WLAN function pins, and others are Bluetooth (BT) function pins. BT
function is under development.
5. Pads 119~126 and 128 are used for SGMII interface.
EC25_Hardware_Design 24 / 112
LTE Standard Module Series
EC25 Hardware Design
6. Pads 24~27 are multiplexing pins used for audio design on EC25 module and BT function on the BT
module.
7. Keep all RESERVED pins and unused pins unconnected.
8. GND pads 85~112 should be connected to ground in the design. RESERVED pads 73~84 should not
be designed in schematic and PCB decal, and these pins should be served as a keepout area.
9. “*” means under development.
3.3. Pin Description
The following tables show the pin definition of EC25 module.
Table 3: I/O Parameters Definition
Type Description
AI Analog input
AO Analog output
DI Digital input
DO Digital output
IO Bidirectional
OD Open drain
PI Power input
PO Power output
Table 4: Pin Description
Power Supply
Pin Name Pin No. I/O Description DC Characteristics Comment
VBAT_BB 59, 60 PI
VBAT_RF 57, 58 PI
Power supply for
module’s baseband
part
Power supply for
module’s RF part
Vmax=4.3V
Vmin=3.3V
Vnorm=3.8V
Vmax=4.3V
Vmin=3.3V
It must be able to
provide sufficient
current up to 0.8A.
It must be able to
provide sufficient
EC25_Hardware_Design 25 / 112
LTE Standard Module Series
EC25 Hardware Design
Vnorm=3.8V current up to 1.8A in a
burst transmission.
Power supply for
VDD_EXT 7 PO
Provide 1.8V for
external circuit
Vnorm=1.8V
I
max=50mA
O
external GPIO’s pull-up
circuits.
If unused, keep it open.
8, 9, 19,
22, 36, 46,
GND
48, 50~54,
Ground
56, 72,
85~112
Turn on/off
Pin Name Pin No. I/O Description DC Characteristics Comment
The output voltage is
PWRKEY 21 DI
Turn on/off the
module
V
H
=0.8V
0.8V because of the
diode drop in the
Qualcomm chipset.
V
max=2.1V
IH
V
min=1.3V
IH
V
max=0.5V
IL
If unused, keep it
open.
RESET_N 20 DI
Reset signal of the
module
Status Indication
Pin Name Pin No. I/O Description DC Characteristics Comment
An external pull-up
resistor is required.
If unused, keep it
open.
STATUS 61 OD
Indicate the module
operating status
The drive current
should be less than
0.9mA.
1.8V power domain.
It cannot be pulled up
before startup.
If unused, keep it
NET_MODE 5 DO
Indicate the
module’s network
registration mode
V
min=1.35V
OH
V
max=0.45V
OL
open.
NET_
STATUS
Indicate the
6 DO
module’s network
activity status
V
min=1.35V
OH
V
max=0.45V
OL
1.8V power domain.
If unused, keep it
open.
USB Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
USB_VBUS 71 PI
USB power supply,
used for USB
detection
Vmax=5.25V
Vmin=3.0V
Vnorm=5.0V
Typical: 5.0V
If unused, keep it
open.
EC25_Hardware_Design 26 / 112
LTE Standard Module Series
EC25 Hardware Design
Require differential
impedance of 90Ω.
If unused, keep it
open.
Require differential
impedance of 90Ω.
If unused, keep it
open.
USB_DP 69 IO
USB_DM 70 IO
USB differential data
bus (+)
USB differential data
bus (-)
Compliant with USB
2.0 standard
specification.
Compliant with USB
2.0 standard
specification.
(U)SIM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
USIM_GND 10
USIM_
PRESENCE
13 DI
Specified ground for
(U)SIM card
(U)SIM card
insertion detection
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
For 1.8V(U)SIM:
Vmax=1.9V
Vmin=1.7V
USIM_VDD 14 PO
Power supply for
(U)SIM card
For 3.0V(U)SIM:
Vmax=3.05V
Either 1.8V or 3.0V is
supported by the
module automatically.
Vmin=2.7V
I
max=50mA
O
For 1.8V (U)SIM:
V
max=0.6V
IL
V
min=1.2V
IH
V
max=0.45V
OL
V
min=1.35V
OH
For 3.0V (U)SIM:
max=1.0V
V
IL
V
min=1.95V
IH
V
max=0.45V
OL
V
min=2.55V
OH
USIM_DATA 15 IO
Data signal of
(U)SIM card
For 1.8V (U)SIM:
V
max=0.45V
OL
USIM_CLK 16 DO
Clock signal of
(U)SIM card
V
min=1.35V
OH
For 3.0V (U)SIM:
max=0.45V
V
OL
EC25_Hardware_Design 27 / 112
LTE Standard Module Series
EC25 Hardware Design
VOHmin=2.55V
For 1.8V (U)SIM:
max=0.45V
V
OL
V
min=1.35V
OH
For 3.0V (U)SIM:
max=0.45V
V
OL
V
min=2.55V
OH
USIM_RST 17 DO
Reset signal of
(U)SIM card
Main UART Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
V
RI 62 DO Ring indicator
DCD 63 DO
Data carrier
detection
CTS 64 DO Clear to send
RTS 65 DI Request to send
DTR 66 DI
Data terminal ready,
sleep mode control
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
max=0.45V
min=1.35V
max=0.45V
min=1.35V
max=0.45V
min=1.35V
min=-0.3V
max=0.6V
min=1.2V
max=2.0V
min=-0.3V
max=0.6V
min=1.2V
max=2.0V
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
Pulled up by default.
Low level wakes up
the module.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
TXD 67 DO Transmit data
RXD 68 DI Receive data
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
Debug UART Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
DBG_TXD 12 DO Transmit data
max=0.45V
OL
V
min=1.35V
OH
1.8V power domain.
If unused, keep it
V
EC25_Hardware_Design 28 / 112
LTE Standard Module Series
EC25 Hardware Design
open.
V
min=-0.3V
DBG_RXD 11 DI Receive data
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
ADC Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
General purpose
ADC0 45 AI
analog to digital
converter
General purpose
ADC1 44 AI
analog to digital
converter
Voltage range:
0.3V to VBAT_BB
Voltage range:
0.3V to VBAT_BB
If unused, keep it
open.
If unused, keep it
open.
PCM Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
V
min=-0.3V
PCM_IN 24 DI PCM data input
PCM_OUT 25 DO PCM data output
PCM data frame
PCM_SYNC 26 IO
synchronization
signal
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
VOLmax=0.45V
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
In master mode, it is
an output signal. In
slave mode, it is an
input signal.
If unused, keep it
open.
1.8V power domain.
In master mode, it is
an output signal. In
slave mode, it is an
input signal.
If unused, keep it
open.
PCM_CLK 27 IO PCM clock
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
I2C Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
EC25_Hardware_Design 29 / 112
LTE Standard Module Series
EC25 Hardware Design
I2C serial clock.
I2C_SCL 41 OD
Used for external
codec.
I2C serial data.
I2C_SDA 42 OD
Used for external
codec.
An external pull-up
resistor is required.
1.8V only. If unused,
keep it open.
An external pull-up
resistor is required.
1.8V only. If unused,
keep it open.
SD Card Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
SDC2_
DATA3
28 IO
SD card SDIO bus
DATA3
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
SDC2_
DATA2
SDC2_
DATA1
29 IO
30 IO
SD card SDIO bus
DATA2
SD card SDIO bus
DATA1
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
EC25_Hardware_Design 30 / 112
LTE Standard Module Series
EC25 Hardware Design
SDC2_
DATA0
31 IO
SDC2_CLK 32 DO
SD card SDIO bus
DATA0
SD card SDIO bus
clock
VOHmin=1.4V
VILmin=-0.3V
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
min=1.72V
IH
V
max=3.34V
IH
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
3.0V signaling:
max=0.38V
V
OL
V
min=2.01V
OH
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDIO signal level can
be selected according
to SD card supported
level, please refer to
SD 3.0 protocol for
more details.
If unused, keep it
open.
SDC2_CMD 33 IO
SD card SDIO bus
command
1.8V signaling:
V
max=0.45V
OL
V
min=1.4V
OH
V
min=-0.3V
IL
V
max=0.58V
IL
V
min=1.27V
IH
V
max=2.0V
IH
EC25_Hardware_Design 31 / 112
EC25 Hardware Design
SD_INS_
DET
23 DI
VDD_SDIO 34 PO
SD card insertion
detect
SD card SDIO bus
pull-up power
3.0V signaling:
V
OL
V
OH
V
min=-0.3V
IL
V
max=0.76V
IL
V
IH
V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
IH
V
IH
I
max=50mA
O
max=0.38V
min=2.01V
min=1.72V
max=3.34V
min=1.2V
max=2.0V
LTE Standard Module Series
1.8V power domain.
If unused, keep it
open.
1.8V/2.85V
configurable.
Cannot be used for
SD card power.
If unused, keep it
open.
SGMII Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
For 1.8V:
V
max=0.45V
EPHY_RST_
N
119 DO Ethernet PHY reset
EPHY_INT_N 120 DI
Ethernet PHY
interrupt
OL
V
min=1.4V
OH
For 2.85V:
max=0.35V
V
OL
V
min=2.14V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V/2.85V power
domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
For 1.8V:
VOLmax=0.45V
V
min=1.4V
OH
V
max=0.58V
SGMII_
MDATA
SGMII MDIO
121 IO
(Management Data
Input/Output) data
IL
V
min=1.27V
IH
For 2.85V:
max=0.35V
V
OL
V
min=2.14V
OH
V
max=0.71V
IL
V
min=1.78V
IH
1.8V/2.85V power
domain.
If unused, keep it
open.
EC25_Hardware_Design 32 / 112
EC25 Hardware Design
SGMII_
MCLK
122 DO
USIM2_VDD 128 PO
SGMII_TX_M 123 AO
SGMII MDIO
(Management Data
Input/Output) clock
SGMII MDIO pull-up
power source
SGMII transmission
- minus
For 1.8V:
V
max=0.45V
OL
V
min=1.4V
OH
For 2.85V:
max=0.35V
V
OL
V
min=2.14V
OH
LTE Standard Module Series
1.8V/2.85V power
domain.
If unused, keep it
open.
Configurable power
source.
1.8V/2.85V power
domain.
External pull-up for
SGMII MDIO pins.
If unused, keep it
open.
Connect with a 0.1uF
capacitor, close to the
PHY side.
If unused, keep it
open.
Connect with a 0.1uF
capacitor, close to the
PHY side.
If unused, keep it
SGMII_TX_P 124 AO
SGMII transmission
- plus
open.
Connect with a 0.1uF
capacitor, close to
EC25 module.
If unused, keep it
SGMII_RX_P 125 AI
SGMII receiving
- plus
open.
Connect with a 0.1uF
capacitor, close to
EC25 module.
If unused, keep it
SGMII_RX_M 126 AI
SGMII receiving
- minus
open.
Wireless Connectivity Interfaces
Pin Name Pin No. I/O Description DC Characteristics Comment
V
max=0.45V
OL
V
SDC1_
DATA3
129 IO
WLAN SDIO data
bus D3
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
1.8V power domain.
If unused, keep it
open.
EC25_Hardware_Design 33 / 112
EC25 Hardware Design
SDC1_
DATA2
SDC1_
DATA1
SDC1_
DATA0
130 IO
131 IO
132 IO
SDC1_CLK 133 DO
WLAN SDIO data
bus D2
WLAN SDIO data
bus D1
WLAN SDIO data
bus D0
WLAN SDIO bus
clock
VIHmax=2.0V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
max=0.45V
OL
min=1.35V
OH
min=-0.3V
IL
max=0.6V
IL
min=1.2V
IH
max=2.0V
IH
max=0.45V
OL
min=1.35V
OH
min=-0.3V
IL
max=0.6V
IL
min=1.2V
IH
max=2.0V
IH
max=0.45V
OL
min=1.35V
OH
min=-0.3V
IL
max=0.6V
IL
min=1.2V
IH
max=2.0V
IH
max=0.45V
OL
min=1.35V
OH
LTE Standard Module Series
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
SDC1_CMD 134 DO
WLAN SDIO bus
command
PM_ENABLE 127 DO WLAN power control
WAKE_ON_
WIRELESS
135 DI
Wake up the host
(EC25 module) by
FC20 module
WLAN function
WLAN_EN 136 DO
control via FC20
module
COEX_UART
_RX
137 DI
LTE/WLAN&BT
coexistence signal
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
Active low.
If unused, keep it
open.
1.8V power domain.
Active high.
Cannot be pulled up
before startup.
If unused, keep it
open.
1.8V power domain.
Cannot be pulled up
before startup.
If unused, keep it
open.
EC25_Hardware_Design 34 / 112
COEX_UART
_TX
EC25 Hardware Design
138 DO
LTE/WLAN&BT
coexistence signal
LTE Standard Module Series
1.8V power domain.
V
max=0.45V
OL
V
min=1.35V
OH
Cannot be pulled up
before startup.
If unused, keep it
open.
WLAN_SLP_
CLK
BT_RTS* 37 DI
BT_TXD* 38 DO
BT_RXD* 39 DI
BT_CTS* 40 DO
BT_EN* 139 DO
118 DO WLAN sleep clock
BT UART request to
send
BT UART transmit
data
BT UART receive
data
BT UART clear to
send
BT function control
via FC20 module
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
max=0.45V
OL
V
min=1.35V
OH
V
max=0.45V
OL
V
min=1.35V
OH
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
1.8V power domain.
Cannot be pulled up
before startup.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
RF Interface
Pin Name Pin No. I/O Description DC Characteristics Comment
ANT_DIV 35 AI
Diversity antenna
pad
50Ω impedance
If unused, keep it
open.
ANT_MAIN 49 IO Main antenna pad 50Ω impedance
ANT_GNSS 47 AI GNSS antenna pad 50Ω impedance
If unused, keep it
open.
GPIO Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
V
WAKEUP_IN 1 DI Sleep mode control
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
1.8V power domain.
Cannot be pulled up
before startup.
Low level wakes up
EC25_Hardware_Design 35 / 112
EC25 Hardware Design
W_DISABLE# 4 DI
AP_READY 2 DI
USB_BOOT Interface
Airplane mode
control
Application
processor sleep
state detection
LTE Standard Module Series
the module.
If unused, keep it
open.
1.8V power domain.
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
Pull-up by default.
At low voltage level,
module can enter into
airplane mode.
If unused, keep it
open.
1.8V power domain.
If unused, keep it
open.
Pin Name Pin No. I/O Description DC Characteristics Comment
1.8V power domain.
Cannot be pulled up
before startup.
It is recommended to
reserve test point.
USB_BOOT 115 DI
Force the module to
enter into
emergency
download mode
V
min=-0.3V
IL
V
max=0.6V
IL
V
min=1.2V
IH
V
max=2.0V
IH
RESERVED Pins
Pin Name Pin No. I/O Description DC Characteristics Comment
3, 18, 43,
RESERVED
55, 73~84,
113, 114,
116, 117,
Reserved
Keep these pins
unconnected.
140-144.
NOTES
1. “*” means under development.
2. Pads 24~27 are multiplexing pins used for audio design on the EC25 module and BT function on the
BT module.
EC25_Hardware_Design 36 / 112
LTE Standard Module Series
EC25 Hardware Design
3.4. Operating Modes
The table below briefly summarizes the various operating modes referred in the following chapters.
Table 5: Overview of Operating Modes
Mode Details
Normal
Idle
Operation
Talk/Data
Minimum
Functionality
Mode
Airplane Mode
AT+CFUN command can set the module to a minimum functionality mode without
removing the power supply. In this case, both RF function and (U)SIM card will be
invalid.
AT+CFUN command or W_DISABLE# pin can set the module to airplane mode. In
this case, RF function will be invalid.
In this mode, the current consumption of the module will be reduced to the minimal
Sleep Mode
level. During this mode, the module can still receive paging message, SMS, voice
call and TCP/UDP data from the network normally.
Power Down
Mode
In this mode, the power management unit shuts down the power supply. Software is
not active. The serial interface is not accessible. Operating voltage (connected to
VBAT_RF and VBAT_BB) remains applied.
3.5. Power Saving
Software is active. The module has registered on the network, and it is
ready to send and receive data.
Network connection is ongoing. In this mode, the power consumption is
decided by network setting and data transfer rate.
3.5.1. Sleep Mode
EC25 is able to reduce its current consumption to a minimum value during the sleep mode. The following
section describes power saving procedures of EC25 module.
3.5.1.1. UART Application
If the host communicates with module via UART interface, the following preconditions can let the module
enter into sleep mode.
Execute AT+QSCLK=1 command to enable sleep mode.
Drive DTR to high level.
EC25_Hardware_Design 37 / 112
LTE Standard Module Series
EC25 Hardware Design
The following figure shows the connection between the module and the host.
Figure 3: Sleep Mode Application via UART
Driving the host DTR to low level will wake up the module.
When EC25 has a URC to report, RI signal will wake up the host. Please refer to Chapter 3.17 for
details about RI behaviors.
AP_READY will detect the sleep state of the host (can be configured to high level or low level
detection). Please refer to AT+QCFG="apready"* command for details.
NOTE
“*” meansunder development.
3.5.1.2. USB Application with USB Remote Wakeup Function
If the host supports USB suspend/resume and remote wakeup functions, the following three preconditions
must be met to let the module enter into sleep mode.
Execute AT+QSCLK=1 command to enable sleep mode.
Ensure the DTR is held at high level or keep it open.
The host’s USB bus, which is connected with the module’s USB interface, enters into suspended
state.
EC25_Hardware_Design 38 / 112
LTE Standard Module Series
EC25 Hardware Design
The following figure shows the connection between the module and the host.
Figure 4: Sleep Mode Application with USB Remote Wakeup
Sending data to EC25 through USB will wake up the module.
When EC25 has a URC to report, the module will send remote wake-up signals via USB bus so as to
wake up the host.
3.5.1.3. USB Application with USB Suspend/Resume and RI Function
If the host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is
needed to wake up the host.
There are three preconditions to let the module enter into sleep mode.
Execute AT+QSCLK=1 command to enable the sleep mode.
Ensure the DTR is held at high level or keep it open.
The host’s USB bus, which is connected with the module’s USB interface, enters into suspended
state.
The following figure shows the connection between the module and the host.
Figure 5: Sleep Mode Application with RI
EC25_Hardware_Design 39 / 112
LTE Standard Module Series
EC25 Hardware Design
Sending data to EC25 through USB will wake up the module.
When EC25 has a URC to report, RI signal will wake up the host.
3.5.1.4. USB Application without USB Suspend Function
If the host does not support USB suspend function, USB_VBUS should be disconnected via an additional
control circuit to let the module enter into sleep mode.
Execute AT+QSCLK=1 command to enable sleep mode.
Ensure the DTR is held at high level or keep it open.
Disconnect USB_VBUS.
The following figure shows the connection between the module and the host.
Figure 6: Sleep Mode Application without Suspend Function
Switching on the power switch to supply power to USB_VBUS will wake up the module.
NOTE
Please pay attention to the level match shown in dotted line between the module and the host. For more
details about EC25 power management application, please refer to document [1].
3.5.2. Airplane Mode
When the module enters into airplane mode, the RF function does not work, and all AT commands
correlative with RF function will be inaccessible. This mode can be set via the following ways.
EC25_Hardware_Design 40 / 112
LTE Standard Module Series
EC25 Hardware Design
Hardware:
The W_DISABLE# pin is pulled up by default. Driving it to low level will let the module enter into airplane
mode.
Software:
AT+CFUN command provides the choice of the functionality level through setting <fun> into 0, 1 or 4.
AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
AT+CFUN=1: Full functionality mode (by default).
AT+CFUN=4: Airplane mode. RF function is disabled.
NOTES
1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by
AT+QCFG="airplanecontrol" command, and this command is under development.
2. The execution of AT+CFUN command will not affect GNSS function.
3.6. Power Supply
3.6.1. Power Supply Pins
EC25 provides four VBAT pins for connection with the external power supply. There are two separate
voltage domains for VBAT.
Two VBAT_RF pins for module’s RF part
Two VBAT_BB pins for module’s baseband part
The following table shows the details of VBAT pins and ground pins.
Table 6: VBAT and GND Pins
Pin Name Pin No. Description Min. Typ. Max. Unit
VBAT_RF 57, 58
VBAT_BB 59, 60
8, 9, 19, 22, 36,
GND
EC25_Hardware_Design 41 / 112
46, 48, 50~54,
56, 72, 85~112
Power supply for module’s RF
part
Power supply for module’s
baseband part
Ground - 0 - V
3.3 3.8 4.3 V
3.3 3.8 4.3 V
LTE Standard Module Series
EC25 Hardware Design
3.6.2. Decrease Voltage Drop
The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will
never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G
network. The voltage drop will be less in 3G and 4G networks.
Figure 7: Power Supply Limits during Burst Transmission
To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR=0.7Ω) should be used,
and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It
is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array,
and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an external
application has to be a single voltage source and can be expanded to two sub paths with star structure.
The width of VBAT_BB trace should be no less than 1mm; and the width of VBAT_RF trace should be no
less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to avoid the damage caused by electric surge and ESD, it is suggested that a TVS
diode with suggested low reverse stand-off voltage V
peak pulse current I
VB AT
should be used. The following figure shows the star structure of the power supply.
PP
4.5V, low clamping voltage VC and high reverse
RWM
VB AT_R F
VB AT_BB
D1
WS4.5D3HV
C1
100uF
+
C2
100nF
33pF
C3
C4
10pF
C5
100uF
+
C6
100nFC733pFC810pF
Module
Figure 8: Star Structure of the Power Supply
EC25_Hardware_Design 42 / 112
LTE Standard Module Series
EC25 Hardware Design
3.6.3. Reference Design for Power Supply
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply should be able to provide sufficient current up to 2A at least. If the
voltage drop between the input and output is not too high, it is suggested that an LDO should be used to
supply power for the module. If there is a big voltage difference between the input source and the desired
output (VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +5V input power source. The typical output of the power
supply is about 3.8V and the maximum load current is 3A.
Figure 9: Reference Circuit of Power Supply
NOTE
In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, then the power supply
can be cut off.
3.6.4. Monitor the Power Supply
AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to
document [2].
EC25_Hardware_Design 43 / 112
EC25 Hardware Design
3.7. Power-on and off Scenarios
3.7.1. Turn on Module Using the PWRKEY
The following table shows the pin definition of PWRKEY.
Table 7: Pin Definition of PWRKEY
Pin Name Pin No. I/O Description Comment
LTE Standard Module Series
PWRKEY 21 DI Turn on/off the module
The output voltage is 0.8V because of
the diode drop in the Qualcomm chipset.
When EC25 is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin to a
low level for at least 500ms. It is recommended to use an open drain/collector driver to control the
PWRKEY. After STATUS pin (require external pull-up) outputs a low level, PWRKEY pin can be released.
A simple reference circuit is illustrated in the following figure.
PWRKEY
≥ 500ms
4.7K
10nF
Turn-on pulse
47K
Figure 10: Turn on the Module by Using Driving Circuit
The other way to control the PWRKEY is using a button directly. When pressing the key, electrostatic
strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
EC25_Hardware_Design 44 / 112
EC25 Hardware Design
Figure 11: Turn on the Module by Using Keystroke
The power-on scenario is illustrated in the following figure.
LTE Standard Module Series
NOTE
VBA T
PWRKEY
VDD_EXT
BOOT_CONFIG &
USB_BOOT PINS
RESET_N
STAT US
(OD)
UART
≥500ms
VIL≤0.5V
About 100ms
≥100ms, after this tim e, the BOOT_CONFIG
pins can b e s et h igh level by exter nal circuit
≥2.5s
Inactive
V
H
≥12s
=0.8V
Act ive
≥13s
USB
Inactive
Act ive
Figure 12: Power-on Scenario of Module
EC25_Hardware_Design 45 / 112
LTE Standard Module Series
EC25 Hardware Design
NOTE
Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them should
be no less than 30ms.
3.7.2. Turn off Module
The following procedures can be used to turn off the module:
Normal power-off procedure: Turn off the module using the PWRKEY pin.
Normal power-off procedure: Turn off the module using AT+QPOWD command.
3.7.2.1. Turn off Module Using the PWRKEY Pin
Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-off
procedure after the PWRKEY is released. The power-off scenario is illustrated in the following figure.
VBAT
≥29.5s
Po w er-of f pro cedu r e
OFF
PWRKEY
STATUS
(OD)
Module
Status
≥
RUNNING
65 0ms
Figure 13: Power-off Scenario of Module
3.7.2.2. Turn off Module Using AT Command
It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the
module via PWRKEY pin.
Please refer to document [2] for details about AT+QPOWD command.
EC25_Hardware_Design 46 / 112
LTE Standard Module Series
EC25 Hardware Design
NOTES
1. In order to avoid damaging internal flash, please do not switch off the power supply when the module
works normally. Only after the module is shut down by PWRKEY or AT command, then the power
supply can be cut off.
2. When turning off module with AT command, please keep PWRKEY at high level after the execution of
power-off command. Otherwise the module will be turned on again after successfully turn-off.
3.8. Reset Module
The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a
low level voltage for time between 150ms and 460ms.
Table 8: Pin Definition of RESET_N
Pin Name Pin No. I/O Description Comment
RESET_N 20 DI Reset the module 1.8V power domain
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
Figure 14: Reference Circuit of RESET_N by Using Driving Circuit
EC25_Hardware_Design 47 / 112
EC25 Hardware Design
Figure 15: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated in the following figure.
LTE Standard Module Series
Figure 16: Reset Scenario of Module
NOTES
1. Use RESET_N only when failed to turn off the module by AT+QPOWD command and PWRKEY pin.
2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.
3.9. (U)SIM Interface
The(U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards
are supported.
EC25_Hardware_Design 48 / 112
LTE Standard Module Series
EC25 Hardware Design
Table 9: Pin Definition of (U)SIM Interface
Pin Name Pin No. I/O Description Comment
USIM_VDD 14 PO Power supply for (U)SIM card
Either 1.8V or 3.0V is supported
by the module automatically.
USIM_DATA 15 IO Data signal of (U)SIM card
USIM_CLK 16 DO Clock signal of (U)SIM card
USIM_RST 17 DO Reset signal of (U)SIM card
USIM_
PRESENCE
13 DI (U)SIM card insertion detection
1.8V power domain.
If unused, keep it open.
USIM_GND 10 Specified ground for (U)SIM card
EC25 supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and
high level detections, and is disabled by default. Please refer to document [2] for more details about
AT+QSIMDET command.
The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
Figure 17: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector
If (U)SIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A
reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following
figure.
EC25_Hardware_Design 49 / 112
LTE Standard Module Series
EC25 Hardware Design
Figure 18: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector
In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please
follow the criteria below in (U)SIM circuit design:
Keep placement of (U)SIM card connector to the module as close as possible. Keep the trace length
as less than 200mm as possible.
Keep (U)SIM card signals away from RF and VBAT traces.
Assure the ground between the module and the (U)SIM card connector short and wide. Keep the
trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.
Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as
close to (U)SIM card connector as possible. If the ground is complete on customers’ PCB,
USIM_GND can be connected to PCB ground directly.
To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic
capacitance should not be more than 15pF. The 0Ω resistors should be added in series between the
module and the (U)SIM card to facilitate debugging. The 33pF capacitors are used for filtering
interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to the
(U)SIM card connector.
The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.
3.10. USB Interface
EC25 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0
specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is
EC25_Hardware_Design 50 / 112
LTE Standard Module Series
EC25 Hardware Design
used for AT command communication, data transmission, GNSS NMEA sentences output, software
debugging, firmware upgrade and voice over USB. The following table shows the pin definition of USB
interface.
Table 10: Pin Description of USB Interface
Pin Name Pin No. I/O Description Comment
USB_DP 69 IO USB differential data bus (+)
USB_DM 70 IO USB differential data bus (-)
USB_VBUS 71 PI
USB power supply,
used for USB detection
Require differential
impedance of 90Ω
Require differential
impedance of 90Ω
Typical 5.0V
GND 72 Ground
For more details about the USB 2.0 specifications, please visit http://www.usb.org/home
.
The USB interface is recommended to be reserved for firmware upgrade in customers’ designs. The
following figure shows a reference circuit of USB interface.
Figure 19: Reference Circuit of USB Application
A common mode choke L1 is recommended to be added in series between the module and customer’s
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
EC25_Hardware_Design 51 / 112
LTE Standard Module Series
EC25 Hardware Design
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer with ground shielding on not only upper
and lower layers but also right and left sides.
Pay attention to the influence of junction capacitance of ESD protection components on USB data
lines. Typically, the capacitance value should be less than 2pF.
Keep the ESD protection components to the USB connector as close as possible.
NOTES
1. EC25 module can only be used as a slave device.
2. “*” means under development.
3.11. UART Interfaces
The module provides two UART interfaces: the main UART interface and the debug UART interface. The
230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. The interface is
used for data transmission and AT command communication.
The debug UART interface supports 115200bps baud rate. It is used for Linux console and log
output.
The following tables show the pin definition of the UART interfaces.
Table 11: Pin Definition of Main UART Interface
Pin Name Pin No. I/O Description Comment
RI 62 DO Ring indicator
DCD 63 DO Data carrier detection
1.8V power domain
CTS 64 DO Clear to send
RTS 65 DI Request to send
EC25_Hardware_Design 52 / 112
LTE Standard Module Series
EC25 Hardware Design
DTR 66 DI
Data terminal ready,
sleep mode control
TXD 67 DO Transmit data
RXD 68 DI Receive data
Table 12: Pin Definition of Debug UART Interface
Pin Name Pin No. I/O Description Comment
DBG_TXD 12 DO Transmit data
1.8V power domain
DBG_RXD 11 DI Receive data
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter Min. Max. Unit
VIL -0.3 0.6 V
VIH 1.2 2.0 V
VOL 0 0.45 V
VOH 1.35 1.8 V
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design.
EC25_Hardware_Design 53 / 112
LTE Standard Module Series
EC25 Hardware Design
VDD_EXT
RI
DCD
CTS
RTS
DTR
TXD
RXD
0.1uF
120K
51K
VCCAVCCB
10K
OE
A1
A2
Translator
A3
A4
A5
A6
A7
A8
GND
B1
B2
B3
B4
B5
B6
B7
B8
0.1uF
51K
VDD_MCU
RI_MCU
DCD_MCU
CTS_MCU
RTS_MCU
DTR_MCU
TXD_MCU
RXD_MCU
Figure 20: Reference Circuit with Translator Chip
Please visit http://www.ti.com
for more information.
Another example with transistor translation circuit is shown as below. The circuit design of dotted line
section can refer to the design of solid line section, in terms of both module’s input and output circuit
designs, but please pay attention to the direction of connection.
Figure 21: Reference Circuit with Transistor Circuit
NOTE
Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.
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LTE Standard Module Series
EC25 Hardware Design
3.12. PCM and I2C Interfaces
EC25 provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the
following modes and one I2C interface:
Primary mode (short frame synchronization, works as both master and slave)
Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256KHz, 512KHz, 1024KHz or 2048KHz PCM_CLK at 8KHz PCM_SYNC, and also supports 4096KHz
PCM_CLK at 16KHz PCM_SYNC.
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256KHz, 512KHz, 1024KHz or 2048KHz PCM_CLK and an 8KHz, 50% duty cycle PCM_SYNC.
EC25 supports 16-bit linear data format. The following figures show the primary mode’s timing
relationship with 8KHz PCM_SYNC and 2048KHz PCM_CLK, as well as the auxiliary mode’s timing
relationship with 8KHz PCM_SYNC and 256KHz PCM_CLK.
Figure 22: Primary Mode Timing
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Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name Pin No. I/O Description Comment
PCM_IN 24 DI PCM data input 1.8V power domain
PCM_OUT 25 DO PCM data output 1.8V power domain
PCM_SYNC 26 IO
PCM data frame
synchronization signal
1.8V power domain
PCM_CLK 27 IO PCM data bit clock 1.8V power domain
I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V
I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] for more details about AT+QDAI command.
The following figure shows a reference design of PCM interface with external codec IC.
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Figure 24: Reference Circuit of PCM Application with Audio Codec
NOTES
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuits on the PCM lines, especially for
PCM_CLK.
2. EC25 works as a master device pertaining to I2C interface.
3.13. SD Card Interface
EC25 supports SDIO 3.0 interface for SD card.
The following table shows the pin definition of SD card interface.
Table 15: Pin Definition of SD Card Interface
Pin Name Pin No. I/O Description Comment
SDC2_DATA3 28 IO SD card SDIO bus DATA3
SDIO signal level can be
SDC2_DATA2 29 IO SD card SDIO bus DATA2
SDC2_DATA1 30 IO SD card SDIO bus DATA1
SDC2_DATA0 31 IO SD card SDIO bus DATA0
selected according to SD
card supported level,
please refer to SD 3.0
protocol for more details.
If unused, keep it open.
SDC2_CLK 32 DO SD card SDIO bus clock
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SDC2_CMD 33 IO SD card SDIO bus command
VDD_SDIO 34 PO SD card SDIO bus pull up power
LTE Standard Module Series
1.8V/2.85V configurable.
Cannot be used for SD
card power. If unused,
keep it open.
SD_INS_DET 23 DI SD card insertion detection
The following figure shows a reference design of SD card.
Figure 25: Reference Circuit of SD Card Interface
1.8V power domain.
If unused, keep it open.
In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:
SD_INS_DET must be connected.
The voltage range of SD card power supply VDD_3V is 2.7V~3.6V and a sufficient current up to 0.8A
should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used
for SDIO pull-up resistors, an externally power supply is needed for SD card.
To avoid jitter of bus, resistors R7~R11 are needed to pull up the SDIO to VDD_SDIO. Value of these
resistors is among 10KΩ~100KΩ and the recommended value is 100KΩ. VDD_SDIO should be used
as the pull-up power.
In order to adjust signal quality, it is recommended to add 0Ω resistors R1~R6 in series between the
module and the SD card. The bypass capacitors C1~C6 are reserved and not mounted by default. All
resistors and bypass capacitors should be placed close to the module.
In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins near
the SD card connector with junction capacitance less than 15pF.
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
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It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data trace
is 50Ω (±10%).
Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 15pF.
It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 27mm, so the
exterior total trace length should be less than 23mm.
3.14. ADC Interfaces
The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 command can be
used to read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage
value on ADC1 pin. For more details about these AT commands, please refer to document [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
Table 16: Pin Definition of ADC Interfaces
Pin Name Pin No. Description
ADC0 45 General purpose analog to digital converter
ADC1 44 General purpose analog to digital converter
The following table describes the characteristic of ADC function.
Table 17: Characteristic of ADC
Parameter Min. Typ. Max. Unit
ADC0 Voltage Range 0.3 VBAT_BB V
ADC1 Voltage Range 0.3 VBAT_BB V
ADC Resolution 15 bits
NOTES
1. ADC input voltage must not exceed VBAT_BB.
2. It is prohibited to supply any voltage to ADC pins when VBAT is removed.
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3. It is recommended to use a resistor divider circuit for ADC application.
3.15. Network Status Indication
The network indication pins can be used to drive network status indication LEDs. The module provides
two pins which are NET_MODE and NET_STATUS. The following tables describe the pin definition and
logic level changes in different network status.
Table 18: Pin Definition of Network Connection Status/Activity Indicator
Pin Name Pin No. I/O Description Comment
1.8V power domain
Cannot be pulled up
before startup
1.8V power domain
NET_MODE 5 DO
NET_STATUS 6 DO
Indicate the module’s network
registration mode
Indicate the module’s network activity
status
Table 19: Working State of Network Connection Status/Activity Indicator