Quectel Wireless Solutions 201808EC25AF Users Manual

EC25 Hardware Design

LTE Module Series

Rev. EC25_Hardware_Design_V1.5

Date: 2018-04-20

Status: Released

www.quectel.com

LTE Module Series

EC25 Hardware Design

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EC25 Hardware Design

About the Document

History

Revision Date Author Description

1.0 2016-04-01 Woody WU Initial

LTE Module Series

1.1 2016-09-22

1.2 2016-11-04

Lyndon LIU/

Frank WANG

Lyndon LIU/

Michael ZHANG

1. Updated EC25 series frequency bands in Table 1.

2. Updated transmitting power, supported maximum

baud rate of main UART/internal protocols/USB

drivers of USB interface, firmware upgrade and

temperature range in Table 2.

3. Updated timing of turning on module in Figure 12.

4. Updated timing of turning off module in Figure 13.

5. Updated timing of resetting module in Figure 16.

6. Updated supported baud rates of main UART in

Chapter 3.11.

7. Added notes for ADC interface in Chapter 3.13.

8. Updated GNSS performance in Table 21.

9. Updated operating frequencies of module in Table 23.

10. Added current consumption in Chapter 6.4.

11. Updated RF output power in Chapter 6.5.

12. Added RF receiving sensitivity in Chapter 6.6.

1. Added SGMII and WLAN interfaces in Table 2.

2. Updated function diagram in Figure 1.

3. Updated pin assignment (Top View) in Figure 2.

4. Added description of SGMII and WLAN interfaces in

Table 4.

5. Added SGMII interface in Chapter 3.17.

6. Added WLAN interface in Chapter 3.18.

7. Added USB_BOOT interface in Chapter 3.19.

8. Added reference design of RF layout in Chapter 5.1.4.

9. Added note about SIMO in Chapter 6.6.

1.3 2017-01-24

EC25_Hardware_Design 2 / 112

Lyndon LIU/

Frank WANG

1. Updated function diagram in Figure 1.

2. Updated pin assignment (top view) in Figure 2.

EC25 Hardware Design

AnniceZHANG/

1.4 2018-03-05

Lyndon LIU/

Frank WANG

LTE Module Series

3. Added BT interface in Chapter 3.18.2.

4. Updated GNSS performance in Table 24.

5. Updated reference circuit of wireless connectivity

interfaces with FC20 module in Figure 29.

6. Updated current consumption of EC25-E module in

Table 33.

7. Updated EC25-A conducted RF receiving sensitivity

in Table 38.

8. AddedEC25-J conducted RF receiving sensitivity in

Table 40.

1. Updated functional diagram in Figure 1.

2. Updated frequency bands in Table 1.

3. Updated LTE, UMTS and GSM features in Table 2.

4. Updated description of pin 40/136/137/138.

5. Updated PWRKEY pulled down time to 500ms in

Chapter 3.7.1 and reference circuit in Figure 10.

6. Updated reference circuit of (U)SIM interface in

Figure 17&18.

7. Updated reference circuit of USB interface in Figure

19.

8. Updated PCM mode in Chapter 3.12.

9. Added SD card interface in Chapter 3.13.

10. Updated USB_BOOT reference circuit in Chapter

3.20.

11. Updated module operating frequencies in Table 26.

12. Updated antenna requirements in Table 30.

13. Updated EC25 series module current consumption in

Chapter 6.4.

14. Updated EC25 series module conducted RF receiving

sensitivity in Chapter 6.6.

15. Added thermal consideration description in Chapter

6.8.

16. Added dimension tolerance information in Chapter 7.

17. Added storage temperature range in Table 2 and

Chapter 6.3.

18. Updated RF output power in Table 41.

19. Updated GPRS multi-slot classes in Table 53.

20. Updated storage information in Chapter 8.1.

1. Added information of EC25-AF in Table 1.

2. Updated module operating frequencies in Table 27.

1.5 2018-04-20 Kinsey ZHANG

3. Added current consumption of EC25-AF module in

Table 40.

4. Changed GNSS current consumption of EC25 series

module into Table 41.

EC25_Hardware_Design 3 / 112

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EC25 Hardware Design

5. Added EC25-AF conducted RF receiving sensitivity in

Table 50.

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EC25 Hardware Design

Contents

About the Document ................................................................................................................................ 2

Contents .................................................................................................................................................... 5

Table Index ............................................................................................................................................... 8

Figure Index ............................................................................................................................................ 10

1 Introduction ..................................................................................................................................... 12

1.1. Safety Information ................................................................................................................. 13

2 Product Concept ............................................................................................................................. 14

2.1. General Description .............................................................................................................. 14

2.2. Key Features ......................................................................................................................... 15

2.3. Functional Diagram ............................................................................................................... 18

2.4. Evaluation Board ................................................................................................................... 19

3 Application Interfaces ..................................................................................................................... 20

3.1. General Description .............................................................................................................. 20

3.2. Pin Assignment ..................................................................................................................... 21

3.3. Pin Description ...................................................................................................................... 22

3.4. Operating Modes .................................................................................................................. 34

3.5. Power Saving ........................................................................................................................ 34

3.5.1.

Sleep Mode.................................................................................................................. 34

3.5.1.1. UART Application .............................................................................................. 34

3.5.1.2. USB Application with USB Remote Wakeup Function ....................................... 35

3.5.1.3. USB Application with USB Suspend/Resume and RI Function.......................... 36

3.5.1.4. USB Application without USB Suspend Function .............................................. 37

3.5.2. Airplane Mode .............................................................................................................. 37

3.6. Power Supply ........................................................................................................................ 38

3.6.1. Power Supply Pins ....................................................................................................... 38

3.6.2. Decrease Voltage Drop ............................................................................................... 39

3.6.3. Reference Design for Power Supply ............................................................................ 40

3.6.4. Monitor the Power Supply ............................................................................................ 40

3.7. Turn on and off Scenarios ..................................................................................................... 40

3.7.1. Turn on Module Using the PWRKEY ........................................................................... 40

3.7.2. Turn off Module ............................................................................................................ 42

3.7.2.1. Turn off Module Using the PWRKEY Pin ........................................................... 42

3.7.2.2. Turn off Module Using AT Command ................................................................ 43

3.8. Reset the Module .................................................................................................................. 43

3.9.

(U)SIM Interface .................................................................................................................... 45

3.10. USB Interface ........................................................................................................................ 47

3.11. UART Interfaces ................................................................................................................... 49

3.12. PCM and I2C Interfaces ........................................................................................................ 51

3.13. SD Card Interface ................................................................................................................. 54

3.14. ADC Interfaces ...................................................................................................................... 56

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3.15. Network Status Indication ..................................................................................................... 57

3.16. STATUS ................................................................................................................................ 58

3.17. Behaviors of RI ..................................................................................................................... 59

3.18. SGMII Interface ..................................................................................................................... 60

3.19. Wireless Connectivity Interfaces ........................................................................................... 62

3.19.1. WLAN Interface ........................................................................................................... 64

3.19.2. BT Interface* ................................................................................................................ 64

3.20. USB_BOOT Interface............................................................................................................ 65

4 GNSS Receiver ................................................................................................................................ 66

4.1. General Description .............................................................................................................. 66

4.2. GNSS Performance .............................................................................................................. 66

4.3. Layout Guidelines ................................................................................................................. 67

5 Antenna Interfaces .......................................................................................................................... 68

5.1. Main/Rx-diversity Antenna Interfaces.................................................................................... 68

5.1.1. Pin Definition ................................................................................................................ 68

5.1.2. Operating Frequency ................................................................................................... 68

5.1.3. Reference Design of RF Antenna Interface ................................................................. 70

5.1.4. Reference Design of RF Layout ................................................................................... 70

5.2. GNSS Antenna Interface ....................................................................................................... 72

5.3. Antenna Installation .............................................................................................................. 74

5.3.1. Antenna Requirement .................................................................................................. 74

5.3.2. Recommended RF Connector for Antenna Installation ................................................ 75

6 Electrical, Reliability and Radio Characteristics .......................................................................... 77

6.1. Absolute Maximum Ratings .................................................................................................. 77

6.2. Power Supply Ratings ........................................................................................................... 78

6.3. Operation and Storage Temperatures .................................................................................. 78

6.4. Current Consumption ............................................................................................................ 79

6.5. RF Output Power .................................................................................................................. 90

6.6. RF Receiving Sensitivity ....................................................................................................... 91

6.7. Electrostatic Discharge ......................................................................................................... 95

6.8. Thermal Consideration .......................................................................................................... 95

7 Mechanical Dimensions.................................................................................................................. 98

7.1. Mechanical Dimensions of the the Module ............................................................................ 98

7.2.

Recommended Footprint ..................................................................................................... 100

7.3. Design Effect Drawings of the Module ................................................................................ 101

8 Storage, Manufacturing and Packaging ...................................................................................... 102

8.1. Storage ............................................................................................................................... 102

8.2. Manufacturing and Soldering .............................................................................................. 103

8.3. Packaging ........................................................................................................................... 104

9 Appendix A References ................................................................................................................ 105

10 Appendix B GPRS Coding Schemes ........................................................................................... 109

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11 Appendix C GPRS Multi-slot Classes .......................................................................................... 110

12 Appendix D EDGE Modulationand Coding Schemes ................................................................. 112

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Table Index

TABLE 1: FREQUENCY BANDS OF EC25 SERIES MODULE ....................................................................... 14

TABLE 2: KEY FEATURES OF EC25 MODULE .............................................................................................. 15

TABLE 3: I/O PARAMETERS DEFINITION ...................................................................................................... 22

TABLE 4: PIN DESCRIPTION ........................................................................................................................... 22

TABLE 5: OVERVIEW OF OPERATING MODES ............................................................................................ 34

TABLE 6: VBAT AND GND PINS ...................................................................................................................... 38

TABLE 7: PIN DEFINITION OF PWRKEY ........................................................................................................ 41

TABLE 8: RESET_N PIN DESCRIPTION ......................................................................................................... 43

TABLE 9: PIN DEFINITION OF THE (U)SIM INTERFACE ............................................................................... 45

TABLE 10: PIN DESCRIPTION OF USB INTERFACE ..................................................................................... 47

TABLE 11: PIN DEFINITION OF MAIN UART INTERFACE ............................................................................ 49

TABLE 12: PIN DEFINITION OF DEBUG UART INTERFACE......................................................................... 49

TABLE 13: LOGIC LEVELS OF DIGITAL I/O ................................................................................................... 50

TABLE 14: PIN DEFINITION OF PCM AND I2C INTERFACES ...................................................................... 52

TABLE 15: PIN DEFINITION OF SD CARD INTERFACE ................................................................................ 54

TABLE 16: PIN DEFINITION OF ADC INTERFACES ...................................................................................... 56

TABLE 17: CHARACTERISTIC OF ADC .......................................................................................................... 56

TABLE 18: PIN DEFINITION OF NETWORK CONNECTION STATUS/ACTIVITY INDICATOR .................... 57

TABLE 19: WORKING STATE OF THE NETWORK CONNECTION STATUS/ACTIVITY INDICATOR ......... 57

TABLE 20: PIN DEFINITION OF STATUS ....................................................................................................... 58

TABLE 21: BEHAVIOR OF RI ........................................................................................................................... 59

TABLE 22: PIN DEFINITION OF THE SGMII INTERFACE .............................................................................. 60

TABLE 23: PIN DEFINITION OF WIRELESS CONNECTIVITY INTERFACES ............................................... 62

TABLE 24: PIN DEFINITION OF USB_BOOT INTERFACE............................................................................. 65

TABLE 25: GNSS PERFORMANCE ................................................................................................................. 66

TABLE 26: PIN DEFINITION OF RF ANTENNA ............................................................................................... 68

TABLE 27: MODULE OPERATING FREQUENCIES ....................................................................................... 68

TABLE 28: PIN DEFINITION OF GNSS ANTENNA INTERFACE .................................................................... 72

TABLE 29: GNSS FREQUENCY ...................................................................................................................... 73

TABLE 30: ANTENNA REQUIREMENTS ......................................................................................................... 74

TABLE 31: ABSOLUTE MAXIMUM RATINGS ................................................................................................. 77

TABLE 32: THE MODULE POWER SUPPLY RATINGS .................................................................................. 78

TABLE 33: OPERATION AND STORAGE TEMPERATURES ......................................................................... 78

TABLE 34: EC25-E CURRENT CONSUMPTION ............................................................................................. 79

TABLE 35: EC25-A CURRENT CONSUMPTION ............................................................................................. 81

TABLE 36: EC25-V CURRENT CONSUMPTION ............................................................................................. 82

TABLE 37: EC25-J CURRENT CONSUMPTION ............................................................................................. 83

TABLE 38: EC25-AU CURRENT CONSUMPTION .......................................................................................... 84

TABLE 39: EC25-AUT CURRENT CONSUMPTION ........................................................................................ 87

TABLE 40: EC25-AF CURRENT CONSUMPTION ........................................................................................... 88

TABLE 41: GNSS CURRENT CONSUMPTION OF EC25 SERIES MODULE ................................................ 90

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EC25 Hardware Design

TABLE 42: RF OUTPUT POWER ..................................................................................................................... 90

TABLE 43: EC25-E CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 91

TABLE 44: EC25-A CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 91

TABLE 45: EC25-V CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 92

TABLE 46: EC25-J CONDUCTED RF RECEIVING SENSITIVITY .................................................................. 92

TABLE 47: EC25-AU CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 93

TABLE 48: EC25-AUT CONDUCTED RF RECEIVING SENSITIVITY ............................................................. 93

TABLE 49: EC25-AUTL CONDUCTED RF RECEIVING SENSITIVITY ........................................................... 94

TABLE 50: EC25-AF CONDUCTED RF RECEIVING SENSITIVITY ............................................................... 94

TABLE 51: ELECTROSTATICS DISCHARGE CHARACTERISTICS .............................................................. 95

TABLE 52: RELATED DOCUMENTS ............................................................................................................. 105

TABLE 53: TERMS AND ABBREVIATIONS ................................................................................................... 105

TABLE 54: DESCRIPTION OF DIFFERENT CODING SCHEMES ................................................................ 109

TABLE 55: GPRS MULTI-SLOT CLASSES .................................................................................................... 110

TABLE 56: EDGE MODULATION AND CODING SCHEMES ........................................................................ 112

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Figure Index

FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 19

FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 21

FIGURE 3: SLEEP MODE APPLICATION VIA UART ...................................................................................... 35

FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 36

FIGURE 5: SLEEP MODE APPLICATION WITH RI ......................................................................................... 36

FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION ................................................ 37

FIGURE 7: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ..................................................... 39

FIGURE 8: STAR STRUCTURE OF THE POWER SUPPLY ........................................................................... 39

FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 40

FIGURE 10: TURN ON THE MODULE BY USING DRIVING CIRCUIT ........................................................... 41

FIGURE 11: TURN ON THE MODULE BY USING BUTTON ........................................................................... 41

FIGURE 12: TIMING OF TURNING ON MODULE ........................................................................................... 42

FIGURE 13: TIMING OF TURNING OFF MODULE ......................................................................................... 43

FIGURE 14: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 44

FIGURE 15: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 44

FIGURE 16: TIMING OF RESETTING MODULE ............................................................................................. 44

FIGURE 17: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR

................................................................................................................................................................... 46

FIGURE 18: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR 46

FIGURE 19: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 48

FIGURE 20: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 50

FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 51

FIGURE 22: PRIMARY MODE TIMING ............................................................................................................ 52

FIGURE 23: AUXILIARY MODE TIMING .......................................................................................................... 52

FIGURE 24: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC ................................... 53

FIGURE 25: REFERENCE CIRCUIT OF SD CARD ......................................................................................... 55

FIGURE 26: REFERENCE CIRCUIT OF THE NETWORK INDICATOR ......................................................... 58

FIGURE 27: REFERENCE CIRCUITS OF STATUS ........................................................................................ 59

FIGURE 28: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION ............................................. 61

FIGURE 29: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY AR8033 APPLICATION ................ 61

FIGURE 30: REFERENCE CIRCUIT OF WIRELESS CONNECTIVITY INTERFACES WITH FC20 MODULE

................................................................................................................................................................... 63

FIGURE 31: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 65

FIGURE 32: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................ 70

FIGURE 33: MICROSTRIP LINE DESIGN ON A 2-LAYER PCB ..................................................................... 71

FIGURE 34: COPLANAR WAVEGUIDE LINE DESIGN ON A 2-LAYER PCB ................................................. 71

FIGURE 35: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE

GROUND) .................................................................................................................................................. 71

FIGURE 36: COPLANAR WAVEGUIDE LINE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE

GROUND) .................................................................................................................................................. 72

FIGURE 37: REFERENCE CIRCUIT OF GNSS ANTENNA ............................................................................. 73

EC25_Hardware_Design 10 / 112

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FIGURE 38: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) ............................................... 75

FIGURE 39: MECHANICALS OF U.FL-LP CONNECTORS ............................................................................. 75

FIGURE 40: SPACE FACTOR OF MATED CONNECTOR (UNIT: MM) .......................................................... 76

FIGURE 41: REFERENCED HEATSINK DESIGN (HEATSINK AT THE TOP OF THE MODULE) ................. 96

FIGURE 42: REFERENCED HEATSINK DESIGN (HEATSINK AT THE BACKSIDE OF CUSTOMERS’ PCB)

................................................................................................................................................................... 96

FIGURE 43: MODULE TOP AND SIDE DIMENSIONS .................................................................................... 98

FIGURE 44: MODULE BOTTOM DIMENSIONS (BOTTOM VIEW) ................................................................. 99

FIGURE 45: RECOMMENDED FOOTPRINT (TOP VIEW) ............................................................................ 100

FIGURE 46: TOP VIEW OF THE MODULE .................................................................................................... 101

FIGURE 47: BOTTOM VIEW OF THE MODULE ............................................................................................ 101

FIGURE 48: REFLOW SOLDERING THERMAL PROFILE ............................................................................ 103

FIGURE 49: TAPE AND REEL SPECIFICATIONS ........................................................................................ 104

EC25_Hardware_Design 11 / 112

LTE Module Series

EC25 Hardware Design

1 Introduction

This document defines the EC25 module and describes its air interface and hardware interface which are

connected with customers’ applications.

This document can help customers quickly understand module interface specifications, electrical and

mechanical details, as well as other related information of EC25 module. Associated with application note

and user guide, customers can use EC25 module to design and set up mobile applications easily.

EC25_Hardware_Design 12 / 112

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1.1. Safety Information

The following safety precautions must be observed during all phases of the operation, such as usage,

service or repair of any cellular terminal or mobile incorporating EC25 module. Manufacturers of the cellular

terminal should send the following safety information to users and operating personnel, and incorporate

these guidelines into all manuals supplied with the product. If not so, Quectel assumes no liability for the

customers’ failure to comply with these precautions.

Full attention must be given to driving at all times in order to reduce the risk of an

accident. Using a mobile while driving (even with a hands free kit) causes

distraction and can lead to an accident. You must comply with laws and regulations

restricting the use of wireless devices while driving.

Switch off the cellular terminal or mobile before boarding an aircraft. Make sure it is

switched off. The operation of wireless appliances in an aircraft is forbidden, so as

to prevent interference with communication systems. Consult the airline staff about

the use of wireless devices on boarding the aircraft, if your device offers an

Airplane Mode which must be enabled prior to boarding an aircraft.

Switch off your wireless device when in hospitals,clinics or other health care

facilities. These requests are designed to prevent possible interference with

sensitive medical equipment.

Cellular terminals or mobiles operating over radio frequency signal and cellular

network cannot be guaranteed to connect in all conditions, for example no mobile

fee or with an invalid (U)SIM card. While you are in this condition and need

emergent help, please remember using emergency call. In order to make or

receive a call, the cellular terminal or mobile must be switched on and in a service

area with adequate cellular signal strength.

Your cellular terminal or mobile contains a transmitter and receiver. When it is ON,

it receives and transmits radio frequency energy. RF interference can occur if it is

used close to TV set, radio, computer or other electric equipment.

In locations with potentially explosive atmospheres, obey all posted signs to turn

off wireless devices such as your phone or other cellular terminals. Areas with

potentially explosive atmospheres include fuelling areas, below decks on boats,

fuel or chemical transfer or storage facilities, areas where the air contains

chemicals or particles such as grain, dust or metal powders, etc.

EC25_Hardware_Design 13 / 112

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2 Product Concept

2.1. General Description

EC25 is a series of LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication module with receive

diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA,

WCDMA, EDGE and GPRS networks. It also provides GNSS

specific application. EC25 contains seven variants: EC25-E, EC25-A, EC25-V, EC25-J, EC25-AU,

EC25-AUT, EC25-AF and EC25-AUTL. Customers can choose a dedicated type based on the region or

operator. The following table shows the frequency bands of EC25 series module.

1)

and voice functionality2) for customers’

Table 1: Frequency Bands of EC25 Series Module

Modules2) LTE Bands

EC25-E

EC25-A

EC25-V

EC25-J

EC25-AU3)

EC25-AUT

EC25-AF

FDD: B1/B3/B5/B7/B8/B20

TDD: B38/B40/B41

FDD: B2/B4/B12 B2/B4/B5 N Y

FDD: B4/B13 N N Y

FDD: B1/B3/B8/B18/B19/

B26

TDD: B41

FDD: B1/B2/B3/B4/B5/B7/

B8/B28

TDD: B40

FDD: B1/B3//B5/B7/B28 B1/B5 N Y

FDD: B2/B4//B5/B12/B13/

B14/B66/B71

WCDMA Bands

B1/B5/B8 900/1800MHz Y

B1/B6/B8/B19 N Y

B1/B2/B5/B8

B2/B4/B5 N Y

GSM Bands

850/900/

1800/1900MHz

Rxdiversity

Y

GNSS1)

GPS,

GLONASS,

BeiDou/

Compass,

Galileo,

QZSS

EC25-AUTL

EC25_Hardware_Design 14 / 112

FDD: B3/B7/B28 N N Y N

LTE Module Series

EC25 Hardware Design

NOTES

1)

1.

GNSS function is optional.

2)

2.

EC25 series module (EC25-E/EC25-A/EC25-V/EC25-J/EC25-AU/EC25-AUT/EC25-AF/

EC25-AUTL) contains Telematics version and Data-only version. Telematics version supports voice and data functions, while Data-only version only supports data function.

3)

3.

B2 band on EC25-AU module does not support Rx-diversity.

4. Y = Supported. N = Not supported.

With a compact profile of 29.0mm × 32.0mm × 2.4mm, EC25 can meet almost all requirements for M2M

applications such as automotive, metering, tracking system, security, router, wireless POS, mobile

computing device, PDA phone, tablet PC, etc.

EC25 is an SMD type module which can be embedded into applications through its 144-pin pads,

including 80 LCC signal pads and 64 LGA pads.

2.2. Key Features

The following table describes the detailed features of EC25 module.

Table 2: Key Features of EC25 Module

Feature Details

Power Supply

Transmitting Power

Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V

Class 4 (33dBm±2dB) for GSM850

Class 4 (33dBm±2dB) for EGSM900

Class 1 (30dBm±2dB) for DCS1800

Class 1 (30dBm±2dB) for PCS1900

Class E2 (27dBm±3dB) for GSM850 8-PSK

Class E2 (27dBm±3dB) for EGSM900 8-PSK

Class E2 (26dBm±3dB) for DCS1800 8-PSK

Class E2 (26dBm±3dB) for PCS1900 8-PSK

Class 3 (24dBm+1/-3dB) for WCDMA bands

Class 3 (23dBm±2dB) for LTE-FDD bands

Class 3 (23dBm±2dB) for LTE-TDD bands

Support up to non-CA Cat 4 FDD and TDD

LTE Features

Support 1.4MHz~20MHz RF bandwidth

Support MIMO in DL direction

LTE-FDD: Max 150Mbps (DL)/50Mbps (UL)

EC25_Hardware_Design 15 / 112

UMTS Features

GSM Features

LTE Module Series

EC25 Hardware Design

LTE-TDD: Max 130Mbps (DL)/30Mbps (UL)

Support 3GPP R8 DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA

Support QPSK, 16-QAM and 64-QAM modulation

DC-HSDPA: Max 42Mbps (DL)

HSUPA: Max 5.76Mbps (UL)

WCDMA: Max 384Kbps (DL)/384Kbps (UL)

GPRS:

Support GPRS multi-slot class 33 (33 by default)

Coding scheme: CS-1, CS-2, CS-3 and CS-4

Max 107Kbps (DL)/85.6Kbps (UL)

EDGE:

Support EDGE multi-slot class 33 (33 by default)

Support GMSK and 8-PSK for different MCS (Modulation and Coding

Scheme)

Downlink coding schemes: CS 1-4 and MCS 1-9

Uplink coding schemes: CS 1-4 and MCS 1-9

Max 296Kbps (DL)/236.8Kbps (UL)

Support

TCP/UDP/PPP/FTP/HTTP/NTP/PING/QMI/CMUX*/HTTPS*/SMTP*/

Internet Protocol Features

MMS*/FTPS*/SMTPS*/SSL*/FILE* protocols

Support PAP (Password Authentication Protocol) and CHAP (Challenge

Handshake Authentication Protocol) protocols which are usually used for

PPP connections

Text and PDU mode

SMS

Point to point MO and MT

SMS cell broadcast

SMS storage: ME by default

(U)SIM Interface Support USIM/SIM card: 1.8V, 3.0V

Support one digital audio interface: PCM interface

GSM: HR/FR/EFR/AMR/AMR-WB

Audio Features

WCDMA: AMR/AMR-WB

LTE: AMR/AMR-WB

Support echo cancellation and noise suppression

Used for audio function with external codec

Support 16-bit linear data format

PCM Interface

Support long frame synchronization and short frame synchronization

Support master and slave modes, but must be the master in long frame

synchronization

Compliant with USB 2.0 specification (slave only); the data transfer rate can

USB Interface

reach up to 480Mbps

Used for AT command communication, data transmission, GNSS NMEA

output, software debugging, firmware upgrade and voice over USB*

EC25_Hardware_Design 16 / 112

EC25 Hardware Design

Support USB serial drivers for: Windows 7/8/8.1/10,

Windows CE 5.0/6.0/7.0*, Linux 2.6/3.x/4.1~4.14, Android 4.x/5.x/6.x/7.x

Main UART:

Used for AT command communication and data transmission

Baud rates reach up to 921600bps, 115200bps by default

UART Interface

Support RTS and CTS hardware flow control

Debug UART:

Used for Linux console and log output

115200bps baud rate

SD Card Interface Support SD 3.0 protocol

LTE Module Series

SGMII Interface

Wireless Connectivity

Interfaces

Support 10M/100M/1000M Ethernet work mode

Support maximum 150Mbps (DL)/50Mbps (UL) for 4G network

Support a low-power SDIO 3.0 interface for WLAN and UART/PCM

interface for Bluetooth*

Rx-diversity Support LTE/WCDMA Rx-diversity

GNSS Features

AT Commands

Network Indication

Antenna Interfaces

Physical Characteristics

Gen8C Lite of Qualcomm

Protocol: NMEA 0183

Compliant with 3GPP TS 27.007, 27.005 and Quectel enhanced AT

commands

Two pins including NET_MODE and NET_STATUS to indicate network

connectivity status

Including main antenna interface (ANT_MAIN), Rx-diversity antenna

interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS)

Size: (29.0±0.15)mm × (32.0±0.15)mm × (2.4±0.2)mm

Weight: approx. 4.9g

Operation temperature range: -35°C ~ +75°C

Temperature Range

Extended temperature range: -40°C ~ +85°C

Storage temperature range: -40°C~ +90°C

1)

2)

Firmware Upgrade USB interface and DFOTA*

RoHS All hardware components are fully compliant with EU RoHS directive

NOTES

1)

1.

Within operation temperature range, the module is 3GPP compliant.

2)

2.

Within extended temperature range, the module remains the ability to establish and maintain a

voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There

are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like

P

might reduce in their value and exceed the specified tolerances. When the temperature returns to

out

the normal operating temperature levels, the module will meet 3GPP specifications again.

3. “*” means under development.

EC25_Hardware_Design 17 / 112

LTE Module Series

EC25 Hardware Design

2.3. Functional Diagram

The following figure shows a block diagram of EC25 and illustrates the major functional parts.

 Power management

 Baseband

 DDR+NAND flash

 Radio frequency

 Peripheral interfaces

EC25_Hardware_Design 18 / 112

LTE Module Series

EC25 Hardware Design

ANT_MAIN ANT_DIVANT_GNSS

VBAT_RF

VBAT_BB

PWRKEY

RESET_N

ADCs

STATUS

APT

PMIC

VDD_EXT

Tx

Control

19.2 M

PAM

Duplex

PA

PRx DRx

Transceiver

IQ Cont rol

XO

USB USIM PCM UARTsI2C

SAW

LNA

Switch

SAW

SDRAM

Baseband

SGMII

NAND DDR2

WLAN SDBT*

GPIOs

Figure 1: Functional Diagram

NOTE

“*” means under development.

2.4. Evaluation Board

In order to help customers develop applications with EC25, Quectel supplies an evaluation board (EVB),

USB to RS-232 converter cable, earphone, antenna and other peripherals to control or test the module.

EC25_Hardware_Design 19 / 112

LTE Module Series

EC25 Hardware Design

3 Application Interfaces

3.1. General Description

EC25 is equipped with 80 LCC pads plus 64 LGA pads that can be connected to cellular application

platform. Sub-interfaces included in these pads are described in detail in the following chapters:

 Power supply

 (U)SIM interface

 USB interface

 UART interfaces

 PCM and I2C interfaces

 SD card interface

 ADC interfaces

 Status indication

 SGMII interface

 Wireless connectivity interfaces

 USB_BOOT interface

EC25_Hardware_Design 20 / 112

EC25 Hardware Design

3.2. Pin Assignment

The following figure shows the pin assignment of EC25 module.

LTE Module Series

Figure 2: Pin Assignment (Top View)

NOTES

1)

1.

means that these pins cannot be pulled up before startup.

2)

2.

PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset.

3)

3.

means these interface functions are only supported on Telematics version.

4. Pads 37~40, 118, 127 and 129~139 are used for wireless connectivity interfaces, among which pads

118, 127 and 129~138 are WLAN function pins, and the rest are Bluetooth (BT) function pins. BT

function is under development.

5. Pads 119~126 and 128 are used for SGMII interface.

EC25_Hardware_Design 21 / 112

LTE Module Series

EC25 Hardware Design

6. Pads 24~27 are multiplexing pins used for audio design on the EC25 module and BT function on the

BT module.

7. Keep all RESERVED pins and unused pins unconnected.

8. GND pads 85~112 should be connected to ground in the design, and RESERVED pads 73~84

should not be designed in schematic and PCB decal, and these pins should be served as a keep out

area.

9. “*” means under development.

3.3. Pin Description

The following tables show the pin definition of EC25 modules.

Table 3: I/O Parameters Definition

Type Description

IO Bidirectional

DI Digital input

DO Digital output

PI Power input

PO Power output

AI Analog input

AO Analog output

OD Open drain

Table 4: Pin Description

Power Supply

Pin Name Pin No. I/O Description DC Characteristics Comment

VBAT_BB 59, 60 PI

Power supply for

module’s baseband

part

Vmax=4.3V

Vmin=3.3V

Vnorm=3.8V

It must be able to

provide sufficient

current up to 0.8A.

EC25_Hardware_Design 22 / 112

LTE Module Series

EC25 Hardware Design

It must be able to

provide sufficient

current up to 1.8A in a

burst transmission.

Power supply for

external GPIO’s pull-up

circuits.

VBAT_RF 57, 58 PI

VDD_EXT 7 PO

Power supply for

module’s RF part

Provide 1.8V for

external circuit

Vmax=4.3V

Vmin=3.3V

Vnorm=3.8V

Vnorm=1.8V

I

max=50mA

O

8, 9, 19,

22, 36, 46,

GND

48, 50~54,

Ground

56, 72,

85~112

Turn on/off

Pin Name Pin No. I/O Description DC Characteristics Comment

The output voltage is

0.8V because of the

diode drop in the

Qualcomm chipset.

PWRKEY 21 DI

Turn on/off the

module

V

max=2.1V

IH

V

min=1.3V

IH

V

max=0.5V

IL

max=2.1V

V

RESET_N 20 DI Reset the module

IH

V

min=1.3V

IH

V

max=0.5V

IL

If unused, keep it

open.

Status Indication

Pin Name Pin No. I/O Description DC Characteristics Comment

STATUS 61 OD

Indicate the module

operating status

The drive current

should be less than

0.9mA.

An external pull-up

resistor is required. If

unused, keep it open.

1.8V power domain.

Cannot be pulled up

before startup.

If unused, keep it

NET_MODE 5 DO

Indicate the module

network registration

mode

V

min=1.35V

OH

V

max=0.45V

OL

open.

NET_

STATUS

Indicate the module

6 DO

network activity

status

V

min=1.35V

OH

V

max=0.45V

OL

1.8V power domain.

If unused, keep it

open.

USB Interface

Pin Name Pin No. I/O Description DC Characteristics Comment

USB_VBUS 71 PI USB detection

Vmax=5.25V

Vmin=3.0V

Vnorm=5.0V

Typical: 5.0V

If unused, keep it

open.

EC25_Hardware_Design 23 / 112

LTE Module Series

EC25 Hardware Design

Require differential

impedance of 90Ω.

If unused, keep it

open.

Require differential

impedance of 90Ω.

If unused, keep it

open.

USB_DP 69 IO

USB_DM 70 IO

USB differential data

bus (+)

USB differential data

bus (-)

Compliant with USB

2.0 standard

specification.

Compliant with USB

2.0 standard

specification.

(U)SIM Interface Pin Name Pin No. I/O Description DC Characteristics Comment

USIM_GND 10

USIM_

PRESENCE

13 DI

Specified ground for

(U)SIM card

insertion detection

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V power domain.

If unused, keep it

open.

For 1.8V(U)SIM:

Vmax=1.9V

Vmin=1.7V

USIM_VDD 14 PO

Power supply for

(U)SIM card

For 3.0V(U)SIM:

Vmax=3.05V

Either 1.8V or 3.0V is

supported by the

module automatically.

Vmin=2.7V

I

max=50mA

O

For 1.8V (U)SIM:

V

max=0.6V

IL

V

min=1.2V

IH

V

max=0.45V

OL

V

min=1.35V

OH

For 3.0V (U)SIM:

V

max=1.0V

IL

V

min=1.95V

IH

V

max=0.45V

OL

V

min=2.55V

OH

USIM_DATA 15 IO

Data signal of

(U)SIM card

For 1.8V (U)SIM:

V

max=0.45V

OL

V

min=1.35V

OH

For 3.0V (U)SIM:

V

max=0.45V

OL

V

min=2.55V

OH

USIM_CLK 16 DO

Clock signal of

(U)SIM card

EC25_Hardware_Design 24 / 112

LTE Module Series

EC25 Hardware Design

For 1.8V (U)SIM:

V

max=0.45V

OL

V

min=1.35V

OH

For 3.0V (U)SIM:

V

max=0.45V

OL

V

min=2.55V

OH

USIM_RST 17 DO

Reset signal of

(U)SIM card

Main UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment

V

RI 62 DO Ring indicator

DCD 63 DO

Data carrier

detection

CTS 64 DO Clear to send

RTS 65 DI Request to send

DTR 66 DI

Data terminal ready,

sleep mode control

OL

V

OH

V

OL

V

OH

V

OL

V

OH

V

IL

V

IL

V

IH

V

IH

V

IL

V

IL

V

IH

V

IH

max=0.45V

min=1.35V

max=0.45V

min=1.35V

max=0.45V

min=1.35V

min=-0.3V

max=0.6V

min=1.2V

max=2.0V

min=-0.3V

max=0.6V

min=1.2V

max=2.0V

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

Pulled up by default.

Low level wakes up

the module.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

TXD 67 DO Transmit data

RXD 68 DI Receive data

V

max=0.45V

OL

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

Debug UART Interface Pin Name Pin No. I/O Description DC Characteristics Comment

1.8V power domain.

If unused, keep it

open.

DBG_TXD 12 DO Transmit data

V

max=0.45V

OL

V

min=1.35V

OH

DBG_RXD 11 DI Receive data VILmin=-0.3V 1.8V power domain.

EC25_Hardware_Design 25 / 112

LTE Module Series

EC25 Hardware Design

VILmax=0.6V

VIHmin=1.2V

V

max=2.0V

IH

If unused, keep it

open.

ADC Interface Pin Name Pin No. I/O Description DC Characteristics Comment

General purpose

ADC0 45 AI

analog to digital

converter

General purpose

ADC1 44 AI

analog to digital

converter

Voltage range:

0.3V to VBAT_BB

Voltage range:

0.3V to VBAT_BB

If unused, keep it

open.

If unused, keep it

open.

PCM Interface Pin Name Pin No. I/O Description DC Characteristics Comment

V

min=-0.3V

PCM_IN 24 DI PCM data input

PCM_OUT 25 DO PCM data output

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

V

max=0.45V

OL

V

min=1.35V

OH

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

In master mode, it is

an output signal. In

slave mode, it is an

input signal.

If unused, keep it

open.

1.8V power domain.

In master mode, it is

an output signal. In

slave mode, it is an

input signal.

If unused, keep it

open.

PCM data frame

PCM_SYNC 26 IO

synchronization

signal

PCM_CLK 27 IO PCM clock

VOLmax=0.45V

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

V

max=0.45V

OL

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

I2C Interface Pin Name Pin No. I/O Description DC Characteristics Comment

External pull-up

I2C_SCL 41 OD

I2C serial clock Used

for external codec.

resistor is required.

1.8V only. If unused,

keep it open.

EC25_Hardware_Design 26 / 112

LTE Module Series

EC25 Hardware Design

External pull-up

I2C_SDA 42 OD

I2C serial dataUsed

for external codec.

resistor is required.

1.8V only. If unused,

keep it open.

SD Card Interface

Pin Name Pin No. I/O Description DC Characteristics Comment

1.8V signaling:

V

max=0.45V

OL

V

min=1.4V

OH

V

min=-0.3V

SDC2_

DATA3

28 IO

SD card SDIO bus

DATA3

IL

V

max=0.58V

IL

V

min=1.27V

IH

V

max=2.0V

IH

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

V

min=-0.3V

IL

V

max=0.76V

IL

V

min=1.72V

IH

V

max=3.34V

IH

SDIO signal level can

be selected according

to SD card supported

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

1.8V signaling:

V

max=0.45V

OL

V

min=1.4V

OH

V

min=-0.3V

SDC2_

DATA2

SDC2_

DATA1

29 IO

30 IO

SD card SDIO bus

DATA2

SD card SDIO bus

DATA1

IL

V

max=0.58V

IL

V

min=1.27V

IH

V

max=2.0V

IH

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

V

min=-0.3V

IL

V

max=0.76V

IL

V

min=1.72V

IH

V

max=3.34V

IH

1.8V signaling:

V

max=0.45V

OL

V

min=1.4V

OH

V

min=-0.3V

IL

V

max=0.58V

IL

V

min=1.27V

IH

SDIO signal level can

be selected according

to SD card supported

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

SDIO signal level can

be selected according

to SD card supported

EC25_Hardware_Design 27 / 112

LTE Module Series

EC25 Hardware Design

SDC2_

DATA0

31 IO

SDC2_CLK 32 DO

SD card SDIO bus

DATA0

SD card SDIO bus

clock

VIHmax=2.0V

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

V

min=-0.3V

IL

V

max=0.76V

IL

V

min=1.72V

IH

V

max=3.34V

IH

1.8V signaling:

V

max=0.45V

OL

V

min=1.4V

OH

V

min=-0.3V

IL

V

max=0.58V

IL

V

min=1.27V

IH

V

max=2.0V

IH

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

V

min=-0.3V

IL

V

max=0.76V

IL

V

min=1.72V

IH

V

max=3.34V

IH

1.8V signaling:

V

max=0.45V

OL

V

min=1.4V

OH

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

SDIO signal level can

be selected according

to SD card supported

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

SDIO signal level can

be selected according

to SD card supported

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

1.8V signaling:

max=0.45V

V

OL

V

SDC2_CMD 33 IO

SD card SDIO bus

command

min=1.4V

OH

V

min=-0.3V

IL

V

max=0.58V

IL

V

min=1.27V

IH

V

max=2.0V

IH

3.0V signaling:

max=0.38V

V

OL

V

min=2.01V

OH

V

min=-0.3V

IL

SDIO signal level can

be selected according

to SD card supported

level, please refer to

SD 3.0 protocol for

more details.

If unused, keep it

open.

EC25_Hardware_Design 28 / 112

LTE Module Series

EC25 Hardware Design

VILmax=0.76V

VIHmin=1.72V

V

max=3.34V

IH

V

min=-0.3V

SD_INS_

DET

23 DI

SD card insertion

detect

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V power domain.

If unused, keep it

open.

1.8V/2.85V

configurable. Cannot

be used for SD card

power. If unused,

VDD_SDIO 34 PO

SD card SDIO bus

pull-up power

I

max=50mA

O

keep it open.

SGMII Interface Pin Name Pin No. I/O Description DC Characteristics Comment

For 1.8V:

V

max=0.45V

EPHY_RST_

N

119 DO Ethernet PHY reset

EPHY_INT_N 120 DI

Ethernet PHY

interrupt

OL

V

min=1.4V

OH

For 2.85V:

V

max=0.35V

OL

V

min=2.14V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V/2.85V power

domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

For 1.8V:

V

max=0.45V

OL

V

min=1.4V

OH

V

max=0.58V

SGMII_

MDATA

SGMII MDIO

121 IO

(Management Data

Input/Output) data

IL

V

min=1.27V

IH

For 2.85V:

V

max=0.35V

OL

V

min=2.14V

OH

V

max=0.71V

IL

V

min=1.78V

IH

1.8V/2.85V power

domain.

If unused, keep it

open.

For 1.8V:

V

max=0.45V

SGMII_

MCLK

SGMII MDIO

122 DO

(Management Data

Input/Output) clock

OL

V

min=1.4V

OH

For 2.85V:

V

max=0.35V

OL

V

min=2.14V

OH

1.8V/2.85V power

domain.

If unused, keep it

open.

EC25_Hardware_Design 29 / 112

EC25 Hardware Design

USIM2_VDD 128 PO

SGMII_TX_M 123 AO

SGMII_TX_P 124 AO

SGMII MDIO pull-up

power source

SGMII transmission

- minus

SGMII transmission

- plus

LTE Module Series

Configurable power

source.

1.8V/2.85V power

domain.

External pull-up for

SGMII MDIO pins.

If unused, keep it

open.

Connect with a 0.1uF

capacitor, close to the

PHY side.

If unused, keep it

open.

Connect with a 0.1uF

capacitor, close to the

PHY side.

If unused, keep it

open.

Connect with a 0.1uF

capacitor, close to

EC25 module.

If unused, keep it

SGMII_RX_P 125 AI

SGMII receiving

- plus

open.

Connect with a 0.1uF

capacitor, close to

EC25 module.

If unused, keep it

SGMII_RX_M 126 AI

SGMII receiving

-minus

open.

Wireless Connectivity Interfaces

Pin Name Pin No. I/O Description DC Characteristics Comment

V

max=0.45V

OL

V

min=1.35V

SDC1_

DATA3

SDC1_

DATA2

129 IO

130 IO

WLAN SDIO data

bus D3

WLAN SDIO data

bus D2

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

V

max=0.45V

OL

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

EC25_Hardware_Design 30 / 112

EC25 Hardware Design

SDC1_

DATA1

SDC1_

DATA0

131 IO

132 IO

SDC1_CLK 133 DO

WLAN SDIO data

bus D1

WLAN SDIO data

bus D0

WLAN SDIO bus

clock

V

OL

VOHmin=1.35V

V

IL

V

IL

V

IH

V

IH

V

OL

V

OH

V

IL

V

IL

V

IH

V

IH

V

OL

V

OH

max=0.45V

min=-0.3V

max=0.6V

min=1.2V

max=2.0V

max=0.45V

min=1.35V

min=-0.3V

max=0.6V

min=1.2V

max=2.0V

max=0.45V

min=1.35V

LTE Module Series

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

SDC1_CMD 134 DO

PM_ENABLE 127 DO

WAKE_ON_

WIRELESS

135 DI

WLAN_EN 136 DO

COEX_UART

_RX

137 DI

WLAN SDIO bus

command

External power

control

Wake up the host

(EC25 module) by

FC20 module

WLAN function

control via FC20

module

LTE/WLAN&BT

coexistence signal

V

max=0.45V

OL

V

min=1.35V

OH

V

max=0.45V

OL

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

V

max=0.45V

OL

V

min=1.35V

OH

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

Active low.

If unused, keep it

open.

1.8V power domain.

Active high.

Cannot be pulled up

before startup.

If unused, keep it

open.

1.8V power domain.

Cannot be pulled up

before startup.

If unused, keep it

open.

1.8V power domain.

COEX_UART

_TX

138 DO

LTE/WLAN&BT

coexistence signal

V

max=0.45V

OL

V

min=1.35V

OH

Cannot be pulled up

before startup.

If unused, keep it

open.

WLAN_SLP_

CLK

118 DO WLAN sleep clock

If unused, keep it

open.

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BT_RTS* 37 DI

BT_TXD* 38 DO

BT_RXD* 39 DI

BT_CTS* 40 DO

BT UART request to

send

BT UART transmit

data

BT UART receive

data

BT UART clear to

send

V

VILmax=0.6V

V

min=-0.3V

IL

min=1.2V

IH

max=2.0V

IH

max=0.45V

OL

min=1.35V

OH

min=-0.3V

IL

max=0.6V

IL

min=1.2V

IH

max=2.0V

IH

max=0.45V

OL

min=1.35V

OH

LTE Module Series

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

If unused, keep it

open.

1.8V power domain.

Cannot be pulled up

before startup.

If unused, keep it

open.

BT_EN* 139 DO

BT function control

via the BT module

V

max=0.45V

OL

V

min=1.35V

OH

1.8V power domain.

If unused, keep it

open.

RF Interface

Pin Name Pin No. I/O Description DC Characteristics Comment

ANT_DIV 35 AI

Diversity antenna

pad

ANT_MAIN 49 IO Main antenna pad

50Ω impedance

If unused, keep it

open.

50Ω impedance

ANT_GNSS 47 AI GNSS antenna pad

If unused, keep it

open.

GPIO Pins

Pin Name Pin No. I/O Description DC Characteristics Comment

1.8V power domain.

Cannot be pulled up

before startup.

Low level wakes up

the module.

If unused, keep it

WAKEUP_IN 1 DI Sleep mode control

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

open.

V

W_DISABLE# 4 DI

Airplane mode

control

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

1.8V power domain.

Pull-up by default.

At low voltage level,

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V

max=2.0V module can enter into

IH

airplane mode.

If unused, keep it

open.

V

min=-0.3V

AP_READY 2 DI

Application

processor sleep

state detection

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

1.8V power domain.

If unused, keep it

open.

USB_BOOT Interface

Pin Name Pin No. I/O Description DC Characteristics Comment

1.8V power domain.

Cannot be pulled up

before startup.

It is recommended to

reserve test point.

USB_BOOT 115 DI

Force the module to

enter into

emergency

download mode

V

min=-0.3V

IL

V

max=0.6V

IL

V

min=1.2V

IH

V

max=2.0V

IH

RESERVED Pins

Pin Name Pin No. I/O Description DC Characteristics Comment

3, 18, 43,

RESERVED

55, 73~84,

113, 114,

116, 117,

Reserved

Keep these pins

unconnected.

140-144.

NOTES

1. “*” means under development.

2. Pads 24~27 are multiplexing pins used for audio design on the EC25 module and BT function on the

BT module.

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3.4. Operating Modes

The table below briefly summarizes the various operating modes referred in the following chapters.

Table 5: Overview of Operating Modes

Mode Details

Normal

Idle

Operation

Talk/Data

Minimum

Functionality

Mode

Airplane Mode

AT+CFUN command can set the module to a minimum functionality mode without

removing the power supply. In this case, both RF function and (U)SIM card will be

invalid.

AT+CFUN command or W_DISABLE# pin can set the module to airplane mode. In

this case, RF function will be invalid.

In this mode, the current consumption of the module will be reduced to the minimal

Sleep Mode

level. During this mode, the module can still receive paging message, SMS, voice

call and TCP/UDP data from the network normally.

Power Down

Mode

In this mode, the power management unit shuts down the power supply. Software is

not active. The serial interface is not accessible. Operating voltage (connected to

VBAT_RF and VBAT_BB) remains applied.

3.5. Power Saving

Software is active. The module has registered on the network, and it is

ready to send and receive data.

Network connection is ongoing. In this mode, the power consumption is

decided by network setting and data transfer rate.

3.5.1. Sleep Mode

EC25 is able to reduce its current consumption to a minimum value during the sleep mode. The following

section describes power saving procedures of EC25 module.

3.5.1.1. UART Application

If the host communicates with module via UART interface, the following preconditions can let the module

enter into sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.

 Drive DTR to high level.

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The following figure shows the connection between the module and the host.

Figure 3: Sleep Mode Application via UART

 Driving the host DTR to low level will wake up the module.

 When EC25 has a URC to report, RI signal will wake up the host. Please refer to Chapter 3.17 for

details about RI behaviors.

 AP_READY will detect the sleep state of the host (can be configured to high level or low level

detection). Please refer to AT+QCFG="apready"* command for details.

NOTE

“*” means under development.

3.5.1.2. USB Application with USB Remote Wakeup Function

If the host supports USB suspend/resume and remote wakeup function, the following three preconditions

must be met to let the module enter into the sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.

 Ensure the DTR is held at high level or keep it open.

 The host’s USB bus, which is connected with the module’s USB interface, enters into suspended

state.

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The following figure shows the connection between the module and the host.

Figure 4: Sleep Mode Application with USB Remote Wakeup

 Sending data to EC25 through USB will wake up the module.

 When EC25 has a URC to report, the module will send remote wake-up signals via USB bus so as to

wake up the host.

3.5.1.3. USB Application with USB Suspend/Resume and RI Function

If the host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is

needed to wake up the host.

There are three preconditions to let the module enter into the sleep mode.

 Execute AT+QSCLK=1 command to enable the sleep mode.

 Ensure the DTR is held at high level or keep it open.

 The host’s USB bus, which is connected with the module’s USB interface, enters into suspended

state.

The following figure shows the connection between the module and the host.

Figure 5: Sleep Mode Application with RI

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 Sending data to EC25 through USB will wake up the module.

 When EC25 has a URC to report, RI signal will wake up the host.

3.5.1.4. USB Application without USB Suspend Function

If the host does not support USB suspend function, USB_VBUS should be disconnected via an additional

control circuit to let the module enter into sleep mode.

 Execute AT+QSCLK=1 command to enable sleep mode.

 Ensure the DTR is held at high level or keep it open.

 Disconnect USB_VBUS.

The following figure shows the connection between the module and the host.

Figure 6: Sleep Mode Application without Suspend Function

Switching on the power switch to supply power to USB_VBUS will wake up the module.

NOTE

Please pay attention to the level match shown in dotted line between the module and the host. For more

details about EC25 power management application, please refer to document [1].

3.5.2. Airplane Mode

When the module enters into airplane mode, the RF function does not work, and all AT commands

correlative with RF function will be inaccessible. This mode can be set via the following ways.

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Hardware:

The W_DISABLE# pin is pulled up by default; driving it to low level will let the module enter into airplane

mode.

Software: AT+CFUN command provides the choice of the functionality level through setting <fun> into 0, 1 or 4.

 AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.  AT+CFUN=1: Full functionality mode (by default).  AT+CFUN=4: Airplane mode. RF function is disabled.

NOTES

1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by

AT+QCFG="airplanecontrol" command, and this command is under development.

2. The execution of AT+CFUN command will not affect GNSS function.

3.6. Power Supply

3.6.1. Power Supply Pins

EC25 provides four VBAT pins to connect with the external power supply, and there are two separate

voltage domains for VBAT.

 Two VBAT_RF pins for module’s RF part

 Two VBAT_BB pins for module’s baseband part

The following table shows the details of VBAT pins and ground pins.

Table 6: VBAT and GND Pins

Pin Name Pin No. Description Min. Typ. Max. Unit

VBAT_RF 57, 58

VBAT_BB 59, 60

8, 9, 19, 22, 36,

GND

EC25_Hardware_Design 38 / 112

46, 48, 50~54,

56, 72, 85~112

Power supply for module’s RF

part

Power supply for module’s

baseband part

Ground - 0 - V

3.3 3.8 4.3 V

LTE Module Series

EC25 Hardware Design

3.6.2. Decrease Voltage Drop

The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will

never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G

network. The voltage drop will be less in 3G and 4G networks.

Figure 7: Power Supply Limits during Burst Transmission

To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR=0.7Ω) should be used,

and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR. It

is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array,

and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an external

application has to be a single voltage source and can be expanded to two sub paths with star structure.

The width of VBAT_BB trace should be no less than 1mm; and the width of VBAT_RF trace should be no

less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.

In addition, in order to get a stable power source, it is suggested that a zener diode whose reverse zener

voltage is 5.1V and dissipation power is more than 0.5W should be used. The following figure shows the

star structure of the power supply.

Figure 8: Star Structure of the Power Supply

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3.6.3. Reference Design for Power Supply

Power design for the module is very important, as the performance of the module largely depends on the

power source. The power supply should be able to provide sufficient current up to 2A at least. If the

voltage drop between the input and output is not too high, it is suggested that an LDO should be used to

supply power for the module. If there is a big voltage difference between the input source and the desired

output (VBAT), a buck converter is preferred to be used as the power supply.

The following figure shows a reference design for +5V input power source. The typical output of the power

supplyis about 3.8V and the maximum load current is 3A.

Figure 9: Reference Circuit of Power Supply

NOTE

In order to avoid damaging internal flash, please do not switch off the power supply when the module

works normally. Only after the module is shutdown by PWRKEY or AT command, then the power supply

can be cut off.

3.6.4. Monitor the Power Suppl y

AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to

document [2].

3.7. Turn on and off Scenarios

3.7.1. Turn on Module Using the PWRKEY

The following table shows the pin definition of PWRKEY.

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EC25 Hardware Design

Table 7: Pin Definition of PWRKEY

Pin Name Pin No. I/O Description Comment

LTE Module Series

PWRKEY 21 DI Turn on/off the module

The output voltage is 0.8V because of

the diode drop in the Qualcomm chipset.

When EC25 is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin to a

low level for at least 500ms. It is recommended to use an open drain/collector driver to control the

PWRKEY. After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be

released. A simple reference circuit is illustrated in the following figure.

PWRKEY

≥ 500ms

4.7K 10nF

Turn on pulse

47K

Figure 10: Turn on the Module by Using Driving Circuit

The other way to control the PWRKEY is using a button directly. When pressing the key, electrostatic

strike may generate from finger. Therefore, a TVS component is indispensable to be placed nearby the

button for ESD protection. A reference circuit is shown in the following figure.

Figure 11: Turn on the Module by Using Button

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The turn on scenario is illustrated in the following figure.

LTE Module Series

Figure 12: Timing of Turning on Module

NOTE

Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them should

be no no less than 30ms.

3.7.2. Turn off Module

The following procedures can be used to turn off the module:

 Normal power down procedure: Turn off the module using the PWRKEY pin.

 Normal power down procedure: Turn off the module using AT+QPOWD command.

3.7.2.1. Turn off Module Using the PWRKEY Pin

Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-down

procedure after the PWRKEY is released. The power-down scenario is illustrated in the following figure.

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Figure 13: Timing of Turning off Module

3.7.2.2. Turn off Module Using AT Command

It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the

module via PWRKEY pin.

Please refer to document [2] for details about AT+QPOWD command.

NOTES

1. Inorder to avoid damaging internal flash, please do not switch off the power supply when the module

works normally. Only after the module is shut down by PWRKEY or AT command, then the power

supply can be cut off.

2. When turn off module with AT command, please keep PWRKEY at high level after the execution of

power-off command. Otherwise the module will be turned on again after successfully turn-off.

3.8. Reset the Module

The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a

low level voltage for time between 150ms and 460ms.

Table 8: RESET_N Pin Description

Pin Name Pin No. I/O Description Comment

RESET_N 20 DI Reset the module 1.8V power domain

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The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button

can be used to control the RESET_N.

Figure 14: Reference Circuit of RESET_N by Using Driving Circuit

Figure 15: Reference Circuit of RESET_N by Using Button

The reset scenario is illustrated inthe following figure.

Figure 16: Timing of Resetting Module

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NOTES

1. Use RESET_N only when turning off the module by AT+QPOWD command and PWRKEY pin failed.

2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.

3.9. (U)SIM Interface

The(U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards

are supported.

Table 9: Pin Definition of the (U)SIM Interface

Pin Name Pin No. I/O Description Comment

USIM_VDD 14 PO Power supply for (U)SIM card

Either 1.8V or 3.0V is supported

by the module automatically.

USIM_DATA 15 IO Data signal of (U)SIM card

USIM_CLK 16 DO Clock signal of (U)SIM card

USIM_RST 17 DO Reset signal of (U)SIM card

USIM_

PRESENCE

13 DI (U)SIM card insertion detection

USIM_GND 10 Specified ground for (U)SIM card

EC25 supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and

high level detections, and it is disabled by default. Please refer to document [2] for more details about

AT+QSIMDET command.

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The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.

Figure 17: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector

If (U)SIM card detection function is not needed, please keep USIM_PRESENCE unconnected. A

reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following

figure.

Figure 18: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector

In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please

follow the criteria below in (U)SIM circuit design:

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 Keep placement of (U)SIM card connector to the module as close as possible. Keep the trace length

as less than 200mm as possible.

 Keep (U)SIM card signals away from RF and VBAT traces.

 Assure the ground between the module and the (U)SIM card connector short and wide. Keep the

trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential.

Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as

close to (U)SIM card connector as possible. If the ground is complete on customers’ PCB,

USIM_GND can be connected to PCB ground directly.

 To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and

shield them with surrounded ground.

 In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic

capacitance should not be more than 15pF. The 0Ω resistors should be added in series between the

module and the (U)SIM card to facilitate debugging. The 33pF capacitors are used for filtering

interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to the

(U)SIM card connector.

 The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace

and sensitive occasion are applied, and it should be placed close to the (U)SIM card connector.

3.10. USB Interface

EC25 contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0

specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is

used for AT command communication, data transmission, GNSS NMEA sentences output, software

debugging, firmware upgrade and voice over USB*. The following table shows the pin definition of USB

interface.

Table 10: Pin Description of USB Interface

Pin Name Pin No. I/O Description Comment

USB_DP 69 IO USB differential data bus (+)

USB_DM 70 IO USB differential data bus (-)

USB_VBUS 71 PI USB connection detection Typical 5.0V

Require differential

impedance of 90Ω

Require differential

impedance of 90Ω

GND 72 Ground

For more details about the USB 2.0 specifications, please visit http://www.usb.org/home

.

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The USB interface is recommended to be reserved for firmware upgrade in customers’ designs. The

following figure shows a reference circuit of USB interface.

Figure 19: Reference Circuit of USB Application

A common mode choke L1 is recommended to be added in series between the module and customer’s

MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be

added in series between the module and the test points so as to facilitate debugging, and the resistors are

not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components

must be placed close to the module, and also these resistors should be placed close to each other. The

extra stubs of trace must be as short as possible.

The following principles should be complied with when design the USB interface, so as to meet USB 2.0

specification.

 It is important to route the USB signal traces as differential pairs with total grounding. The impedance

of USB differential trace is 90Ω.

 Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is

important to route the USB differential traces in inner-layer with ground shielding on not only upper

and lower layers but also right and left sides.

 Pay attention to the influence of junction capacitance of ESD protection components on USB data

lines. Typically, the capacitance value should be less than 2pF.

 Keep the ESD protection components to the USB connector as close as possible.

NOTES

1. EC25 module can only be used as a slave device.

2. “*” means under development.

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3.11. UART Interfaces

The module provides two UART interfaces: the main UART interface and the debug UART interface. The

following shows their features.

 The main UART interface supports 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,

230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. This interface is

used for data transmission and AT command communication.

 The debug UART interface supports 115200bps baud rate. It is used for Linux console and log

output.

The following tables show the pin definition of the UART interfaces.

Table 11: Pin Definition of Main UART Interface

Pin Name Pin No. I/O Description Comment

RI 62 DO Ring indicator

DCD 63 DO Data carrier detection

CTS 64 DO Clear to send

RTS 65 DI Request to send

1.8V power domain

DTR 66 DI Data terminal ready

TXD 67 DO Transmit data

RXD 68 DI Receive data

Table 12: Pin Definition of Debug UART Interface

Pin Name Pin No. I/O Description Comment

DBG_TXD 12 DO Transmit data

1.8V power domain

DBG_RXD 11 DI Receive data

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The logic levels are described in the following table.

Table 13: Logic Levels of Digital I/O

Parameter Min. Max. Unit

VIL -0.3 0.6 V

VIH 1.2 2.0 V

VOL 0 0.45 V

VOH 1.35 1.8 V

The module provides 1.8V UART interface. A level translator should be used if customers’ application is

equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments

is recommended. The following figure shows a reference design.

Figure 20: Reference Circuit with Translator Chip

Please visit http://www.ti.com

for more information.

Another example with transistor translation circuit is shown as below. The circuit design of dotted line

section can refer to the design of solid line section, in terms of both module’s input and output circuit

designs, but please pay attention to the direction of connection.

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Figure 21: Reference Circuit with Transistor Circuit

NOTE

Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.

3.12. PCM and I2C Interfaces

EC25 provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the

following modes and one I2C interface:

 Primary mode (short frame synchronization, works as both master and slave)

 Auxiliary mode (long frame synchronization, works as master only)

In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising

edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports

256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK at 8kHz PCM_SYNC, and also supports 4096kHz

PCM_CLK at 16kHz PCM_SYNC.

In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising

edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a

256kHz, 512kHz, 1024kHz or 2048kHz PCM_CLK and an 8kHz, 50% duty cycle PCM_SYNC.

EC25 supports 16-bit linear data format. The following figures show the primary mode’s timing

relationship with 8KHz PCM_SYNC and 2048KHz PCM_CLK, as well as the auxiliary mode’s timing

relationship with 8KHz PCM_SYNC and 256KHz PCM_CLK.

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Figure 22: Primary Mode Timing

Figure 23: Auxiliary Mode Timing

The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio

codec design.

Table 14: Pin Definition of PCM and I2C Interfaces

Pin Name Pin No. I/O Description Comment

PCM_IN 24 DI PCM data input 1.8V power domain

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PCM_OUT 25 DO PCM data output 1.8V power domain

PCM_SYNC 26 IO

PCM data frame

synchronization signal

1.8V power domain

PCM_CLK 27 IO PCM data bit clock 1.8V power domain

I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V

I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V

Clock and mode can be configured by AT command, and the default configuration is master mode using

short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to

document [2] for more details about AT+QDAI command.

The following figure shows a reference design of PCM interface with external codec IC.

Figure 24: Reference Circuit of PCM Application with Audio Codec

NOTES

1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuits on the PCM lines, especially for

PCM_CLK.

2. EC25 works as a master device pertaining to I2C interface.

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3.13. SD Card Interface

EC25 supports SDIO 3.0 interface for SD card.

The following table shows the pin definition of SD card interface.

Table 15: Pin Definition of SD Card Interface

Pin Name Pin No. I/O Description Comment

SDIO signal level can be

selected according to SD

SDC2_DATA3 28 IO SD card SDIO bus DATA3

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

SDC2_DATA2 29 IO SD card SDIO bus DATA2

SDC2_DATA1 30 IO SD card SDIO bus DATA1

SDC2_DATA0 31 IO SD card SDIO bus DATA0

SDC2_CLK 32 DO SD card SDIO bus clock

SDIO signal level can be

selected according to SD

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

SDIO signal level can be

selected according to SD

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

SDIO signal level can be

selected according to SD

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

SDIO signal level can be

selected according to SD

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

SDC2_CMD 33 IO SD card SDIO bus command

SDIO signal level can be

selected according to SD

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VDD_SDIO 34 PO SD card SDIO bus pull up power

LTE Module Series

card supported level,

please refer to SD 3.0

protocol for more details.

If unused, keep it open.

1.8V/2.85V configurable.

Cannot be used for SD

card power. If unused,

keep it open.

SD_INS_DET 23 DI SD card insertion detection

The following figure shows a reference design of SD card.

1.8V power domain.

If unused, keep it open.

Figure 25: Reference Circuit of SD card

In SD card interface design, in order to ensure good communication performance with SD card, the

following design principles should be complied with:

 SD_INS_DET must be connected.

 The voltage range of SD card power supply VDD_3V is 2.7V~3.6V and a sufficient current up to 0.8A

should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used

for SDIO pull-up resistors, an externally power supply is needed for SD card.

 To avoid jitter of bus, resistors R7~R11 are needed to pull up the SDIO to VDD_SDIO. Value of these

resistors is among 10KΩ~100KΩ and the recommended value is 100KΩ. VDD_SDIO should be used

as the pull-up power.

 In order to adjust signal quality, it is recommended to add 0Ω resistors R1~R6 in series between the

module and the SD card. The bypass capacitors C1~C6 are reserved and not mounted by default. All

resistors and bypass capacitors should be placed close to the module.

 In order to offer good ESD protection, it is recommended to add a TVS diode on SD card pins near

the SD card connector with junction capacitance less than 15pF.

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 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,

etc., as well as noisy signals such as clock signals, DCDC signals, etc.

 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data trace

is 50Ω (±10%).

 Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of

SDIO bus should be less than 15pF.

 It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm

and the total routing length less than 50mm. The total trace length inside the module is 27mm, so the

exterior total trace length should be less than 23mm.

3.14. ADC Interfaces

The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 command can be used to read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage value on ADC1 pin. For more details about these AT commands, please refer to document [2].

In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.

Table 16: Pin Definition of ADC Interfaces

Pin Name Pin No. Description

ADC0 45 General purpose analog to digital converter

ADC1 44 General purpose analog to digital converter

The following table describes the characteristic of ADC function.

Table 17: Characteristic of ADC

Parameter Min. Typ. Max. Unit

ADC0 Voltage Range 0.3 VBAT_BB V

ADC1 Voltage Range 0.3 VBAT_BB V

ADC Resolution 15 Bits

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NOTES

1. ADC input voltage must not exceed VBAT_BB.

2. It is prohibited to supply any voltage to ADC pins when VBAT is removed.

3. It is recommended to use a resistor divider circuit for ADC application.

3.15. Network Status Indication

The network indication pins can be used to drive network status indication LEDs. The module provides

two pins which are NET_MODE and NET_STATUS. The following tables describe the pin definition and

logic level changes in different network status.

Table 18: Pin Definition of Network Connection Status/Activity Indicator

Pin Name Pin No. I/O Description Comment

1.8V power domain

Cannot be pulled up

before startup

1.8V power domain

NET_MODE 5 DO

NET_STATUS 6 DO

Indicate the module network

registration mode.

Indicate the module network activity

status.

Table 19: Working State of the Network Connection Status/Activity Indicator

Pin Name Logic Level Changes Network Status

Always High Registered on LTE network

NET_MODE

Always Low Others

Flicker slowly (200ms High/1800ms Low) Network searching

Flicker slowly (1800ms High/200ms Low) Idle

NET_STATUS

Flicker quickly (125ms High/125ms Low) Data transfer is ongoing

Always High Voice calling

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A reference circuit is shown in the following figure.

Figure 26: Reference Circuit of the Network Indicator

LTE Module Series

3.16. STATUS

The STATUS pin is an open drain output for indicating the module’s operation status. It can be connected

to a GPIO of DTE with a pull-up resistor, or as LED indication circuit as below. When the module is turned

on normally, the STATUS will present the low state. Otherwise, the STATUS will present high-impedance

state.

Table 20: Pin Definition of STATUS

Pin Name Pin No. I/O Description Comment

STATUS 61 OD Indicate the module’s operation status

The following figure shows different circuit designs of STATUS, and customers can choose either one

according to customers’ application demands.

An external pull-up resistor

is required.

If unused, keep it open.

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3.17. Behaviors of RI

LTE Module Series

Figure 27: Reference Circuits of STATUS

AT+QCFG="risignaltype","physical" command can be used to configure RI behavior.

No matter on which port URC is presented, URC will trigger the behavior of RI pin.

NOTE

URC can be outputted from UART port, USB AT port and USB modem port through configuration via

AT+QURCCFG command. The default port is USB AT port.

In addition, RI behavior can be configured flexibly. The default behavior of the RI is shown as below.

Table 21: Behavior of RI

State Response

Idle RI keeps at high level

URC RI outputs 120ms low pulse when a new URC returns

The RI behavior can be changed by AT+QCFG="urc/ri/ring" command. Please refer to document [2]

for details.

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3.18. SGMII Interface

EC25 includes an integrated Ethernet MAC with an SGMII interface and two management interfaces, key

features of the SGMII interface are shown below:

 IEEE802.3 compliance

 Support 10M/100M/1000M Ethernet work mode

 Support maximum 150Mbps (DL)/50Mbps (UL) for 4G network

 Support VLAN tagging

 Support IEEE1588 and Precision Time Protocol (PTP)

 Can be used to connect to external Ethernet PHY like AR8033, or to an external switch

 Management interfaces support dual voltage 1.8V/2.85V

The following table shows the pin definition of SGMII interface.

Table 22: Pin Definition of the SGMII Interface

Pin Name Pin No. I/O Description Comment Control Signal Part

EPHY_RST_N 119 DO Ethernet PHY reset 1.8V/2.85V power domain

EPHY_INT_N 120 DI Ethernet PHY interrupt 1.8V power domain

SGMII_MDATA 121 IO

SGMII_MCLK 122 DO

SGMII MDIO (Management Data

Input/Output) data

SGMII MDIO (Management Data

Input/Output) clock

1.8V/2.85V power domain

Configurable power source.

USIM2_VDD 128 PO SGMII MDIO pull-up power source

1.8V/2.85V power domain.

External pull-up power source for

SGMII MDIO pins.

SGMII Signal Part

SGMII_TX_M 123 AO SGMII transmission-minus

Connect with a 0.1uF capacitor,

close to the PHY side.

SGMII_TX_P 124 AO SGMII transmission-plus

SGMII_RX_P 125 AI SGMII receiving-plus

SGMII_RX_M 126 AI SGMII receiving-minus

Connect with a 0.1uF capacitor,

close to the PHY side.

Connect with a 0.1uF capacitor,

close to EC25 module.

Connect with a 0.1uF capacitor,

close to EC25 module.

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The following figure shows the simplified block diagram for Ethernet application.

Figure 28: Simplified Block Diagram for Ethernet Application

The following figure shows a reference design of SGMII interface with PHY AR8033 application.

Figure 29: Reference Circuit of SGMII Interface with PHY AR8033 Application

In order to enhance the reliability and availability in customers’ applications, please follow the criteria

below in the Ethernet PHY circuit design:

 Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,

analog signals, etc., as well as noisy signals such as clock signals, DCDC signals, etc.

 Keep the maximum trace length less than 10-inch and keep skew on the differential pairs less than

20mil.

 The differential impedance of SGMII data trace is 100Ω±10%, and the reference ground of the area

should be complete.

 Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the

same to the adjacent signal traces.

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3.19. Wireless Connectivity Interfaces

EC25 supports a low-power SDIO 3.0 interface for WLAN and a UART/PCM interface for BT.

The following table shows the pin definition of wireless connectivity interfaces.

Table 23: Pin Definition of Wireless Connectivity Interfaces

Pin Name Pin No. I/O Description Comment WLAN Part

SDC1_DATA3 129 IO WLAN SDIO data bus D3 1.8V power domain

SDC1_DATA2 130 IO WLAN SDIO data bus D2 1.8V power domain

SDC1_DATA1 131 IO WLAN SDIO data bus D1 1.8V power domain

SDC1_DATA0 132 IO WLAN SDIO data bus D0 1.8V power domain

SDC1_CLK 133 DO WLAN SDIO bus clock 1.8V power domain

SDC1_CMD 134 IO WLAN SDIO bus command 1.8V power domain

1.8V power domain.

WLAN_EN 136 DO

WLAN function control via FC20

module.

Active high.

Cannot be pulled up

before startup.

Coexistence and Control Part

PM_ENABLE 127 DO External power control

WAKE_ON_

WIRELESS

135 DI

Wake up the host (EC25 module) by

FC20 module

1.8V power domain

Active high.

1.8V power domain

1.8V power domain.

COEX_UART_RX 137 DI LTE/WLAN&BT coexistence signal

Cannot be pulled up

before startup.

1.8V power domain.

COEX_UART_TX 138 DO LTE/WLAN&BT coexistence signal

Cannot be pulled up

before startup.

WLAN_SLP_CLK 118 DO WLAN sleep clock

BT Part*

BT_RTS* 37 DI BT UART request to send 1.8V power domain

BT_TXD* 38 DO BT UART transmit data 1.8V power domain

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BT_RXD* 39 DI BT UART receive data 1.8V power domain

1.8V power domain.

BT_CTS* 40 DO BT UART clear to send

Cannot be pulled up

before startup.

PCM_IN1) 24 DI PCM data input 1.8V power domain

PCM_OUT1) 25 DO PCM data output 1.8V power domain

PCM_SYNC1) 26 IO

PCM data frame synchronization

signal

1.8V power domain

PCM_CLK1) 27 IO PCM data bit clock 1.8V power domain

BT_EN* 139 DO BT function control via BT module.

1.8V power domain

Active high.

The following figure shows a reference design of wireless connectivity interfaces with Quectel FC20

module.

POWER

WLAN

Module

SDC1_DAT A3

SDC1_DAT A2

SDC1_DAT A1

SDC1_DATA0

WLAN_SLP_CLK

WAKE_ ON _WIRELE SS

PM_ENABLE

VDD_EXT VIO

SDC1_CLK

SDC1_CMD

WLAN_EN

DCDC/LDO

FC20 Module

VDD_3V3

SDIO_D3

SDIO_D2

SDIO_D1

SDIO_D0

SDIO_CLK

SDIO_CMD

WLAN_EN

32K HZ_IN

WAKE_ ON_WIRELE SS

COEX

COEX_ UART_RX

COEX_UART_TX

LTE_UART_TXD

LTE_UART_RXD

Figure 30: Reference Circuit of Wireless Connectivity Interfaces with FC20 Module

NOTES

1. FC20 module can only be used as a slave device.

2. When BT function is enabled on EC25 module, PCM_SYNC and PCM_CLK pins are only used to

output signals.

3. For more information about wireless connectivity interfaces, please refer to document [5].

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4. “*” means under development.

1)

5.

Pads 24~27 are multiplexing pins used for audio design on EC25 module and BT function on BT

module.

3.19.1. WLAN Interface

EC25 provides a low power SDIO 3.0 interface and control interface for WLAN design.

SDIO interface supports the SDR mode (up to 50MHz).

As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the

SDIO 3.0 specification, please comply with the following principles:

 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal

trace is 50Ω±10%.

 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,

 etc., as well as noisy signals such as clock signals, DCDC signals, etc.

 It is recommended to keep matching length between CLK andDATA/CMD less than 1mm and total

routing length less than 50mm.

 Keep termination resistors within 15Ω~24Ω on clock lines near the module and keep the route

distance from the module clock pins to termination resistors less than 5mm.

 Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than

15pF.



NOTE

WLAN is an optional function for EC25-AF which not included in current product.

3.19.2. BT Interface*

EC25 supports a dedicated UART interface and a PCM interface for BT application.

Further information about BT interface will be added in future version of this document.

NOTE

“*” means under development.

BT is an optional function for EC25-AF which not included in current product.

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3.20. USB_BOOT Interface

EC25 provides a USB_BOOT pin. Developers can pull up USB_BOOT to VDD_EXT before powering on

the module, thus the module will enter into emergency download mode when powered on. In this mode,

the module supports firmware upgrade over USB interface.

Table 24: Pin Definition of USB_BOOT Interface

Pin Name Pin No. I/O Description Comment

1.8V power domain.

USB_BOOT 115 DI

Force the module enter into

emergency download mode

The following figure shows a reference circuit of USB_BOOT interface.

Active high.

It is recommended to

reserve test point.

Module

VDD_EXT

Test point

USB_BOOT

Cl ose to tes t po in t

TVS

Figure 31: Reference Circuit of USB_BOOT Interface

4.7K

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4 GNSS Receiver

4.1. General Description

EC25 includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of

Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS).

EC25 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via

USB interface by default.

By default, EC25 GNSS engine is switched off. It has to be switched on via AT command. For more

details about GNSS engine technology and configurations, please refer to document [3].

4.2. GNSS Performance

The following table shows GNSS performance of EC25.

Table 25: GNSS Performance

Parameter Description Conditions Typ. Unit

Cold start Autonomous -146 dBm

Sensitivity

(GNSS)

TTFF

(GNSS)

Reacquisition Autonomous -157 dBm

Tracking Autonomous -157 dBm

Cold start

@open sky

Warm start

@open sky

Autonomous 35 s

XTRA enabled 18 s

Autonomous 26 s

XTRA enabled 2.2 s

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Autonomous 2.5 s

XTRA enabled 1.8 s

Autonomous

@open sky

<1.5 m

Accuracy

(GNSS)

Hot start

@open sky

CEP-50

NOTES

1. Tracking sensitivity: the lowest GNSSsignal value at the antenna port on which the module can keep

on positioning for 3 minutes.

2. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can

fix position again within 3 minutes after loss of lock.

3. Cold start sensitivity: the lowest GNSS signal value at the antenna port on which the module fixes

position within 3 minutes after executing cold start command.

4.3. Layout Guidelines

The following layout guidelines should be taken into account in customers’ designs.

 Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna.

 Digital circuits such as (U)SIM card, USB interface, camera module and display connector should be

kept away from the antennas.

 Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar

isolation and protection.

 Keep 50Ω characteristic impedance for the ANT_GNSS trace.

Please refer to Chapter 5 for GNSS antenna reference design and antenna installation information.

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5 Antenna Interfaces

EC25 antenna interfaces include a main antenna interface, an Rx-diversity antenna interface which is

used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS

antenna interface. The impedance of the antenna port is 50Ω.

5.1. Main/Rx-diversity Antenna Interfaces

5.1.1. Pin Definition

The pin definition of main antenna and Rx-diversityantenna interfaces is shown below.

Table 26: Pin Definition of RF Antenna

Pin Name Pin No. I/O Description Comment

ANT_MAIN 49 IO Main antenna pad 50Ω impedance

50Ω impedance

ANT_DIV 35 AI Receive diversity antenna pad

If unused, keep it

open.

5.1.2. Operating Frequency

Table 27: Module Operating Frequencies

3GPP Band Transmit Receive Unit

GSM850 824~849 869~894 MHz

EGSM900 880~915 925~960 MHz

DCS1800 1710~1785 1805~1880 MHz

PCS1900 1850~1910 1930~1990 MHz

WCDMA B1 1920~1980 2110~2170 MHz

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WCDMA B2 1850~1910 1930~1990 MHz

WCDMA B4 1710~1755 2110~2155 MHz

WCDMA B5 824~849 869~894 MHz

WCDMA B6 830~840 875~885 MHz

WCDMA B8 880~915 925~960 MHz

WCDMA B19 830~845 875~890 MHz

LTE FDD B1 1920~1980 2110~2170 MHz

LTE FDD B2 1850~1910 1930~1990 MHz

LTE FDD B3 1710~1785 1805~1880 MHz

LTE FDD B4 1710~1755 2110~2155 MHz

LTE FDD B5 824~849 869~894 MHz

LTE FDD B7 2500~2570 2620~2690 MHz

LTE FDD B8 880~915 925~960 MHz

LTE FDD B12 699~716 729~746 MHz

LTE FDD B13 777~787 746~756 MHZ

LTE FDD B14 788~798 758~768 MHZ

LTE FDD B18 815~830 860~875 MHz

LTE FDD B19 830~845 875~890 MHz

LTE FDD B20 832~862 791~821 MHz

LTE FDD B28 703~748 758~803 MHz

LTE TDD B38 2570~2620 2570~2620 MHz

LTE TDD B40 2300~2400 2300~2400 MHz

LTE TDD B41 2555~2655 2555~2655 MHz

LTE TDD B66 1710~1780 2100~2200 MHz

LTE TDD B71 663~698 617~652 MHz

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5.1.3. Reference Design of RF Antenna Interface

Areference design of ANT_MAIN and ANT_DIV antenna pads is shown as below. A π-type matching

circuit should be reserved for better RF performance. The capacitors are not mounted by default.

Figure 32: Reference Circuit of RF Antenna Interface

NOTES

1. Keep a proper distance between the main antenna and the Rx-diversity antenna to improve the

receiving sensitivity.

2. ANT_DIV function is enabled by default.

3. Place the π-type matching components (R1&C1&C2, R2&C3&C4) as close to the antenna as

possible.

5.1.4. Reference Design of RF Layout

For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The

impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,

the distance between signal layer and reference ground (H), and the clearance between RF trace and

ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic

impedance control. The following are reference designs of microstrip line or coplanar waveguide line with

different PCB structures

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.

Figure 33: Microstrip Line Design on a 2-layer PCB

Figure 34: Coplanar Waveguide Line Design on a 2-layer PCB

Figure 35: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground)

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Figure 36: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground)

In order to ensure RF performance and reliability, the following principles should be complied with in RF

layout design:

 Please use an impedance simulation tool to control the characteristic impedance of RF traces as

50Ω.

 The GND pins adjacent to RF pins should not be designed as thermal relief pads, and they should be

fully connected to ground.

 The distance between the RF pins and the RF connector should be as short as possible, and all the

right angle traces should be changed to curved ones.

 There should be clearance area under the signal pin of the antenna connector or solder joint.

 The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around

RF traces and the reference ground could help to improve RF performance. The distance between

the ground vias and RF traces should be no less than two times the width of RF signal traces (2*W).

For more details about RF layout, please refer to document [6].

5.2. GNSS Antenna Interface

The following tables show pin definition and frequency specification of GNSS antenna interface.

Table 28: Pin Definition of GNSS Antenna Interface

Pin Name Pin No. I/O Description Comment

ANT_GNSS 47 AI GNSS antenna

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50Ω impedance

If unused, keep it open.

LTE Module Series

EC25 Hardware Design

Table 29: GNSS Frequency

Type Frequency Unit

GPS/Galileo/QZSS 1575.42±1.023 MHz

GLONASS 1597.5~1605.8 MHz

BeiDou 1561.098±2.046 MHz

A reference design of GNSS antenna is shown as below.

Figure 37: Reference Circuit of GNSS Antenna

NOTES

1. An external LDO can be selected to supply power according to the active antenna requirement.

2. If the module is designed with a passive antenna, then the VDD circuit is not needed.

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5.3. Antenna Installation

5.3.1. Antenna Requirement

The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna.

Table 30: Antenna Requirements

Type Requirements

Frequency range: 1561MHz~1615MHz

Polarization: RHCP or linear

VSWR: < 2 (Typ.)

GNSS1)

Passive antenna gain: > 0dBi

Active antenna noise figure: < 1.5dB

Active antenna gain: > 0dBi

Active antenna embedded LNA gain: < 17 dB

VSWR: ≤ 2

Efficiency: > 30%

Max Input Power: 50W

Input Impedance: 50Ω

Cable Insertion Loss: < 1dB

GSM/WCDMA/LTE

(GSM850, GSM 900, WCDMA B5/B6/B8/B19,

LTE-FDD B5/B8/B12/B13/B14/B18/B19/B20/B26/B28/B71)

Cable Insertion Loss: < 1.5dB

(DCS1800, PCS1900, WCDMA B1/B2/B4,

LTE-FDD B1/B2/B3/B4/B66)

Cable Insertion loss: < 2dB

(LTE-FDD B7, LTE-TDD B38/B40/B41)

NOTE

1)

It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of

active antenna may generate harmonics which will affect the GNSS performance.

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5.3.2. Recommended RF Connector for Antenna Installation

If RF connector is used for antenna connection, it is recommended to use U.FL-R-SMT connector

provided by Hirose.

Figure 38: Dimensions of the U.FL-R-SMT Connector (Unit: mm)

U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.

Figure 39: Mechanicals of U.FL-LP Connectors

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The following figure describes the space factor of mated connector.

LTE Module Series

Figure 40: Space Factor of Mated Connector (Unit: mm)

For more details, please visit http://hirose.com

.

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6 Electrical, Reliability and Radio

Characteristics

6.1. Absolute Maximum Ratings

Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are

listed in the following table.

Table 31: Absolute Maximum Ratings

Parameter Min. Max. Unit

VBAT_RF/VBAT_BB -0.3 4.7 V

USB_VBUS -0.3 5.5 V

Peak Current of VBAT_BB 0 0.8 A

Peak Current of VBAT_RF 0 1.8 A

Voltage at Digital Pins -0.3 2.3 V

Voltage at ADC0 0 VBAT_BB V

Voltage at ADC1 0 VBAT_BB V

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6.2. Power Supply Ratings

Table 32: The Module Power Supply Ratings

Parameter Description Conditions Min. Typ. Max. Unit

The actual input voltages

VBAT_BB and

VBAT_RF

VBAT

must stay between the

minimum and maximum

values.

3.3 3.8 4.3 V

I

VBAT

Voltage drop during

burst transmission

Peak supply current

(during transmission

slot)

Maximum power control

level on EGSM900.

Maximum power control

level on EGSM900.

400 mV

1.8 2.0 A

USB_VBUS USB detection 3.0 5.0 5.25 V

6.3. Operation and Storage Temperatures

The operation and storage temperatures are listed in the following table.

Table 33: Operation and Storage Temperatures

Parameter Min. Typ. Max. Unit

OperationTemperature Range1) -35 +25 +75 ºC

Extended Operation Range2) -40 +85 ºC

Storage Temperature Range -40 +90 ºC

NOTES

1)

1.

Within operation temperature range, the module is 3GPP compliant.

2)

2.

Within extended temperature range, the module remains the ability to establish and maintain a

voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There

are also no effects on radio spectrum and no harm to radio network. Only one or more parameters

like P

might reduce in their value and exceed the specified tolerances. When the temperature

out

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returns to the normal operating temperature levels, the module will meet 3GPP specifications again.

6.4. Current Consumption

The values of current consumption are shown below.

Table 34: EC25-E Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 11 uA

I

VBAT

Sleep state

AT+CFUN=0 (USB disconnected)

1.16 mA

GSM DRX=2 (USB disconnected) 2.74 mA

GSM DRX=9 (USB disconnected) 2.0 mA

WCDMA PF=64 (USB disconnected) 2.15 mA

WCDMA PF=128 (USB disconnected) 1.67 mA

LTE-FDD PF=64 (USB disconnected) 2.60 mA

LTE-FDD PF=128 (USB disconnected) 1.90 mA

LTE-TDD PF=64 (USB disconnected) 2.79 mA

LTE-TDD PF=128 (USB disconnected) 2.00 mA

GSM DRX=5 (USB disconnected) 19.5 mA

GSM DRX=5 (USB connected) 29.5 mA

WCDMA PF=64 (USB disconnected) 21.0 mA

Idle state

WCDMA PF=64 (USB connected) 31.0 mA

LTE-FDD PF=64 (USB disconnected) 20.7 mA

LTE-FDD PF=64 (USB connected) 30.8 mA

LTE-TDD PF=64 (USB disconnected) 20.8 mA

EC25_Hardware_Design 79 / 112

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EC25 Hardware Design

LTE-TDD PF=64 (USB connected) 32.0 mA

EGSM900 4DL/1UL @33.22dBm 271.0 mA

EGSM900 3DL/2UL @33.0dBm 464.0 mA

EGSM900 2DL/3UL @30.86dBm 524.0 mA

GPRS data

transfer

(GNSS OFF)

EDGE data

transfer

(GNSS OFF)

EGSM900 1DL/4UL @29.58dBm 600 mA

DCS1800 4DL/1UL @29.92dBm 192.0 mA

DCS1800 3DL/2UL @29.84dBm 311.0 mA

DCS1800 2DL/3UL @29.67dBm 424.0 mA

DCS1800 1DL/4UL @29.48dBm 539.0 mA

EGSM900 4DL/1UL PCL=8 @27.40dBm 174.0 mA

EGSM900 3DL/2UL PCL=8 @27.24dBm 281.0 mA

EGSM900 2DL/3UL PCL=8 @27.11dBm 379.0 mA

EGSM900 1DL/4UL PCL=8 @26.99dBm 480.0 mA

DCS1800 4DL/1UL PCL=2 @25.82dBm 159.0 mA

DCS1800 3DL/2UL PCL=2 @25.85dBm 251.0 mA

WCDMA

datatransfer

(GNSS OFF)

LTE datatransfer

(GNSS OFF)

DCS1800 2DL/3UL PCL=2 @25.68dBm 340.0 mA

DCS1800 1DL/4UL PCL=2 @25.57dBm 433.0 mA

WCDMA B1 HSDPA @22.47dBm 613.0 mA

WCDMA B1 HSUPA @22.44dBm 609.0 mA

WCDMA B5 HSDPA @23.07dBm 671.0 mA

WCDMA B5 HSUPA @23.07dBm 669.0 mA

WCDMA B8 HSDPA @22.67dBm 561.0 mA

WCDMA B8 HSUPA @22.39dBm 557.0 mA

LTE-FDD B1 @23.27dBm 754.0 mA

LTE-FDD B3 @23.54dBm 774.0 mA

EC25_Hardware_Design 80 / 112

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EC25 Hardware Design

LTE datatransfer

(GNSS OFF)

GSM

voice call

WCDMA voice

call

LTE-FDD B5 @22.83dBm 762.0 mA

LTE-FDD B7 @23.37dBm 842.0 mA

LTE-FDD B8 @23.48dBm 720.0 mA

LTE-FDD B20 @22.75dBm 714.0 mA

LTE-TDD B38 @23.05dBm 481.0 mA

LTE-TDD B40 @23.17dBm 431.8 mA

LTE-TDD B41 @23.02dBm 480.0 mA

EGSM900 PCL=5 @33.08dBm 264.0 mA

DCS1800 PCL=0 @29.75dBm 190.0 mA

WCDMA B1 @23.22dBm 680.0 mA

WCDMA B5 @23.18dBm 677.0 mA

WCDMA B8 @23.54dBm 618.0 mA

Table 35: EC25-A Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 10 uA

AT+CFUN=0 (USB disconnected)

1.1 mA

WCDMA PF=64 (USB disconnected) 1.8 mA

Sleep state

WCDMA PF=128 (USB disconnected) 1.5 mA

LTE-FDD PF=64 (USB disconnected) 2.2 mA

I

VBAT

LTE-FDD PF=128 (USB disconnected) 1.6 mA

WCDMA PF=64 (USB disconnected) 21.0 mA

WCDMA PF=64 (USB connected) 31.0 mA

Idle state

LTE-FDD PF=64 (USB disconnected) 21.0 mA

LTE-FDD PF=64 (USB connected) 31.0 mA

EC25_Hardware_Design 81 / 112

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EC25 Hardware Design

WCDMA B2 HSDPA @21.9dBm 591.0 mA

WCDMA B2 HSUPA @21.62dBm 606.0 mA

WCDMA

WCDMA B4 HSDPA @22.02dBm 524.0 mA

datatransfer

(GNSS OFF)

WCDMA B4 HSUPA @21.67dBm 540.0 mA

WCDMA B5 HSDPA @22.71dBm 490.0 mA

WCDMA B5 HSUPA @22.58dBm 520.0 mA

LTE-FDD B2 @22.93dBm 715.0 mA

LTE datatransfer

(GNSS OFF)

LTE-FDD B4 @22.96dBm 738.0 mA

LTE-FDD B12 @23.35dBm 663.0 mA

WCDMA B2 @22.93dBm 646.0 mA

WCDMA voice

call

WCDMA B4 @23dBm 572.0 mA

WCDMA B5 @23.78dBm 549.0 mA

Table 36: EC25-V Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 10 uA

0.85 mA

Sleep state

AT+CFUN=0 (USB disconnected)

LTE-FDD PF=64 (USB disconnected) 2.0 mA

LTE-FDD PF=128 (USB disconnected) 1.5 mA

LTE-FDD PF=64 (USB disconnected) 20.0 mA

I

VBAT

LTE-FDD PF=64 (USB connected) 31.0 mA

WCDMA B2 HSUPA @21.62dBm 606.0 mA

Idle state

WCDMA B4 HSDPA @22.02dBm 524.0 mA

WCDMA B4 HSUPA @21.67dBm 540.0 mA

WCDMA B5 HSDPA @22.71dBm 490.0 mA

EC25_Hardware_Design 82 / 112

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EC25 Hardware Design

WCDMA B5 HSUPA @22.58dBm 520.0 mA

LTE

LTE-FDD B4 @23.14dBm 770.0 mA

datatransfer

(GNSS OFF)

LTE-FDD B13 @23.48dBm 531.0 mA

Table 37: EC25-J Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 10 uA

AT+CFUN=0 (USB disconnected)

1.1 mA

WCDMA PF=64 (USB disconnected) 1.9 mA

WCDMA PF=128 (USB disconnected) 1.5 mA

Sleep state

LTE-FDD PF=64 (USB disconnected) 2.5 mA

LTE-FDD PF=128 (USB disconnected) 1.8 mA

I

VBAT

LTE-TDD PF=64 (USB disconnected) 2.6 mA

LTE-TDD PF=128 (USB disconnected) 1.9 mA

WCDMA PF=64 (USB disconnected) 21.0 mA

WCDMA PF=64 (USB connected) 31.0 mA

LTE-FDD PF=64 (USB disconnected) 21.0 mA

Idle state

LTE-FDD PF=64 (USB connected) 32.0 mA

LTE-TDD PF=64 (USB disconnected) 21.0 mA

LTE-TDD PF=64 (USB connected) 32.0 mA

WCDMA B1 HSDPA @22.32dBm 550.0 mA

WCDMA B1 HSUPA @22.64dBm 516.0 mA

WCDMA

datatransfer

WCDMA B6 HSDPA @22.02dBm 524.0 mA

(GNSS OFF)

WCDMA B6 HSUPA @22.33dBm 521.0 mA

WCDMA B19 HSDPA @22.67dBm 517.0 mA

EC25_Hardware_Design 83 / 112

EC25 Hardware Design

LTE

datatransfer

(GNSS OFF)

LTE Module Series

WCDMA B19 HSUPA @22.33dBm 522.0 mA

LTE-FDD B1 @23.16dBm 685.0 mA

LTE-FDD B3 @23.22dBm 766.0 mA

LTE-FDD B8 @23.22dBm 641.0 mA

LTE-FDD B18 @23.35dBm 661.0 mA

LTE-FDD B19 @23.16dBm 677.0 mA

LTE-FDD B26 @22.87dBm 690.0 mA

LTE-TDD B41 @22.42dBm 439.0 mA

WCDMA B1 @22.33dBm 605.0 mA

WCDMA voice

call

WCDMA B6 @23.28dBm 549.0 mA

WCDMA B19 @23.28dBm 549.0 mA

Table 38: EC25-AU Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 11 uA

AT+CFUN=0

AT+CFUN=0 (USB disconnected)

1.3 mA

1.46 mA

GSM850 DRX=5 (USB disconnected) 1.8 mA

EGSM900 DRX=5 (USB disconnected) 2.0 mA

I

VBAT

DCS1800 DRX=5 (USB disconnected) 1.9 mA

Sleep state

PCS1900 DRX=5 (USB disconnected) 1.9 mA

WCDMA PF=64 (USB disconnected) 2.0 mA

WCDMA PF=128 (USB disconnected) 1.6 mA

LTE-FDD PF=64 (USB disconnected) 2.2 mA

LTE-FDD PF=128 (USB disconnected) 1.6 mA

EC25_Hardware_Design 84 / 112

Idle state

LTE Module Series

EC25 Hardware Design

LTE-TDD PF=64 (USB disconnected) 2.3 mA

LTE-TDD PF=128 (USB disconnected) 1.6 mA

EGSM900 DRX=5 (USB disconnected) 22.0 mA

EGSM900 DRX=5 (USB connected) 34.0 mA

WCDMA PF=64 (USB disconnected) 22.0 mA

WCDMA PF=64 (USB connected) 33.0 mA

LTE-FDD PF=64 (USB disconnected) 24.0 mA

LTE-FDD PF=64 (USB connected) 35.0 mA

LTE-TDD PF=64 (USB disconnected) 24.0 Ma

GPRS data

transfer

(GNSS OFF)

LTE-TDD PF=64 (USB connected) 35.0 mA

GSM850 1UL/4DL @32.53dBm 232.0 mA

GSM850 2UL/3DL @32.34dBm 384.0 mA

GSM850 3UL/2DL @30.28dBm 441.0 mA

GSM850 4UL/1DL @29.09dBm 511.0 mA

EGSM900 1UL/4DL @32.34dBm 241.0 mA

EGSM900 2UL/3DL @32.19dBm 397.0 mA

EGSM900 3UL/2DL @30.17dBm 459.0 mA

EGSM900 4UL/1DL @28.96dBm 533.0 mA

DCS1800 1UL/4DL @29.71dBm 183.0 mA

DCS1800 2UL/3DL @29.62dBm 289.0 mA

DCS1800 3UL/2DL @29.49dBm 392.0 mA

DCS1800 4UL/1DL @29.32dBm 495.0 mA

PCS1900 1UL/4DL @29.61dBm 174.0 mA

PCS1900 1UL/4DL @29.48dBm 273.0 mA

PCS1900 1UL/4DL @29.32dBm 367.0 mA

EC25_Hardware_Design 85 / 112

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EC25 Hardware Design

PCS1900 1UL/4DL @29.19dBm 465.0 mA

GSM850 1UL/4DL @27.09dBm 154.0 mA

GSM850 2UL/3DL @26.94dBm 245.0 mA

GSM850 3UL/2DL @26.64dBm 328.0 mA

GSM850 4UL/1DL @26.53dBm 416.0 mA

EGSM900 1UL/4DL @26.64dBm 157.0 mA

EGSM900 2UL/3DL @26.95dBm 251.0 mA

EGSM900 3UL/2DL @26.57dBm 340.0 mA

EDGE data

transfer

(GNSS OFF)

EGSM900 4UL/1DL @26.39dBm 431.0 mA

DCS18001 UL/4DL @26.03dBm 152.0 mA

DCS1800 2UL/3DL @25.62dBm 240.0 mA

DCS1800 3UL/2DL @25.42dBm 325.0 mA

DCS1800 4UL/1DL @25.21dBm 415.0 mA

PCS1900 1UL/4DL @25.65dBm 148.0 mA

PCS1900 1UL/4DL @25.63dBm 232.0 mA

PCS1900 1UL/4DL @25.54dBm 313.0 mA

PCS1900 1UL/4DL @25.26dBm 401.0 mA

WCDMA B1 HSDPA @22.34dBm 625.0 mA

WCDMA B1 HSUPA @21.75dBm 617.0 mA

WCDMA B2 HSDPA @22.51dBm 610.0 mA

WCDMA data

(GNSS OFF)

WCDMA B2 HSUPA @22. 14dBm 594.0 mA

WCDMA B5 HSDPA @22.98dBm 576.0 mA

WCDMA B5 HSUPA @22.89dBm 589.0 mA

WCDMA B8 HSDPA @22.31dBm 556.0 mA

WCDMA B8 HSUPA @22.11dBm 572.0 mA

EC25_Hardware_Design 86 / 112

LTE Module Series

EC25 Hardware Design

LTE-FDD B1 @23.28dBm 817.0 mA

LTE-FDD B2 @23.34dBm 803.0 mA

LTE-FDD B3 @23.2dBm 785.0 mA

LTE

datatransfer

(GNSS OFF)

GSM voice

call

WCDMA

voice call

LTE-FDD B4 @22.9dBm 774.0 mA

LTE-FDD B5 @23.45dBm 687.0 mA

LTE-FDD B7 @22.84dBm 843.0 mA

LTE-FDD B8 @22.92dBm 689.0 mA

LTE-FDD B28 @23.23dBm 804.0 mA

LTE-TDD B40 @23.3dBm 429.0 mA

GSM850 PCL5 @32.66dBm 228.0 mA

EGSM900 PCL5 @32.59dBm 235.0 mA

DCS1800 PCL0 @29.72dBm 178.0 mA

PCS1900 PCL0 @29.82dBm 170.0 mA

WCDMA B1 @23.27dBm 687.0 mA

WCDMA B2 @23.38dBm 668.0 mA

WCDMA B5 @23.38dBm 592.0 mA

WCDMA B8 @23.32dBm 595.0 mA

Table 39: EC25-AUT Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 10 uA

AT+CFUN=0 (USB disconnected)

1.0 mA

I

VBAT

Sleep state

WCDMA PF=64 (USB disconnected) 1.9 mA

WCDMA PF=128 (USB disconnected) 1.5 mA

LTE-FDD PF=64 (USB disconnected) 2.3 mA

LTE-FDD PF=128 (USB disconnected) 1.9 mA

EC25_Hardware_Design 87 / 112

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EC25 Hardware Design

I

VBAT

Idle state

WCDMA

datatransfer

(GNSS OFF)

LTE

datatransfer

(GNSS OFF)

WCDMA PF=64 (USB disconnected) 23.0 mA

WCDMA PF=64 (USB connected) 33.0 mA

LTE-FDD PF=64 (USB disconnected) 17.0 mA

LTE-FDD PF=64 (USB connected) 29.0 mA

LTE-TDD PF=64 (USB disconnected) 21.0 mA

LTE-TDD PF=64 (USB connected) 32.0 mA

WCDMA B1 HSDPA @22.24dBm 500.0 mA

WCDMA B1 HSUPA @22.05dBm 499.0 mA

WCDMA B5 HSDPA @22.39dBm 418.0 mA

WCDMA B5 HSUPA @22dBm 486.0 mA

LTE-FDD B1 @23.28dBm 707.0 mA

LTE-FDD B3 @23.36dBm 782.0 mA

LTE-FDD B5 @23.32dBm 588.0 mA

LTE-FDD B7 @23.08dBm 692.0 mA

LTE-FDD B28-A @23.37dBm 752.0 mA

LTE-FDD B28-B @23.48dBm 770.0 mA

WCDMA voice

call

WCDMA B1 @23.22dBm 546.0 mA

WCDMA B5 @23.01dBm 511.0 mA

Table 40: EC25-AF Current Consumption

Parameter Description Conditions Typ. Unit

OFF state Power down 10 uA

I

VBAT

Sleep state

AT+CFUN=0 (USB disconnected)

WCDMA PF=64 (USB disconnected) 1.8 mA

1.0 mA

WCDMA PF=128 (USB disconnected) 1.4 mA

EC25_Hardware_Design 88 / 112

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EC25 Hardware Design

I

VBAT

Idle state

WCDMA

datatransfer

(GNSS OFF)

LTE-FDD PF=64 (USB disconnected) 2.2 mA

LTE-FDD PF=128 (USB disconnected) 1.8 mA

WCDMA PF=64 (USB disconnected) 23.3 mA

WCDMA PF=64 (USB connected) 33.4 mA

LTE-FDD PF=64 (USB disconnected) 17.6 mA

LTE-FDD PF=64 (USB connected) 29.4 mA

WCDMA B2 HSDPA @22.36dBm 509.0 mA

WCDMA B2 HSUPA @22.27dBm 511.0 mA

WCDMA B4 HSDPA @22.22dBm 521.0 mA

WCDMA B4 HSUPA @22.31dBm 518.0 mA

WCDMA B5 HSDPA @22.39dBm 496.0 mA

LTE

datatransfer

(GNSS OFF)

WCDMA voice

call

WCDMA B5 HSUPA @22dBm 502.0 mA

LTE-FDD B2 @23.2dBm 600.0 mA

LTE-FDD B4 @23.85dBm 634.0 mA

LTE-FDD B5 @23.0dBm 600.0 mA

LTE-FDD B12 @23.08dBm 692.0 mA

LTE-FDD B13 @23.1dBm 660.0 mA

LTE-FDD B14 @23.5dBm 676.0 mA

LTE-FDD B66 @22.9dBm 662.0 mA

LTE-FDD B71 @22.88dBm 600.0 mA

WCDMA B2 @23.24dBm 570.0 mA

WCDMA B4 @23.2dBm 581.0 mA

WCDMA B5 @23.4dBm 500.0 mA

EC25_Hardware_Design 89 / 112

LTE Module Series

EC25 Hardware Design

Table 41: GNSS Current Consumption of EC25 Series Module

Parameter Description Conditions Typ. Unit

Cold start @Passive Antenna 54.0 mA

Lost state @Passive Antenna 53.9 mA

Instrument Environment 30.5 mA

Open Sky @Passive Antenna 33.2 mA

I

VBAT

(GNSS)

Searching

(AT+CFUN=0)

Tracking

(AT+CFUN=0)

Open Sky @Active Antenna 40.8 mA

6.5. RF Output Power

The following table shows the RF output power of EC25 module.

Table 42: RF Output Power

Frequency Max. Min.

GSM850/EGSM900 33dBm±2dB 5dBm±5dB

DCS1800/PCS1900 30dBm±2dB 0dBm±5dB

GSM850/EGSM900 (8-PSK) 27dBm±3dB 5dBm±5dB

DCS1800/PCS1900 (8-PSK) 26dBm±3dB 0dBm±5dB

WCDMA bands 24dBm+1/-3dB <-49dBm

LTE-FDD bands 23dBm±2dB <-39dBm

LTE-TDD bands 23dBm±2dB <-39dBm

NOTE

In GPRS 4 slots TX mode, the maximum output power is reduced by 3dB. The design conforms to the

GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1.

EC25_Hardware_Design 90 / 112

LTE Module Series

EC25 Hardware Design

6.6. RF Receiving Sensitivity

The following tables show conducted RF receiving sensitivity of EC25 series module.

Table 43: EC25-E Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

EGSM900 -109.0dBm / / -102.0dBm

DCS1800 -109.0dBm / / -102.0dbm

WCDMA B1 -110.5dBm / / -106.7dBm

WCDMA B5 -110.5dBm / / -104.7dBm

WCDMA B8 -110.5dBm / / -103.7dBm

LTE-FDD B1 (10M) -98.0dBm -98.0dBm -101.5dBm -96.3dBm

LTE-FDD B3 (10M) -96.5dBm -98.5dBm -101.5dBm -93.3dBm

LTE-FDD B5 (10M) -98.0dBm -98.5dBm -101.0dBm -94.3dBm

LTE-FDD B7 (10M) -97.0dBm -94.5dBm -99.5dBm -94.3dBm

LTE-FDD B8 (10M) -97.0dBm -97.0dBm -101.0dBm -93.3dBm

LTE-FDD B20 (10M) -97.5dBm -99.0dBm -102.5dBm -93.3dBm

LTE-TDD B38 (10M) -96.7dBm -97.0dBm -100.0dBm -96.3dBm

LTE-TDD B40 (10M) -96.3dBm -98.0dBm -101.0dBm -96.3dBm

LTE-TDD B41 (10M) -95.2dBm -95.7dBm -99.0dBm -94.3dBm

Table 44: EC25-A Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

WCDMA B2 -110.0dBm / / -104.7dBm

WCDMA B4 -110.0dBm / / -106.7dBm

WCDMA B5 -110.5dBm / / -104.7dBm

EC25_Hardware_Design 91 / 112

LTE Module Series

EC25 Hardware Design

LTE-FDD B2 (10M) -98.0dBm -98.0dBm -101.0dBm -94.3dBm

LTE-FDD B4 (10M) -97.5dBm -99.0dBm -101.0dBm -96.3dBm

LTE-FDD B12 (10M) -96.5dBm -98.0dBm -101.0dBm -93.3dBm

Table 45: EC25-V Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

LTE-FDD B4 (10M) -97.5dBm -99.0dBm -101.0dBm -96.3dBm

LTE-FDD B13 (10M) -95.0dBm -97.0dBm -100.0dBm -93.3dBm

Table 46: EC25-J Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

WCDMA B1 -110.0dBm / / -106.7dBm

WCDMA B6 -110.5dBm / / -106.7dBm

WCDMA B8 -110.5dBm / / -103.7dBm

WCDMA B19 -110.5dBm / / -106.7dBm

LTE-FDD B1 (10M) -97.5dBm -98.7dBm -100.2dBm -96.3dBm

LTE-FDD B3 (10M) -96.5dBm -97.1dBm -100.5dBm -93.3dBm

LTE-FDD B8 (10M) -98.4dBm -99.0dBm -101.2dBm -93.3dBm

LTE-FDD B18 (10M) -99.5dBm -99.0dBm -101.7dBm -96.3dBm

LTE-FDD B19 (10M) -99.2dBm -99.0dBm -101.4dBm -96.3dBm

LTE-FDD B26 (10M) -99.5dBm -99.0dBm -101.5dBm -93.8dBm

LTE-TDD B41 (10M) -95.0dBm -95.7dBm -99.0dBm -94.3dBm

EC25_Hardware_Design 92 / 112

LTE Module Series

EC25 Hardware Design

Table 47: EC25-AU Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

GSM850 -109.0dBm / / -102.0dBm

EGSM900 -109.0dBm / / -102.0dBm

DCS1800 -109.0dBm / / -102.0dBm

PCS1900 -109.0dBm / / -102.0dBm

WCDMA B1 -110.0dBm / / -106.7dBm

WCDMA B2 -110.0dBm / / -104.7dBm

WCDMA B5 -111.0dBm / / -104.7dBm

WCDMA B8 -111.0dBm / / -103.7dBm

LTE-FDD B1 (10M) -97.2dBm -97.5dBm -100.2dBm -96.3dBm

LTE-FDD B2 (10M) -98.2dBm / / -94.3dBm

LTE-FDD B3 (10M) -98.7dBm -98.6dBm -102.2dBm -93.3dBm

LTE-FDD B4 (10M) -97.7dBm -97.4dBm -100.2dBm -96.3dBm

LTE-FDD B5 (10M) -98.0dBm -98.2dBm -101.0dBm -94.3dBm

LTE-FDD B7 (10M) -97.7dBm -97.7dBm -101.2dBm -94.3dBm

LTE-FDD B8 (10M) -99.2dBm -98.2dBm -102.2dBm -93.3dBm

LTE-FDD B28 (10M) -98.6dBm -98.7dBm -102.0dBm -94.8dBm

LTE-TDD B40 (10M) -97.2dBm -98.4dBm -101.2dBm -96.3dBm

Table 48: EC25-AUT Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

WCDMA B1 -110.0dBm / / -106.7dBm

WCDMA B5 -110.5dBm / / -104.7dBm

LTE-FDD B1 (10M) -98.5dBm -98.0dBm -101.0dBm -96.3dBm

EC25_Hardware_Design 93 / 112

LTE Module Series

EC25 Hardware Design

LTE-FDD B3 (10M) -98.0dBm -96.0dBm -100.0dBm -93.3dBm

LTE-FDD B5 (10M) -98.0dBm -99.0dBm -102.5dBm -94.3dBm

LTE-FDD B7 (10M) -97.0dBm -95.0dBm -98.5dBm -94.3dBm

LTE-FDD B28 (10M) -97.0dBm -99.0dBm -102.0dBm -94.8dBm

Table 49: EC25-AUTL Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

LTE-FDD B3 (10M) -98.0dBm -96.0dBm -100.0dBm -93.3dBm

LTE-FDD B7 (10M) -97.0dBm -95.0dBm -98.5dBm -94.3dBm

LTE-FDD B28 (10M) -97.0dBm -99.0dBm -102.0dBm -94.8dBm

Table 50: EC25-AF Conducted RF Receiving Sensitivity

Frequency Primary Diversity SIMO1) 3GPP (SIMO)

WCDMA B2 -109.5dBm -111dbm -113dbm -104.7dBm

WCDMA B4 -108dBm -111dbm -111.5dbm -106.7dBm

WCDMA B5 -110.5dBm -111.5dbm -114dbm -104.7dBm

LTE-FDD B2 (10M) -98.2dBm -99.1dBm -101.7dBm -94.3dBm

LTE-FDD B4 (10M) -97.3dBm -98.6dBm -101.1dBm -96.3dBm

LTE-FDD B5 (10M) -99dBm -100.3dBm -101.3dBm -94.3Bm

LTE-FDD B12 (10M) -99dBm -99.2dBm -102.1dBm -93.3dBm

LTE-FDD B13 (10M) -98.1dBm -98.4dBm -100.2dBm -93.3dBm

LTE-FDD B14 (10M) -97.9dBm -98.6dBm -99.5dBm -93.3dBm

LTE-FDD B66 (10M) -96.7dBm -98.1dBm -99.4dBm -96.5dBm

LTE-FDD B71 (10M) -99.2dBm -99.4dBm -101.5dBm -94.2dBm

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NOTE

1)

SIMO is a smart antenna technology that uses a single antenna at the transmitter side and two

antennas at the receiver side, which can improve RX performance.

6.7. Electrostatic Discharge

The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject

to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and

packaging procedures must be applied throughout the processing, handling and operation of any

application that incorporates the module.

The following table shows the module electrostatics discharge characteristics.

Table 51: Electrostatics Discharge Characteristics

Tested Points Contact Discharge Air Discharge Unit

VBAT, GND ±5 ±10 kV

All Antenna Interfaces ±4 ±8 kV

Other Interfaces ±0.5 ±1 kV

6.8. Thermal Consideration

In order to achieve better performance of the module, it is recommended to comply with the following

principles for thermal consideration:

 On customers’ PCB design, please keep placement of the module away from heating sources,

especially high power components such as ARM processor, audio power amplifier, power supply,

etc.

 Do not place components on the opposite side of the PCB area where the module is mounted, in

order to facilitate adding of heatsink when necessary.

 Do not apply solder mask on the opposite side of the PCB area where the module is mounted, so as

to ensure better heat dissipation performance.

 The reference ground of the area where the module is mounted should be complete, and add ground

vias as many as possible for better heat dissipation.

 Make sure the ground pads of the module and PCB are fully connected.

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 According to customers’ application demands, the heatsink can be mounted on the top of the module,

or the opposite side of the PCB area where the module is mounted, or both of them.

 The heatsink should be designed with as many fins as possible to increase heat dissipation area.

Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and

module/PCB.

The following shows two kinds of heatsink designs for reference and customers can choose one or both

of them according to their application structure.

Figure 41: Referenced Heatsink Design (Heatsink at the Top of the Module)

Figure 42: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB)

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NOTE

The module offers the best performance when the internal BB chip stays below 105°C. When the

maximum temperature of the BB chip reaches or exceeds 105°C, the module works normal but provides

reduced performance (such as RF output power, data rate, etc.). When the maximum BB chip

temperature reaches or exceeds 115°C, the module will disconnect from the network, and it will recover to

network connected state after the maximum temperature falls below 115°C. Therefore, the thermal design

should be maximally optimized to make sure the maximum BB chip temperature always maintains below

105°C. Customers can execute AT+QTEMP command and get the maximum BB chip temperature from

the first returned value.

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7 Mechanical Dimensions

This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm.

The tolerances for dimensions without tolerance values are ±0.05mm.

7.1. Mechanical Dimensions of the the Module

29.0±0.15

32.0± 0 .15

Figure 43: Module Top and Side Dimensions

2.4±0.2

0.8

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Figure 44: Module Bottom Dimensions (Bottom View)

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