PIONEER CX-3007 Service Manual

PIONEER CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan

PIONEER ELECTRONICS (USA) INC. P.O.Box 1760, Long Beach, CA 90801-1760 U.S.A. PIONEER EUROPE NV Haven 1087 Keetberglaan 1, 9120 Melsele, Belgium PIONEER ELECTRONICS ASIACENTRE PTE.LTD. 253 Alexandra Road, #04-01, Singapore 159936

C PIONEER CORPORATION 2002

K-ZZA. JAN. 2002 Printed in Japan

ORDER NO.

CRT2820

Model Service Manual CD Mechanism Module DEH-P740MP/XN/UC CRT2783 CXK5555 DEH-P7400MP/XN/UC DEH-P7450MP/XN/ES DEH-P7400MP/XN/EW CRT2784

CD MECHANISM MODULE

CX-3007

- This service manual describes the operation of the CD mechanism module incorporated in models

listed in the table below.

- When performing repairs use this manual together with the specific manual for model under repair.

CONTENTS

1. CIRCUIT DESCRIPTIONS ...........................................2

2. MECHANISM DESCRIPTIONS.................................18

3. DISASSEMBLY .........................................................20

C X-3007

1. CIRCUIT DESCRIPTIONS

Recently, most CD LSI's have included DAC, RF amplifier and other peripheral circuits, as well as the core circuit DSP.

This series of mechanisms employ a multi-task LSI UPD63760GJ, which has CD-ROM decoder and MP3 decoder in

addition to the CD block as shown in the Fig.1.0.1. This enables to reproduce a CD-ROM where MP3 data is recorded.

Plus, in this lineup, there are WMA supported models available where WMA decoder UPD61002GC is added.

CXK5555 --- WMA non-supported

CXK5556 and CXK5557 --- WMA supported

Fig.1.0.1 Block diagram of CD LSI UPD63760GJ

DRAM

A - F

RF AMPLIFIER

EFM

DRIVE OUTPUT

DIGITAL SERVO

CD-ROM DECODER

SIGNAL PROCESSOR

UCOM

BMC

MP3 DECODER

AUDIO OUTPUT

DAC

UPD63760GJ

C X-3007

1.1 PREAMPLIFIER BLOCK (UPD63760GJ: IC201)

In the preamplifier block, the pickup output signals are processed to generate signals that are used for the next-stage

blocks: the servo block, demodulator, and control.

After I/V-converted by the preamplifier with built-in photo detectors (inside the pickup), the signals are applied to the

preamplifier block in the CD LSI UPD63760GJ (IC201). After added by the RF amplifier in this block, these signals are

used to produce necessary signals such as RF, FE, TE, and TE zero-cross signals.

The CD LSI employs a single power supply system of + 3.3V. Therefore, the REFO (1.65V) is used as the reference

voltage both for this CD LSI and the pickup. The LSI produces the REFO signal by using the REFOUT via the buffer

amplifier and outputs from the pin 131. All the measurements should be made based on this REFO.

Caution: Be careful not to short the REFO and GRD when measuring.

1.1.1 APC (Automatic Power Control)

A laser diode has extremely negative temperature characteristics in optical output at constant-current drive. To keep

the output constant, the LD current is controlled by monitor diodes. This is called the APC circuit. The LD current is

calculated at about 30mA, which is the voltage between LD1 and V3R3D divided by 7.5 (ohms).

Fig. 1.1.1 APC

PICKUP UNIT

LD-

LD+

UNIT

14 14

141

R001

1R5 x 5

R1 R1

100/16

2SB1132

1SS355

140

LDREGO

142

143

UPD63760GJ

REG 1R25V

LDS

6R5K

110K

6R5K

Vref

APN

100K

C X-3007

1.1.2 RF and RFAGC amplifiers

The photo-detector outputs (A + C) and (B + D) are added, amplified, and equalized inside this LSI, and then provided

as the RF signal from the RFI terminal. The RF signal can be used for eye-pattern check.

The low frequency component of the RFO voltage is:

RFO = (A + B + C + D) x 2

The RFO is used for the FOK generation circuit and RF offset adjustment circuit.

The RFI output from the pin 118 is A/C-coupled outside this LSI, and returned to the pin 117 of this LSI. The signal is

amplified in the RFAGC amplifier to obtain the RFAGC signal. This LSI is equipped with the RFAGC auto-adjustment

function as explained below. This function automatically controls the RFO level to keep at 1.5V by switching the

feedback gain for the RFAGC amplifier.

The RFO signal is also used for the EFM, DFCT, MIRR, and RFAGC auto-adjustment circuits.

Fig. 1.1.2 RF/AGC/FE

PICKUP UNIT

VREF

A+C

B+C

RFO

18K

117

AGCI

20K 11R2K

RFOFF SETTING

7R05K

VREF

10K 10K

DEFECT/ A3T DETECTION

RFOK GENERATION

RF2-

RF-

EQ2

EQ1

AGCO

FEO

FE A/D

FE-

121

122

119

120

116

134

133

330

1R8K

R01

18P

27P

10K

UNIT

VREF

UPD63760GJ

124

10k

125

10k

127

10K

126

10K

8R8K

15R2K

61R0K

15R2K

118

35K

RFOFF SETTING

111K

C X-3007

1.1.3 Focus error amplifier

The photo-detector outputs (A + C) and (B + D) are applied to the differential amplifier and the error amplifier to obtain

the (A + C - B - D) signal, which is then provided from the pin 91 as the FE signal.

The low frequency component of the FE voltage is:

FE = (A + C - B - D) x 8.8/10k x 111k/61k x 160k/72k

= (A + C - B - D) x 3.5

The FE output shows 1.5Vp-p S-shaped curve based on the REFO. For the next-stage amplifiers, the cutoff frequency

is 14.6kHz.

1.1.4 RFOK

The RFOK circuit generates the RFOK signal, which indicates focus-close timing and focus-close status during the play

mode, and outputs from the pin 53. This signal is shifted to "H" when the focus is closed and during the play mode.

The DC level of the RFI signal is peak-held in the digital block and compared with a certain threshold level to generate

the RFOK signal. Therefore, even on a non-pit area or a mirror-surface area of a disc, the RFOK becomes "H" and the

focus is closed.

This RFOK signal is also applied to the microcomputer via the low-pass filer as the FOK signal, which is used for

protection and RF amplifier gain switching.

1.1.5 Tracking error amplifier

The photo-detector outputs E and F are applied to the differential amplifier and the error amplifier to obtain the (E - F)

signal, and then provided from the pin 136 as the TE signal.

The low frequency component of the TE voltage is:

FEO = (E - F) x 160k/112k x 90.6k/45.36k x 160k/45.4k

= (E - F) x 5.7

The TE output provides the TE waveform of about 1.3Vp-p based on the REFO. For the next-stage amplifiers, the

cutoff frequency is 21.1kHz.

Fig. 1.1.3 TE

UPD63760GJ

128

112K

129

112K

160K

160K 160K

45R36K

TEOFF SETTING

80K

90R6K

TE A/D

160K

60K

136

135

137

138

TEO

TE-

TE2

TEC

PICKUP UNIT

P10

UNIT

VREF

68P

6800P

VREF

INTERNAL TEC

C X-3007

1.1.6 Tracking zero-cross amplifier

The tracking zero-cross signal (hereinafter TEC signal) is obtained by amplifying the TE signal 4 times, and used to

detect the tracking-error zero-cross point.

By using the information on this point, the following two operations can be performed:

1. Track counting in the carriage move and track jump modes

2. Sensing the lens-moving direction at the moment of the tracking close (The sensing result is used for the tracking

brake circuit as explained below.)

The frequency range of the TEC signal is between 300Hz and 20kHz.

TEC voltage = TE level x 4

The TEC level can be calculated at 5.2V. This level exceeds the D range of the operation amplifier, and the signal gets

clipped. However, it can be ignored because the CD LSI only uses the signal at the zero-cross point.

1.1.7 EFM

The EFM circuit converts the RF signal into a digital signal expressed in binary digits 0 and 1. The AGCO output from

the pin 116 is A/C-coupled in the peripheral circuit, fed back to the LSI from the pin 115, and sent to the EFM circuit

inside the LSI.

On scratched or dirty discs, part of the RF signal recorded may be missing. On other discs, part of the RF signal

recorded may be asymmetric, which was caused by dispersion in production quality. Such lack of information cannot

be completely eliminated by this AC coupling process. Therefore, by utilizing the fifty-fifty occurrence ratio of binary

digits (0 and 1) in the EFM signal, the EFM comparator reference voltage ASY is controlled, so that the comparator

level always stays around the center of the RFO signal. The reference voltage ASY is made from the EFM comparator

output via the low-pass filter. The EFM signal is put out from the pin 111.

Fig. 1.1.4 EFM

RFI

115

40K

Vdd

112

111

ASY

EFM

UPD63760GJ

EFM SIGNAL

1R5K 7R5K

C X-3007

1.2 SERVO BLOCK (UPD63760GJ: IC201)

The servo block controls the servo systems for error signal equalizing, in-focus, track jump and carriage move and so

on. The DSP block is a signal-processing block, where data decoding, error correction, and compensation are

performed.

After A/D-converted, the FE and TE signals (generated in the preamplifier block) are applied to the servo block and

used to generate the drive signals for the focus, tracking, and carriage servos.

The EFM signal is decoded in the DSP block, and finally sent out as the audio signal after D/A-converted. In this

decoding process, the spindle servo error signal is generated, supplied to the spindle servo block, and used to

generate the spindle drive signal.

The drive signals for focus, tracking, carriage, and spindle servos (FD, TD, SD, and MD) are provided as PWM3 data,

and then converted to the analog data by the low-pass filter in the driver IC BA5996FM (IC301). These analog drive

signals can be monitored by the FIN, TIN, CIN, and SIN signals respectively. Afterwards, the signals are amplified and

applied to each servo's actuator and motor.

1.2.1 Focus servo system

In the focus servo system, the digital equalizer block works as its main equalizer. The figure 1.2.1 shows the block

diagram of the focus servo system.

To close the focus loop circuit, the lens should be moved to within the in-focus range. While moving the lens up and

down by using the focus search triangular signal, the system tries to find the in-focus point. In the meantime, the

spindle motor rotation is kept at the prescribed one by using the kick mode.

The servo LSI monitors the FE and RFOK signals and automatically performs the focus close operations at an

appropriate timing. The focus loop will close when the following three conditions are satisfied at the same time:

1) The lens moves toward the disc surface.

2) The RFOK signal is shifted to "H".

3) The FE signal is zero-crossed. At last, the FE signal comes to the zero level (or REFO).

When the focus loop is closed, the FSS bit is shifted from "H" to "L". The microcomputer starts monitoring the RFOK

signal obtained through the low-pass filter 10msec after that.

If the RFOK signal is detected as "L", the microcomputer will take several actions including protection.

The timing chart for focus close operations is shown in fig. 1.2.2. (This shows the case where the system fails focus

close.)

In the test mode, the S-shaped curve, search voltage, and actual lens movement can be confirmed by pressing the

focus close button when the focus mode selector displays 01.

Fig. 1.2.1 Block diagram of the focus servo system

IC201 UPD63760GJ

A+C

B+D

124

127

AMP

WAVE GENERATOR

A/D

FOCUS SEARCH

TRIANGULAR

DIG.

CONTROL

105

PWM

IC301 BA5996FM

FOP

LENS

FOM

+ 15 hidden pages