Service
Manual
ORDER NO.
CRT2653
MD MECHANISM MODULE
CX-1020
NOTE:
-This Service Manual describes the operations of the MD mechanism module being used for the models listed in the Table indicated below.
-Be sure to reference this service manual as well as the service manual prepared for respective models must be referenced before implementing the repair work.
MODEL |
SERVICE MANUAL |
MD MECHANISM MODULE |
MEH-P7300R/EW |
CRT2660 |
CXK3320 |
MEH-P7350/ES |
CRT2660 |
CXK3320 |
MEH-P5350/ES |
CRT2654 |
CXK3310 |
CONTENTS
1. |
CIRCUIT DESCRIPTIONS ........................................... |
2 |
2. |
MECHANISM DESCRIPTIONS................................. |
12 |
3. |
DISASSEMBLY ......................................................... |
15 |
PIONEER CORPORATION 4-1, Meguro 1-Chome, Meguro-ku, Tokyo 153-8654, Japan
PIONEER ELECTRONICS SERVICE INC. P.O.Box 1760, Long Beach, CA 90801-1760 U.S.A.
PIONEER EUROPE NV Haven 1087 Keetberglaan 1, 9120 Melsele, Belgium
PIONEER ELECTRONICS ASIACENTRE PTE.LTD. 253 Alexandra Road, #04-01, Singapore 159936
C PIONEER CORPORATION 2001 |
K-ZZU. MAR. 2001 Printed in Japan |
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CX-1020
1. CIRCUIT DESCRIPTIONS
1.1 RF AMPLIFIER BLOCK (CXA2523AR : IC101)
This section works to process the output signals from the MD pickup to generate signals to be transferred to the next stage, namely, the DSP section (IC201).
Respective photo-detector output signals A, B, C, D, E and F are I-V converted and processed inside the RF amplifier to become FE, TE and ADIP signals.
Also, I and J outputs which have been I-V converted by the amplifier incorporating the photo-detector inside the pickup are processed to become the RF signals and the PEAK and BOTM signals.
Meanwhile, since this system is of the single power (+3.3V) specification, the reference voltage for the servo-signals is Vc (1.65V).
Vc is being output from this RF amplifier (IC101, 3pin).
(Note) Do not short the Vc and GND while making measurements.
Fig. 1 : CXA2523AR BLOCK DIAGRAM
2
CX-1020
1) APC (Automatic Power Control) Circuit
Since laser diode (LD) has temperature characteristics, the APC circuit is provided to control current flow using the monitor diode so that the output may be kept at a constant level.
LD current is determined by measuring voltage across V1 and 3VD.
The current value should be approximately 40 mA (0.4V/10Ω ).
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3VD |
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R105 470K |
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C108 R001 |
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C106 |
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1.25V |
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100/6R3 |
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R103 10 |
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21 |
VREF |
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R106 |
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APC REF |
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VI |
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6R8K |
APC |
R104 |
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R101 |
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– |
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PD 10 |
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11 |
680 |
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C105 |
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47K |
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3VD |
R1 |
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C107 |
22P |
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3VD |
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12 |
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LD+ |
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14 |
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Q102 |
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CXA2523AR |
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UMD2N |
6 |
5 |
4 |
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LD |
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2 |
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PU unit |
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MD |
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LDCNT |
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MON |
19 |
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Vr |
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1 |
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3 |
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20 |
6 |
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13 |
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GND |
GND |
LD – |
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2) RF Amplifier
I and J signals being I-J converted in the pickup are entered to 1 and 2 pins. Then, their difference signal (group signal) and sum signal (bit signal) are generated on RFA1 and RFA2, respectively.
RFA2 and RFA3 are switching operational amplifiers. The amplifiers detect high reflection (Premastered) and low reflection (Recordable) using the disc detector switch (S404) to switch to the gain selected by the serial command HLPT or PTGR.
RF signal (46 pin) is operated and conducted to the AGC circuit and equalizer via C112 to generate RF signal (36 pin). RF signal is maintained essentially at a constant level (approximately at 1.1 Vpp) by the AGC circuit.
This signal is entered to the signal processing LSI (IC201: 102 pins) for the data processing as well as control of the Premastered Disc playing spindle.
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C111 |
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MORFO |
R047 |
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48 |
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J |
2 |
– |
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I |
1 |
+ |
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RFA1 |
GRV |
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–1 |
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–1 |
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ABCD |
–2 |
GRVA |
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OFST |
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HLPT |
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–1 |
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–1 |
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–2 |
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–2 |
RFA2 |
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C112 |
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MORFI |
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RFO |
R022 |
AGCI |
RFAGC |
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47 |
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46 |
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40 |
39 |
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–2 |
PTGR |
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RF |
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–1 |
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AGC |
EQA |
38 |
<To IC201> |
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EQADJ |
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RFA3 |
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22 |
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–2 |
PBH1 |
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PEAK |
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20 |
F0CNT |
Peak/Bottom |
37 |
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23 |
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–1 |
Hold |
36 |
BOTM |
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3TADJ |
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PBSW |
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F0CNT |
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20 |
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25 |
WBLADJ |
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BPF |
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Peak |
I3 |
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fo=720kHz |
Hold |
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BPF3T |
PEAK3T |
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3
CX-1020
3) I-V, ADIP, ABCD and FE Amplifier Blocks
They are used for I-V conversion of photo-detector signals (A to F pins) from the pickup.
ADIP, FE and full quantity of light signals are generated from A to D signals, and TE signal is generated from E and F signals.
The ABCD amplifier generates the full quantity of light signal for the main spot. This signal is sum of A to D signals after I-V conversion. According to the level of the full quantity of light signal, resistance value of I-V is automatically adjusted so that ADIP, FE and TE signals may be maintained at the specified level.
FE and TE signals output from both the Recordable and Premastered Discs are adjusted to approximately 1 Vpp and 1.7 Vpp, respectively. This adjustment is executed whenever a disc is inserted.
ABCD signal entered to the signal processing LSI (IC201: 82 pins) is also used for generating FOK and defect detect signals.
The ADIP amplifier is used for generating ADIP signal that is present only on the Recordable Disc.
Addresses are already recorded on the Recordable Disc by wobbling FM signal that uses 22.05 KHz as the carrier. In order to detect wobble elements, noise elements of the signal are eliminated on the BPF, then the signal is output to the ADFM via the AGC. The signal is then sent to C119 for DC cut and binary converted on the comparator to generate ADFG signal. ADFG signal is entered to the signal processing LSI (IC201: 67 pins) to control the address and spindle when the Recordable Disc is played.
I-V amplifier
A 4
IVR0-IVR4
B 5
IVR0-IVR4
C 6
IVR0-IVR4
D 7
IVR0-IVR4
ADIP amplifier |
ADDC |
ADAGC |
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AIV |
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BPF22 |
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AA |
BB |
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BPF |
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ADFM |
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CC |
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AGC |
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AA |
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fo=22.05kHz |
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ADIPAGC |
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C119 |
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DD |
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ATA |
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BIV |
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4700P |
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BB |
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30 |
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ADIN |
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BPFC |
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ADFG |
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CIV |
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COMP |
32 |
<To IC201 67 pins> |
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CC |
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– |
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25 |
20 |
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F0CNT |
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WBLADJ |
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+DIV
DD
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Focus err amplifier
ABCD amplifier |
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AA |
– |
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FE R207 |
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CC |
– |
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BB |
+ |
34 |
<To IC201 83 pins> |
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DD |
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100 |
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FEA |
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AA |
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ABCD |
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BB |
– |
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35 <To IC201 82 pins> |
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CC |
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DD |
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ABCDA
4
CX-1020
4) TE and SE Amplifiers
Side spot E and F signals are I-V converted, then entered to the EF balance adjusting amplifier. Then, after polarity of the tracking error signal is switched by the TE differential amplifier (TESW), the signal is conducted to the gain amplifier to generate TE signal.
Select PTGR = 1 for the Pit play and PTGR = 2 for the group play.
The EF balance adjusting amplifier automatically adjusts an EF balance resistance value so that level of SE signal becomes the same as the reference voltage Vc when the TRKG made is open.
The SE amplifier generates TE signal from the LPF, then enters it into the signal processing LSI (IC201: 91 pins) for digital equalizing.
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Condition |
PTGR |
HLPT |
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PremasterdDisc |
Pit |
High reflection |
1 |
2 |
RecordableDisc |
Pit |
Low reflection |
1 |
1 |
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Groove |
Low reflection |
2 |
1 |
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C120 |
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R1 |
CSLED |
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27 |
TG |
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EIV |
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— 1 |
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SE |
E |
8 |
+ |
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— 2 |
28 |
<To IC201 91 pins> |
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EE |
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— |
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SEA |
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IVR0-IVR4 |
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Pit / GR Select |
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EFB0-EFB4 |
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PTGR |
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F |
9 |
+ |
FIV |
EE |
— 1 |
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Pit |
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FF |
FF |
+1 |
— 1 |
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TE R208 |
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IVR0-IVR4 |
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+2 |
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GR |
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26 |
<To IC201 92 pins> |
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— 2 |
TESW |
— 2 |
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100 |
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TEA |
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5
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