Philips UDA1328T Datasheet

INTEGRATED CIRCUITS

DATA SHEET

UDA1328T

Multi-channel filter DAC

Preliminary specification			1999 Oct 12
File under Integrated Circuits, IC01

Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

CONTENTS

1 FEATURES

1.1General

1.2Multiple format input interface

1.3Multi-channel DAC

1.4Advanced audio configuration

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5QUICK REFERENCE DATA

6BLOCK DIAGRAM

7PINNING

8FUNCTIONAL DESCRIPTION

8.1System clock

8.2Application modes

8.3Interpolation filter (DAC)

8.4Digital silence detection

8.5Noise shaper

8.6Filter Stream DAC

8.7Static Mode

8.7.1System clock setting

8.7.2De-emphasis control

8.7.3Digital interface formats

8.8L3 mode

8.8.1Digital interface formats

8.8.2L3 address

9	L3 INTERFACE DESCRIPTION

9.1Address mode

9.2Data transfer mode

9.2.1Programming the sound processing and other features

9.2.2Reset bit

9.2.3System clock frequency

9.2.4Data input format

9.2.5Quick mute

9.2.6Power control

9.3Feature settings

9.3.1Volume control

9.3.2Sub volume control

9.3.3Mute

9.3.4Digital silence mode

9.3.5De-emphasis

9.3.6Output polarity control

10LIMITING VALUES

11HANDLING

12THERMAL CHARACTERISTICS

13QUALITY SPECIFICATION

14DC CHARACTERISTICS

15AC CHARACTERISTICS (ANALOG)

16AC CHARACTERISTICS (DIGITAL)

17APPLICATION INFORMATION

18PACKAGE OUTLINE

19SOLDERING

19.1Introduction to soldering surface mount packages

19.2Reflow soldering

19.3Wave soldering

19.4Manual soldering

19.5Suitability of surface mount IC packages for wave and reflow soldering methods

20DEFINITIONS

21LIFE SUPPORT APPLICATIONS

1999 Oct 12

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

1 FEATURES

1.1General

∙2.7 to 3.6 V power supply

∙5 V tolerant TTL compatible inputs

∙Selectable control via L3 microcontroller interface or via static pin control

∙Multi-channel integrated digital filter plus non-inverting Digital-to-Analog Converter (DAC)

∙Supports sample frequencies between 5 and 100 kHz

∙Digital silence detection (output)

∙Slave mode only applications

∙No analog post filtering required for DAC

∙Easy application.

1.2Multiple format input interface

∙I2S-bus, MSB-justified and LSB-justified format compatible (in L3 mode)

∙I2S-bus and LSB-justified format compatible

∙1fs input format data rate.

1.3Multi-channel DAC

∙6-channel DAC with power on/off control

∙Digital logarithmic volume control via L3; volume can be set for each of the channels individually

∙Digital de-emphasis for 32, 44.1, 48 and 96 kHz fs via L3 and, for 32, 44.1 and 48 kHz in static mode

∙Soft or quick mute via L3

∙Output signal polarity control via L3 microcontroller interface.

1.4Advanced audio configuration

∙6-channel line output (under L3 volume control)

∙A stereo differential output (channel 1 and channel 2) for improved performance

∙High linearity, wide dynamic range, low distortion.

4 ORDERING INFORMATION

2 APPLICATIONS

This multi-channel DAC is eminently suitable for DVD like applications in which 5.1 channel encoded signals are used.

3 GENERAL DESCRIPTION

The UDA1328 is a single-chip 6-channel DAC employing bitstream conversion techniques, which can be used either in L3 microcontroller mode or in static pin mode.

The UDA1328 supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 and 24 bits.

All digital sound processing features can be controlled with the L3 interface e.g. volume control, selecting digital silence type, output polarity control and mute. Also system features such as power control, digital silence detection mode and output polarity control.

Under static pin control, via static pins, the system clock can be set to either 256fs or 384fs support, digital de-emphasis can be set, there is digital mute and the digital input formats can also be set.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
UDA1328T	SO32	plastic small outline package; 32 leads; body width 7.5 mm	SOT287-1

1999 Oct 12

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Philips Semiconductors					Preliminary specification
Multi-channel filter DAC						UDA1328T
5 QUICK REFERENCE DATA
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.		MAX.	UNIT
Supplies
VDDA	analog supply voltage		2.7	3.3		3.6	V
VDDD	digital supply voltage		2.7	3.3		3.6	V
IDDA	analog supply current	6 channels active	−	28		−	mA
IDDD	digital supply current		−	11		−	mA
Tamb	ambient temperature		−20	−		+85	°C
DAC: channels 1 and 2 differential
Vo(rms)	output voltage (RMS value)	notes 1 and 2	−	2		−	V
(THD + N)/S	total harmonic distortion plus	at 0 dB
	noise-to-signal ratio	fs = 48 kHz	−	−95		−88	dB
		fs = 96 kHz	−	−90		−	dB
		at −60 dB; A-weighted
		fs = 48 kHz	−	−46		−	dB
		fs = 96 kHz	−	−44		−	dB
S/N	signal-to-noise ratio	code = 0; A-weighted
		fs = 48 kHz	−	106		−	dB
		fs = 96 kHz	−	104		−	dB
DAC: channels 3 to 6 (channels 1 and 2 non-differential)
Vo(rms)	output voltage (RMS value)	note 1	−	1		−	V
(THD + N)/S	total harmonic distortion plus	at 0 dB
	noise-to-signal ratio	fs = 48 kHz	−	−90		−83	dB
		fs = 96 kHz	−	−85		−	dB
		at −60 dB; A-weighted
		fs = 48 kHz	−	−43		−	dB
		fs = 96 kHz	−	−41		−	dB
S/N	signal-to-noise ratio	code = 0; A-weighted
		fs = 48 kHz	−	103		−	dB
		fs = 96 kHz	−	101		−	dB
αcs	channel separation		−	100		−	dB

Notes

1.The output voltage scales proportionally with the power supply voltage.

2.In this case the two outputs per channel (for channels 1 and 2) are combined.

1999 Oct 12

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T
6 BLOCK DIAGRAM

VDDD			VSSD
	21		20
	UDA1328T				9
					STATIC
					23
10					MUTE
					24
BCK					DEEM1
11				CONTROL	25
WS				INTERFACE	DEEM0
12	DIGITAL				18
DATAI12	INTERFACE				L3CLOCK
13					19
DATAI34					L3DATA
14					17
DATAI56					L3MODE
	VOLUME/MUTE/DE-EMPHASIS				26
					DS
27	INTERPOLATION FILTER				8
TEST1					TEST3
16	6-CHANNEL NOISE SHAPER				22
SYSCLK					TEST2
DAC			DAC		32
28
VOUT1P					VOUT2P
29					31
VOUT1N					VOUT2N
	DAC		DAC
1					2
VOUT3					VOUT4
	DAC	DAC
4					5
VOUT5					VOUT6
6	7, 15		3	30
					MGR979
VDDA	n.c.		VSSA	Vref

Fig.1 Block diagram.

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

7 PINNING

SYMBOL	PIN	DESCRIPTION
VOUT3	1	channel 3 analog output
VOUT4	2	channel 4 analog output
VSSA	3	analog ground
VOUT5	4	channel 5 analog output
VOUT6	5	channel 6 analog output
VDDA	6	analog supply voltage
n.c.	7	not connected (reserved)
TEST3	8	test output 3
STATIC	9	static mode/L3 mode switch input
BCK	10	bit clock input
WS	11	word select input
DATAI12	12	data input channel 1 and 2
DATAI34	13	data input channel 3 and 4
DATAI56	14	data input channel 5 and 6
n.c.	15	not connected (reserved)
SYSCLK	16	system clock: 256fs, 384fs,
		512fs and 768fs
L3MODE	17	L3 mode selection input
L3CLOCK	18	L3 clock input
L3DATA	19	L3 data input
VSSD	20	digital ground
VDDD	21	digital supply voltage
TEST2	22	test output 2
MUTE	23	static mute control input
DEEM1	24	DEEM control 1 input
		(static mode)
DEEM0	25	L3 address select
		(L3 mode)/DEEM control 0 input
		(static mode)
DS	26	digital silence detect output
TEST1	27	test input 1
VOUT1P	28	channel 1 analog output P
VOUT1N	29	channel 1 analog output N
Vref	30	DAC reference voltage
VOUT2N	31	channel 2 analog output N
VOUT2P	32	channel 2 analog output P

handbook, halfpage
VOUT3	1			32	VOUT2P
VOUT4					VOUT2N
	2			31
VSSA					Vref
	3			30
VOUT5					VOUT1N
	4			29
VOUT6					VOUT1P
	5			28
VDDA					TEST1
	6			27
n.c.					DS
	7			26
TEST3					DEEM0
	8		UDA1328T	25
STATIC					DEEM1
	9			24
BCK	10			23	MUTE
WS					TEST2
	11			22
DATAI12					VDDD
	12			21
DATAI34					VSSD
	13			20
DATAI56					L3DATA
	14			19
n.c.					L3CLOCK
	15			18
SYSCLK	16			17	L3MODE
			MGR980

Fig.2 Pin configuration.

1999 Oct 12

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

8 FUNCTIONAL DESCRIPTION

8.1System clock

The UDA1328 operates in slave mode only, this means that in all applications the system must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs, 512fs and 768fs for the L3 mode and 256fs or 384fs for the static mode. The system clock must be frequency-locked to the digital interface signals.

It should be noted that the UDA1328 can operate from 5 to 100 kHz sampling frequency (fs). However in 768fs mode the sampling frequency must be limited to 55 kHz.

8.2Application modes

Operating mode can be set with the STATIC pin, either to L3 mode (STATIC = LOW) or to the static mode (STATIC = HIGH). See Table 1 for pin functions in the static mode.

Table 1 Mode selection in the static mode

PIN	L3 MODE	STATIC MODE
L3CLOCK	L3CLOCK	clock select
L3MODE	L3MODE	SF1(1)
L3DATA	L3DATA	SF0(1)
MUTE	X(2)	MUTE
DEEM1	X(2)	DEEM1
DEEM0	L3ADR	DEEM0

Notes

1.SF1 and SF0 are the Serial Format inputs (2-bit).

2.X means that the pin has no function in this mode and can best be connected to ground.

8.3Interpolation filter (DAC)

The digital filter interpolates from 1 to 128fs by cascading a half-band filter and a FIR filter, see Table 2. The overall filter characteristic of the digital filters is illustrated in Fig.3, and the pass-band ripple is illustrated in Fig.4. Both figures are with a 44.1 kHz sampling frequency.

Table 2 Interpolation filter characteristics

ITEM	CONDITION	VALUE (dB)
Pass-band ripple	0 to 0.45fs	±0.02
Stop band	>0.55fs	−55
Dynamic range	0 to 0.45fs	>114
DC gain	−	−3.5

8.4Digital silence detection

The UDA1328 can detect digital silence conditions in channels 1 to 6, and report this via the output pin DS. This function is implemented to allow for external manipulation of the audio signal in the absence of program material, such as muting or recorder control.

An active LOW output is produced at the DS pin if the channels selected via L3 or for all channels in static mode, carries all zeroes for at least 9600 consecutive audio samples (equals 200 ms for fs = 48 kHz). The DS pin is also active LOW when the output is digitally muted either via the L3 interface or via the STATIC pin.

In static mode all channels participate in the digital silence detection. In L3 mode control each channel can be set, either to participate in the digital silence detection or not.

8.5Noise shaper

The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).

8.6Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally with the power supply voltage.

8.7Static mode

The UDA1328 is set to static mode by setting the STATIC pin HIGH. The function of 6 pins of the device now get another function as can be seen in Table 1.

8.7.1SYSTEM CLOCK SETTING

In static mode pin 18 (L3CLOCK) is used to select the system clock setting. When pin 18 is LOW, the device is in 256fs mode, when pin 18 is HIGH the device is in 384fs mode.

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

8.7.2DE-EMPHASIS CONTROL

In static pin mode the pins DEEM0 and DEEM1 control the de-emphasis mode; see Table 3.

Table 3 De-emphasis control

DEEM MODE	DEEM1	DEEM0
No de-emphasis	0	0
32 kHz de-emphasis	0	1
44.1 kHz de-emphasis	1	0
48 kHz de-emphasis	1	1

8.7.3DIGITAL INTERFACE FORMATS

In static pin mode the digital audio interface formats can be selected via pin 17 (SF1) and 19 (SF0). The following interface formats can be selected (see also Table 4):

∙I2S-bus with data word length of up to 24 bits

∙LSB-justified format with data word length of 16, 20 or 24 bits.

Table 4 Input format selection in the static mode

INPUT FORMAT	SF1	SF0
I2S-bus	0	0
LSB-justified 16 bits	0	1
LSB-justified 20 bits	1	0
LSB-justified 24 bits	1	1

It should be noted that the digital audio interface holds that the BCK frequency can be 64 times the WS maximum frequency, or fBCK ≤ 64 × fWS

8.8L3 mode

The device is set to L3 mode by setting the STATIC pin to LOW. The device can then be controlled via the L3 microcontroller interface (see Chapter 9).

8.8.1DIGITAL INTERFACE FORMATS

The following interface formats can be selected in the L3 mode:

∙I2S-bus with data word length of up to 24 bits

∙MSB-justified with data word length of up to 24 bits

∙LSB-justified format with data word length of 16, 18, 20 or 24 bits.

8.8.2L3 ADDRESS

The UDA1328 can be addressed via the L3 microcontroller interface using one of two addresses. This is done in order to individually control the UDA1328 and other Philips DACs or CODECs via the same L3 bus.

The address can be selected using pin 25 (DEEM0) in L3 mode. When pin 25 is set LOW, the address is 000100. When pin 25 is set HIGH the address is 000101.

1999 Oct 12

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Philips Semiconductors	Preliminary specification
Multi-channel filter DAC	UDA1328T

MGR981

0

volume (dB)

−20

−40

−60

−80

−100

0	40	80	120	160	200
				f (kHz)

fs = 6.14400 MHz

Fig.3 Overall frequency characteristics.

MGR982

−3.45

Vo (dB)

−3.47

−3.49

−3.51

−3.53

0	10	20	f (kHz)	30

fs = 6.14400 MHz

Fig.4 Pass-band ripple of all filters.

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