Philips UDA1321 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

UDA1321

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

Preliminary speciﬁcation File under Integrated Circuits, IC01

1997 Jun 18

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

FEATURES General

• Complete stereo USB-DAC system with integrated filtering and line output drivers

• Supports USB-compliant audio multimedia devices over an industry standard USB-compatible 4-wire cable

• Supports 12 Mbits/s ‘full speed’ serial data transmission

• Fully automatic ‘Plug-and-Play’ operation

• Supports multiple audio data formats

• 3.3 V power supply

• Low power consumption

• Efficient power management mode

• On-chip master clock oscillator, only an external crystal

is required

• High linearity

• Wide dynamic range

• Superior signal-to-noise ratio

• Low total harmonic distortion

• Easy application and inexpensive to implement

• Partly programmable USB descriptors via EEROM

• 28 lead Small Outline package (SO28) or

32 Shrink Dual Inline package (SDIP32).

Sound processing

• Separate digital volume control for left and right channel

• Soft mute

• Digital bass and treble tone control

• External Digital Sound Processor (DSP) option possible

via standard I2S or Japanese digital I/O-format

• Selectable clipping prevention

• Selectable Dynamic Bass Boost (DBB)

• On-chip digital de-emphasis.

Document references

•

“USB Specification”

•

“USB Device Class Definition for Audio Devices”

release 0.9

•

“Device Class Definition for Human Interface Devices (HID)”

, release 1.0 draft 4

•

“USB HID Usage Table”,

, release 1.0

release 0.7f.

UDA1321

GENERAL DESCRIPTION

The UDA1321 is a stereo CMOS digital-to-analog bitstream converter designed for USB-compliant audio devices and multimedia audio applications. The UDA1321 is an adaptive asynchronous sink USB audio device with a continuous sampling frequency range from 5 to 55 kHz. It contains a USB-interface, an embedded micro controller and an Asynchronous Digital-to-Analog Converter (ADAC).

The USB-interface is the interface between the USB, the ADAC and the microcontroller. The USB-interface consists of an analog front-end and a USB-processor. The analog front-end transforms the differential USB-data to a digital data stream. The USB-processor buffers incoming and outgoing data from the analog front-end and handles all low level USB protocols. The USB-processor selects the relevant data from the bus, performs an extensive error detection and separates control information (in- and out-going) and audio information (in-going only). The control information is made accessible to the microcontroller. The audio information becomes available at the digital I/O-output or is fed directly to the ADAC.

The microcontroller handles the high level USB protocols, translates the incoming control requests and takes care of the user interface, through general purpose pins, and an

C port.

The ADAC enables the wide and continuous range of input sampling frequencies. By means of a Sample Frequency Generator (SFG), the ADAC is able to reconstruct the average sample frequency from the incoming audio samples. Furthermore the ADAC performs the sound processing. The ADAC consists of a FIFO, an unique audio feature processing DSP, the SFG, digital upsample filters, a variable hold register, a Noise Shaper (NS) and a Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The audio information is applied to the ADAC via the USB-processor or via the digital I/O-input.

Via the digital I/O-bus an external DSP can be used for adding extra sound processing features.

The UDA1321 supports the standard I2S-bus data input format and the LSB justified serial data input format with word lengths of 16, 18 and 20 bits.

1997 Jun 18 2

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB)

UDA1321

Digital-to-Analog Converter (DAC)

The wide dynamic range of the bitstream conversion technique used in the UDA1321 guarantees a high audio sound quality.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power supplies

DD(ps)

supply voltage note 1 3.0 3.3 3.6 V supply current − 50 mA supply current (power-saving mode) − 18 − mA

Dynamic performance DAC

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

S/N signal-to-noise ratio at bipolar zero A-weighted at

FS(o)(rms)

full-scale output voltage (RMS value) VDD= 3.3 V − 0.66 − V

General characteristics

i(sample)

amb

audio sample input frequency 5 − 55 kHz operating ambient temperature 0 25 70 °C

APPLICATIONS

• USB monitors

• USB speakers

• USB headsets

• USB telephone/answering machines

• USB links in consumer audio devices.

fs= 44.1 kHz; RL=5kΩ

at input signal of 1 kHz (0 dB)

at input signal of 1 kHz (−60 dB)

−−85 −80 dB

− 0.0056 0.01 %

−−30 −20 dB

− 3.2 10.0 %

90 95 − dBA

code 0000H

Note

1. All VDD and VSS pins must be connected to the same supply or ground respectively.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1321T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 UDA1321 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

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Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

BLOCK DIAGRAM

handbook, full pagewidth

RTCB

SHTCB

GP4/BCKO

GP3/WSO

GP2/DO

GP1/DI

GP0/BCKI

GP5/WSI

3 2

1 28

24 25

TCB

D+

D−

ANALOG FRONT END

USB-PROCESSOR

DIGITAL I/O

MICRO-

CONTROLLER

UDA1321

GP6/SCL

26 27

GP7/SDA

SSX XTAL1 XTAL2

DDX

VOUTL

FREQUENCY GENERATOR

11 12 13 14

SAMPLE

OSC

TIMING

FIFO

fs_in

AUDIO FEATURE

PROCESSING DSP

fs_in

UPSAMPLE FILTERS

64fs_in

VARIABLE HOLD REGISTER

128fs

3th ORDER

NOISE SHAPER

LEFT

DAC

REFERENCE

VOLTAGE

RIGHT

DAC

UDA1321T

20 19 17 16

9 8 7

DDE

SSE

SSI

DDI

DDO

SSO

DDA

SSA

VOUTR

15 V

Fig.1 Block diagram SO28 pinning.

1997 Jun 18 4

ref

MGG999

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB)

UDA1321

Digital-to-Analog Converter (DAC)

PINNING

SYMBOL

SDIP32

GP2/DO 1 1 I/O general purpose pin/data output pin for extra DSP chip (digital) GP3/WSO 2 2 I/O general purpose pin/master word select output pin for extra DSP chip (digital) GP4/BCKO 3 3 I/O general purpose pin/master bit clock output pin for extra DSP chip (digital) SHTCB 4 4 I shift clock TCB (active HIGH; digital)

5 − n.c.

D− 6 5 I/O negative data line of the differential data bus conforming to the USB-standard

D+ 7 6 I/O positive data line of the differential data bus conforming to the USB-standard

V V V V

DDI SSI SSE DDE

87−digital supply digital core 98−digital ground core

10 9 − digital ground I/O pads

11 10 − digital supply I/O pads

12 − n.c.

SSX

13 11 − crystal oscillator ground XTAL1 14 12 I crystal connection (analog) XTAL2 15 13 O crystal connection (analog) V

DDX

16 14 − supply crystal oscillator

17 − n.c. V V V

ref SSA DDA

18 15 I V

19 16 − analog ground

20 17 − analog supply VOUTR 21 18 O voltage output pin right channel (analog) V V

SSO DDO

22 19 − opamp ground

23 20 − opamp supply VOUTL 24 21 O voltage output pin left channel (analog) TC 25 22 I test control pin (active HIGH; analog) RTCB 26 23 I asynchronous reset TCB (active HIGH; digital) GP0/BCKI 27 24 I/O general purpose pin (digital)

28 − n.c. GP5/WSI 29 25 I/O general purpose pin (digital) GP6/SCL 30 26 I/O general purpose pin/clock line I GP7/SDA 31 27 I/O general purpose pin/data line I GP1/DI 32 28 I/O general purpose pin/data input pin from extra DSP chip (digital)

SO28

I/O DESCRIPTION

(analog)

output pin (analog)

ref

C-bus (digital)

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Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

handbook, halfpage

GP2/DO

GP3/WSO

GP4/BCKO

SHTCB

D− D+

DDI

SSI

SSE

DDE

SSX

XTAL1 XTAL2

DDX

1 2 3 4 5 6 7

UDA1321T

9 10 11 12 13

MGG998

28 27 26 25 24 23 22 21 20 19 18 17 16 1514

GP1/DI GP7/SDA GP6/SCL GP5/WSI GP0/BCKI RTCB TC VOUTL V

DDO

SSO

VOUTR V

DDA

SSA

ref

handbook, halfpage

GP3/WSO GP7/SDA

GP4/BCKO GP6/SCL

UDA1321

GP2/DO GP1/DI

SHTCB GP5/WSI

1 2 3 4

n.c.

D− GP0/BCKI

D+ RTCB

DDI

SSI

SSE

DDE

n.c.

SSX XTAL1 XTAL2

DDX

9 10 11 12 13 14 15 16

UDA1321

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

MBK135

n.c.

TC VOUTL V

DDO

SSO VOUTR V

DDA V

SSA V

ref n.c.

Fig.2 Pin configuration SO28.

1997 Jun 18 6

Fig.3 Pin configuration SDIP32.

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB)

Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 Ω intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection.

The analog front-end

The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s).

The analog front-end can be switched in power saving mode.

The USB-processor

The USB-processor forms the interface between the analog front-end, the ADAC and the microcontroller. The USB-processor consists of:

• The Philips Serial Interface Engine (PSIE)

• The Memory Management Unit (MMU)

• The Audio Sample Redistribution (ASR) module.

The Philips Serial Interface Engine and Memory Management Unit (PSIE_MMU)

The PSIE_MMU translates the electrical USB signals into bytes and signals. Depending upon the device USB address and the USB endpoint address, the USB data is directed to the correct endpoint buffer on the PSIE_MMU interface. The data transfer could be of bulk, isochronous, control or interrupt type. The device USB address is conﬁgured during the enumeration process. The UDA1321 has three endpoints. These are:

• Control Endpoint 0

• Status Interrupt Endpoint

• Isochronous Data Sink Endpoint

UDA1321

USB sync-word and handles all low-level USB protocols and error checking.

The MMU is the digital back-end of the USB-processor. It handles the temporary data storage of all USB packets that are received or sent over the bus. On the USB, three types of packets are defined. These are:

• Token packets

• Data packets

• Handshake packets.

The token packet contains information about the destination of the data packet. The audio data is transferred via an isochronous data sink endpoint and as a consequence no handshaking mechanism is used. The MMU also generates a 1 kHz clock that is locked to the USB Start-Of-Frame (SOF) token.

The Audio Sample Redistributor (ASR)

The ASR reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to I The ASR generates the bit clock and the word select signal of the digital I/O. The digital I/O-formats the received audio samples to one of the four speciﬁed serial digital audio formats (I2S, 16, 18 or 20 bits LSB-justiﬁed).

The microcontroller

The microcontroller receives the control information selected from the USB by the USB-processor. It handles the high level USB protocols and the user interfaces.

The major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1321 in such a way that it behaves as a USB device.

Therefore the microcontroller:

• interprets the USB requests and maps them upon the UDA1321 application

• controls the internal operation of the UDA1321, the digital I/O-pins and the GP I/O-pins

• communicates with the external world (EEROM) using

C-bus facility and the GP I/O-pins.

S or Japanese digital I/O-format.

The amount of bytes/packet on the control endpoint is limited by the PSIE_MMU hardware to 8 bytes/packet.

The PSIE is the digital front-end of the USB-processor. This module recovers the 12 MHz USB-clock, detects the

1997 Jun 18 7

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

The Asynchronous Digital-to-Analog Converter (ADAC)

The ADAC receives USB audio information from the USB-processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and takes care of the audio sound processing. After the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of:

• A Sample Frequency Generator (SFG)

• FIFO registers

• An audio feature processing DSP

• Two digital upsample filters and a variable hold register

• A digital Noise Shaper (NS)

• A Filter Stream DAC (FSDAC) with integrated filter and

line output drivers.

UDA1321

Table 1 Frequency domains for audio processing

DOMAIN SAMPLE FREQUENCY

1 5..12 kHz 2 12..25 kHz 3 25..40 kHz 4 40.. 55 kHz

The upsample ﬁlters and variable hold function

After the audio feature processing DSP two upsample filters and a variable hold function increase the oversampling rate to 128f

The noise shaper

A third order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band.

The Sample Frequency Generator (SFG)

The SFG controls the timing signals for the asynchronous D/A conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the upsample ﬁlters.

First In First Out (FIFO) registers

The FIFO registers are used to store the audio samples temporarily coming from the USB-processor or from the digital I/O-input. The use of a FIFO (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal.

The audio feature processing DSP

A DSP processes the sound features. The control and mapping of the sound features is explained in Section “Controlling the USB-DAC”. Depending on the sampling rate f frequency domains in which the treble and bass are regulated. The domain is chosen automatically.

the DSP knows four

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A postfilter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

USB-DAC descriptors

In a typical USB environment the PC has to know which kind of devices are connected to its USB-bus. For this purpose each device contains a number of USB descriptors. These descriptors describe, from different points of view (USB-configuration, USB-interface and USB-endpoint), the capabilities of a device. Each of them can be requested by the host. The collection of descriptors is denoted as a descriptor map. This descriptor map will be reported to the USB host during enumeration.

The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1321 are shortly explained below.

1997 Jun 18 8

Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

GENERAL DESCRIPTORS The UDA1321 supports one configuration containing a

control interface, an audio interface and a HID interface. The descriptor map that describes this configuration is partly fixed and partly programmable.

The programmable part can be retrieved from one out of four internal configuration maps or from an I2C EEROM. At start-up time one out of four internal configuration maps can be selected depending on the logical combination of GP3 and GP0. It is possible to overwrite this configuration map with a configuration map loaded from an I2C EEROM.

The descriptors of the descriptor map as mentioned above are described in Tables 2 and 3. The programmable descriptors are marked with a star. The given values are examples used in Philips applications.

Table 2 Standard Device Descriptor and Conﬁgurations.

DEVICE

DESCRIPTOR

bLength 12 bDescriptorType 01 bcdUSB 0001 cDeviceClass 00 cDeviceSubClass 00 cDeviceProtocol 00 bMaxPacketSize0 08 idVendor 7104* idProduct 0101* bcdDevice 0001 iManufactor 01 iProduct 02 iSerialNumber 03 bNumConﬁgurations 01

V ALUE

HEX

UDA1321

Table 3 Conﬁguration Descriptor and Interfaces.

CONFIGURATION

DESCRIPTOR

bLength 09 bDescriptortype 02 wTotalLength tbf bNumInterfaces 03 bConﬁgurationValue 01 iConﬁguration 00 bmAttributes 40* MaxPower 0*

UDIO DEVICE CLASS SPECIFIC DESCRIPTORS

A The Audio Device Class is partly specified with Standard

Descriptors and partly with Specific Audio Device Class Descriptors. The Standard Descriptors specify the number and the type of the interface or endpoint. The UDA1321 supports 7 different audio modes:

• 8-bit PCM mono or stereo audio data

• 16-bit PCM mono or stereo audio data

• 24-bit PCM mono or stereo audio data.

• Zero bandwidth mode.

Each mode is defined as an alternate setting of the audio interface, selectable with the standard audio streaming interface descriptor bAlternateSetting field; see Table 4.

Within the audio interface, an isochronous sink endpoint is defined.

Table 4 Standard Audio Control Interface Descriptor.

DESCRIPTOR

bLength 0B bDescriptortype 04 bInterfaceNumber 00 bAlternateSetting 00 bNumEndpoints 00 bInterfaceClass 01 bInterfaceSubClass 01 bInterfaceProtocol 00 iInterface 00 wNumClasses 0100

VALUE

HEX

VALUE

HEX

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Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

The seven alternate settings are described in more detail by the Specific Audio Device Class Descriptors. For example, support of different sound features, such as Volume, Treble, Bass, Mute etc.

Table 5 Class Speciﬁc Audio Control Interface

Descriptor Header.

DESCRIPTOR

bLength 09 bDescriptortype 24 bDescriptorSubtype 01 bcdADC 0900 wTotalLength 2B00 bInCollection 01 baInterfaceNr(1) 01

The UDA1321 supports the Input Terminal, Output Terminal and the Feature Unit Descriptors.

The Input and Output Terminals are not controllable via USB. The Feature Unit provides the basic manipulation of the incoming logical channels. The supported sound features are: Volume control, Mute control, Treble control Bass control and Bass Boost control.

Table 6 Class Speciﬁc Input Terminal Descriptor.

DESCRIPTOR

bLength 0C bDescriptortype 24 bDescriptorSubtype 02 bTerminalID 01 wTerminalType 0101 bAssocTerminal 00 bNrChannels 02 wChannelConﬁg 0300 iChannelNames 00 iTerminal 00

VALUE

HEX

VALUE

HEX

UDA1321

Table 7 Class Speciﬁc Feature Unit Descriptor.

DESCRIPTOR

bLength 0D bDescriptortype 24 bDescriptorSubtype 06 bUnitID 02 bSourceID 01 bControlSize 02 bmaControls(0) 1501* bmaControls(1) 0200 bmaControls(2) 0200 iFeature 00

Table 8 Class Speciﬁc Output Terminal Descriptor.

DESCRIPTOR

bLength 09 bDescriptortype 24 bDescriptorSubtype 03 bTerminalID 03 wTerminalType 0103* bAssocTerminal 00 bSourceID 02 iTerminal 00

The maximum number of audio data samples within an USB packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint. The maximum buffer capacity is 336 bytes/ms.

For each alternate setting with audio, a maximum bandwidth is claimed as indicated in the Standard Isochronous Audio Data Endpoint Descriptor wMaxPacketSize field. To allow a small overshoot in the number of audio samples per packet, the top sample frequency of 55 kHz is taken in the calculation of the bandwidth for each alternate setting. For each alternate setting, with its own Isochronous Audio Data Endpoint Descriptor, wMaxPacketSize field is then defined as described in Table 9.

VALUE

HEX

VALUE

HEX

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Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

Table 9 Audio bandwidth at each audio mode.

AUDIO MODE wMaxPacketSize

8-bit PCM, mono 56 ( 8-bit PCM, stereo 112 ( 16-bit PCM, mono 112 ( 16-bit PCM, stereo 224 ( 24-bit PCM, mono 168 ( 24-bit PCM, stereo 336 (

The Standard Audio Streaming Interface Descriptor and the Standard Isochronous Audio Data Endpoint Descriptor are given below.

Table 10 Standard Audio Streaming Interface Descriptor

ﬁelds for alternate setting 0.

DESCRIPTOR

bLength 0B bDescriptortype 04 bInterfaceNumber 01 bAlternateSetting 00 bNumEndpoints 00 bInterfaceClass 01 bInterfaceSubClass 02 bInterfaceProtocol 00 iInterface 00 wNumClasses 0100

Table 11 Standard Audio Streaming Interface Descriptor

ﬁelds for alternate setting 1 to 6.

DESCRIPTOR

bLength 0B bDescriptortype 04 bInterfaceNumber 01 bAlternateSetting 01, 02, 03, 04, 05, 06 bNumEndpoints 01 bInterfaceClass 01 bInterfaceSubClass 02 bInterfaceProtocol 00 iInterface 00 wNumClasses 0100

⁄8× 1 × 56)

⁄8× 2 × 56)

⁄8× 1 × 56)

⁄8× 2 × 56)

⁄8× 1 × 56)

⁄8× 2 × 56)

VALUE

HEX

VALUE

HEX

UDA1321

Table 12 Class Speciﬁc Audio Streaming Interface

General Descriptor for alternate setting 1 to 6.

DESCRIPTOR

bLength 07 bDescriptortype 24 bDescriptorSubtype 01 bTerminalLink 01 bDelay 00 wFormatTag 0100

Although in this specific UDA1321 application no endpoint control properties can be used upon the isochronous adaptive sink endpoint, the descriptors are still necessary to inform the host about the definition of this endpoint: isochronous, adaptive, sink, continuous sampling frequency (at input side of this endpoint) with lower bound of 5 kHz and upper bound of 55 kHz. These characteristics are defined in Table 13.

Table 13 Class Speciﬁc Audio Streaming Interface

Format Type I Descriptor Continuous Sampling Frequency for alternate setting 1 to 6.

DESCRIPTOR

bLength 0E bDescriptortype 24 bDescriptorSubtype 02 bFormatType 01 bNrChannels depends on audio mode bSubframeSize depends on audio mode bBitResolution depends on audio mode bSamFreqType 00 tLowerSamFreq 7E 13 00 tUpperSamFreq E2 D6 00

Notice the tLowerSamFreq and tUpperSamFreq fields are defined in little Endian order (LSB first). The Audio Class Specific Descriptors can be requested with the ‘Get Descriptor: Configuration request’, which returns all the descriptors, except the Device Descriptor.

VALUE

HEX

VALUE

HEX

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Philips Semiconductors Preliminary speciﬁcation

Universal Serial Bus (USB) Digital-to-Analog Converter (DAC)

Table 14 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 8 bit-PCM mono.

DESCRIPTOR

bNrChannels 01 bSubframeSize 01 bBitResolution 08

Table 15 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 8 bit-PCM stereo.

DESCRIPTOR

bNrChannels 02 bSubframeSize 01 bBitResolution 08

Table 16 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 16 bit-PCM mono.

DESCRIPTOR

bNrChannels 01 bSubframeSize 02 bBitResolution 10

Table 17 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 16 bit-PCM stereo.

DESCRIPTOR

bNrChannels 02 bSubframeSize 02 bBitResolution 10

VALUE

HEX

VALUE

HEX

VALUE

HEX

VALUE

HEX

UDA1321

Table 19 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 24 bit-PCM stereo.

DESCRIPTOR

bNrChannels 02 bSubframeSize 03 bBitResolution 14

Table 20 Standard Isochronous Audio Data Endpoint

Descriptor included for alternate setting 1 to 6.

DESCRIPTOR

bLength 09 bDescriptortype 05 bEndpointAddress 04 bmAttributes 09 wMaxPacketSize depends on audio mode;

see Table 9 bInterval 01 bRefresh 00 bSynchAddress 00

Table 21 Class Speciﬁc Isochronous Audio Data

Endpoint Descriptor included for alternate setting 1 to 6.

DESCRIPTOR

bLength 07 bDescriptortype 25 bDescriptorSubtype 01 bmAttributes 00 bLockDelayUnits 02 bLockDelay 0002

VALUE

HEX

VALUE

HEX

VALUE

HEX

Table 18 bNrChannels, bSubframeSize and

bBitResolution Descriptor ﬁelds for audio

mode 24 bit-PCM mono.

DESCRIPTOR

bNrChannels 01 bSubframeSize 03 bBitResolution 14

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VALUE

HEX

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