Philips UDA1320ATS-N2 Datasheet
DATA SH EET
Preliminary specification
Supersedes data of 1999 Oct 11
File under Integrated Circuits, IC01
2000 Jan 10
INTEGRATED CIRCUITS
UDA1320ATS
Low-cost stereo filter DAC
2000 Jan 10 2
Philips Semiconductors Preliminary specification
Low-cost stereo filter DAC UDA1320ATS
CONTENTS
1 FEATURES
1.1 General
1.2 Multiple format input interface
1.3 DAC digital sound processing
1.4 Advanced audio configuration
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
8.1 System clock
8.2 Application modes
8.3 Multiple format input interface
8.4 Static pin mode
8.5 Pin compatibility
8.6 Interpolation filter (DAC)
8.7 Noise shaper
8.8 Filter-Stream DAC
9 L3 INTERFACE DESCRIPTION
9.1 The L3 interface
9.2 Data transfer mode
9.3 Programming the features
10 LIMITING VALUES
11 HANDLING
12 QUALITY SPECIFICATION
13 THERMAL CHARACTERISTICS
14 DC CHARACTERISTICS
15 AC CHARACTERISTICS
15.1 Analog
15.2 Digital
16 APPLICATION INFORMATION
17 PACKAGE OUTLINE
18 SOLDERING
18.1 Introduction
18.2 Reflow soldering
18.3 Wave soldering
18.4 Repairing soldered joints
19 DEFINITIONS
20 LIFE SUPPORT APPLICATIONS
2000 Jan 10 3
Philips Semiconductors Preliminary specification
Low-cost stereo filter DAC UDA1320ATS
1 FEATURES
1.1 General
• Low power consumption.
• 2.7 to 3.6 V power supply.
• Selectable controlvia L3 microcontroller interface or via
static pin control.
• 256, 384 and 512fs system clock (f
sys
), selectable via
the L3 interface or 256 and 384fs clock mode via static
pin control
• supports sampling frequencies from 16kHz to 48kHz.
• Integrated digital filter plus non inverting DAC
Digital-to-Analog Converter (DAC).
• Easyapplication and no analog postfilteringrequiredfor
DAC.
• Slave mode only applications.
• Small package size (SSOP16).
1.2 Multiple format input interface
• I2S-bus, MSB-justified and LSB-justified 16,18 and 20
bits format compatible (in L3-mode).
• I2S-bus and LSB-justified 16,18 and 20 bits format
compatible in static mode.
• 1fs input format data rate.
1.3 DAC digital sound processing
• Digital logarithmic volume control via L3.
• Digital de-emphasis for 32, 44.1 and 48 kHz fs via
L3 or 44.1 kHz fs via static pin control.
• Soft mute via static pin control or via L3 interface.
1.4 Advanced audio configuration
• Stereo line output (under L3 volume control)
• High linearity, wide dynamic range, low distortion.
2 APPLICATIONS
• Portable digital audio equipment, see Fig.8.
• Set-top boxes
3 GENERAL DESCRIPTION
TheUDA1320ATS/N2 is asingle-chip non inverting stereo
DAC employing bitstreamconversion techniques. The low
power consumption and low voltage requirements make
the device eminently suitable for use in digital audio
equipment which incorporates playback functions.
The UDA1320ATS/N2 supports the I2S-bus data format
with word lengths of up to 20 bits, the MSB-justified data
format with word lengths of up to 20 bits and the
LSB-justified serial data format with word lengths of 16,
18 and 20 bits.
The UDA1320ATS/N2 can be used in two modes, either
L3-mode or static pin mode.
In the L3-mode, all digital soundprocessing features must
becontrolled via the L3 interface, includingtheselectionof
the system clock setting.
In the two static-modes, the UDA1320ATS/N2 can be
operated in the 256fs and 384fs system clock mode. The
mute,de-emphasisfor 44.1 kHz and 4 digital inputformats
(I2S and 16, 18, 20 bits LSB formats) can be selected via
static pins. The L3 interface cannot be used in this
application mode, also, volume control is not available in
this mode.
4 ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
UDA1320ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1
2000 Jan 10 4
Philips Semiconductors Preliminary specification
Low-cost stereo filter DAC UDA1320ATS
5 QUICK REFERENCE DATA
Notes
1. the output voltage has been changed with respect to the UDA1320TZ/N1.
2. the output voltage scales linearly with the power supply voltage.
6 BLOCK DIAGRAM
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DDA
analog supply voltage 2.7 3.3 3.6 V
V
DDD
digital supply voltage 2.7 3.3 3.6 V
I
DDA
DAC supply current − 6.5 − mA
I
DDD
digital supply current − 3.0 − mA
T
amb
ambient temperature −40 − +85
°
C
DAC
V
o(rms)
output voltage (RMS value) note 1, 2 − 1.0 − V
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
at 0 dB −−90 −85 dB
at −60 dB; A-weighted −−38 −35 dB
S/N signal-to-noise ratio code = 0; A-weighted − 100 95 dB
α
cs
channel separation − 100 − dB
T
amb
ambient temperature −40 − +85
°
C
Fig.1 Block diagram.
handbook, full pagewidth
MGM816
DAC
UDA1320A
NOISE SHAPER
INTERPOLATION FILTER
VOLUME/MUTE/DE-EMPHASIS
CONTROL
INTERFACE
14
15
DAC
6
DIGITAL INTERFACE
8
16
9
10
3
2
1
4
5
11
7
13 12
V
O(R)
BCK
V
SSA
WS
V
O(L)
DATAI
V
DDA
V
DDD
V
REF(DAC)
V
SSD
APPL0
SYSCLK
APPL1
APPSEL
APPL2
APPL3
2000 Jan 10 5
Philips Semiconductors Preliminary specification
Low-cost stereo filter DAC UDA1320ATS
7 PINNING 8 FUNCTIONAL DESCRIPTION
8.1 System clock
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
The options are 256fs, 384fs and 512fs for the L3 mode
and 256fsplus 384fsfor the static mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
8.2 Application modes
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = V
SSD
) or to either of
two static modes (APPSEL = 0.5V
DDD
or
APPSEL = V
DDD
). See Table 1 for APPL0 to APPL3 pin
functions (active = HIGH).
Table 1 Selection modes via APPSEL (note 1)
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
In L3 mode pin APPL0 must be set to LOW.
SYMBOL PIN
DESCRIPTION
BCK 1 bit clock
WS 2 word select
DATAI 3 data input
V
DDD
4 digital power supply
V
SSD
5 digital ground
SYSCLK 6 system clock: 256f
s
, 384fs, 512f
s
APPSEL 7 application mode select
APPL3 8 application pin 3
APPL2 9 application pin 2
APPL1 10 application pin 1
APPL0 11 application pin 0
V
REF(DAC)
12 DAC reference voltage
V
DDA
13 analog supply voltage
V
O(L)
14 left output voltage
V
SSA
15 analog ground
V
O(R)
16 right output voltage
Fig.2 Pin configuration.
handbook, halfpage
UDA1320A
MGM817
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
O(R)
BCK
V
SSA
WS
V
O(L)
DATAI
V
DDA
V
DDD
V
REF(DAC)
V
SSD
APPL0SYSCLK
APPL1APPSEL
APPL2APPL3
PIN
APPSEL
V
SSD
0.5V
DDD
(384fs)
V
DDD
(256fs)
APPL0 TEST MUTE MUTE
APPL1 L3CLOCK DEEM DEEM
APPL2 L3MODE SF0 SF0
APPL3 L3DATA SF1 SF1
2000 Jan 10 6
Philips Semiconductors Preliminary specification
Low-cost stereo filter DAC UDA1320ATS
8.3 Multiple format input interface
L3 mode:
• I2S-bus with data word length of up to 20 bits
• MSB-justified format with data word length up to 20 bits
• LSB-justified format with data word length of 16,
18 or 20 bits.
8.4 Static pin mode
The UDA1320ATS/N2 supports the following data input
name formats in the static pin mode (via SF0 and SF1):
• I2S bus with data word length of up to 20 bits
• LSB-justified format with data word length of 16,
18 or 20 bits.
See Table 2, for the static pin codes of the 4 formats,
selectable via SF0 and SF1.
The UDA1320ATS/N2 also accepts double speed data for
double speed data monitoring purposes.
Table 2 Input format selection using SF0 and SF1
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed. The WS signal
must have 50% duty-factor for all LSB-justified modes.
For BCK and WS holds that the BCK frequency must be
equal or smaller then 64 times WS, or f
BCK
=< 64*fWS in
both L3 and static mode.
8.5 Pin compatibility
InL3 interface mode theUDA1320ATS/N2canbe used on
boards that are designed for the UDA1322. The software
for UDA1322 can be used for the UDA1320ATS/N2 to
control de-emphasis, volume control and mute and also
the status settings like system clock setting andinput data
format.
IMPORTANT: UDA1320ATS/N2 differs from the
UDA1320TZ/N1 with respect to:
• in the static mode 384fs is supported instead of 512fs.
• the output voltage of the DAC. In the UDA1320TZ/N1
this is 800mVrmsat 3.0V, now it is 1Vrms at3.3V power
supply
8.6 Interpolation filter (DAC)
The digital filter interpolates from 1 to 128fs by cascading
a recursive filter and a FIR filter, see Table 3.
Table 3 Interpolation filter characteristics
8.7 Noise shaper
The 3rd-order noise shaper operates at 128f
s
. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter-Stream DAC (FSDAC).
8.8 Filter-Stream DAC
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to be
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter isnot needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales linearly with the
power supply voltage.
FORMAT SF0 SF1
I
2
S00
LSB-justified 16 bits 0 1
LSB-justified 18 bits 1 0
LSB-justified 20 bits 1 1
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f
s
±0.1
Stop band >0.55f
s
−50
Dynamic range 0 to 0.45f
s
108
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