Philips UDA1309H-N1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

UDA1309H

Low-power stereo bitstream

ADC/DAC

Product specification

1998 Jan 06

Supersedes data of 1996 Jul 18

File under Integrated Circuits, IC01

Philips Semiconductors	Product specification
Low-power stereo bitstream ADC/DAC	UDA1309H

FEATURES

∙Low power

∙Integrated high-pass filter to cancel DC offset (ADC)

∙Analog loop-through function

∙Multiple digital input/output formats possible

∙256fs system clock frequency

∙Several power-down modes

∙Digital de-emphasis (DAC)

∙Overload detector to enable automatic recording level adjustment (ADC)

∙High dynamic range

∙DAC requires only one capacitor for post-filtering

∙Small 44-pin quad flat pack with 0.8 mm pitch

∙256fs system clock frequency in Analog-to-Digital (AD) and Digital-to-Analog (DA) mode

∙Choice of three system clock frequencies (192fs, 256fs or 384fs) in DA mode.

ORDERING INFORMATION

APPLICATION

∙ Portable digital audio equipment.

GENERAL DESCRIPTION

The UDA1309H is a single chip stereo analog-to-digital and digital-to-analog converter employing bitstream conversion techniques. The device is eminently suitable for use in low-power portable digital audio equipment which incorporates recording and playback functions.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
UDA1309H	QFP44	plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm	SOT307-2

1998 Jan 06

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Philips Semiconductors	Product specification
Low-power stereo bitstream ADC/DAC	UDA1309H

QUICK REFERENCE DATA

VDDD = VDDA = VDDO = VDDD(F) = 5 V; VSSD = VSSA = VSSO = VSSD(F) = 0 V; Tamb = 25 °C; full scale sine wave input; mode 1; fi = 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless

otherwise specified.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VDDA(AD)	ADC analog supply voltage (pin 8)		4.5	5.0	5.5	V
VDDA(DA)	DAC analog supply voltage (pin 25)		4.5	5.0	5.5	V
VDDO	operational amplifiers supply voltage		4.5	5.0	5.5	V
	(pin 19)
VDDD	ADC and DAC digital supply voltage		4.5	5.0	5.5	V
	(pin 28)
VDDD(F)	digital filters supply voltage (pin 34)		4.5	5.0	5.5	V
IDDA(AD)	ADC analog supply current (pin 8)		−	9	13.5	mA
IDDA(DA)	DAC analog supply current (pin 25)		−	4.5	6.8	mA
IDDO	operational amplifiers supply current		−	14	21	mA
	(pin 19)
IDDD	ADC and DAC digital supply current		−	0.2	0.5	mA
	(pin 28)
IDDD(F)	digital filters supply current (pin 34)		−	24	36	mA
Tamb	operating ambient temperature		−20	−	+75	°C
Analog-to-digital converter
VI(rms)	input voltage (RMS value)	note 1	0.9	1.0	1.1	V
(THD + N)/S	total harmonic distortion plus	at 0 dB	−	−85	tbf	dB
	noise-to-signal ratio
		at −60 dB; A-weighted	−	−35	−30	dB
S/N	idle channel signal-to-noise ratio	VI = 0 V; A-weighted	tbf	95	−	dB
αcs	channel separation		−	90	−	dB
Digital-to-analog converter
VO(rms)	output voltage (RMS value)	note 2	0.9	1.0	1.1	V
(THD + N)/S	total harmonic distortion plus	at 0 dB	−	−90	−82	dB
	noise-to-signal ratio
		at −60 dB; A-weighted	−	−38	−34	dB
		at −60 dB; A-weighted; note 3	−	−44	−	dB
S/N	idle channel signal-to-noise ratio	code 0000H; A-weighted	−	104	−	dB
αcs	channel separation		90	100	−	dB

Notes

1.VI for full scale digital output is a function of VDDA(AD) [1.0 V (RMS) at VDDA(AD) = 5.0 V is equivalent to −1.0 dB in the digital domain].

2.At full scale digital input; no de-emphasis; VO(rms) is a function of VDDA(DA).

3.18-bit input data.

1998 Jan 06

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06 Jan1998

analog input

pagewidthook,full

VIL

47 μF

VDDA(AD)

4.7 kΩ

VDDA(DA)

analog output

330 pF

CLKEDGE

VSSD(F)

V

SSA(DA)

0.22 μF

VOL

DADEM

TEST0

MODE2

4.7 kΩ

TEST1

MODE1

VDDD(F)

VDDO

1 nF

SYSCLK

MODE0

VSSO

0.22 μF

Vref(pos)

Vref

BAIL

BAOL

Vref(neg)

DACL

VOL

10

13

12

11

9

40

38

37

44

43

42

3

30

34

33

25

26

19

20

22

21

1.6 kΩ

VSSA(AD) 7

VDDA(AD) 8

ADC

MODE SELECT

DAC

Iref 17

CURRENT

IDAC

47

REFERENCE

DIGITAL

DIGITAL

DIGITAL

DIGITAL

Vm

18

DAref

FILTER

INTERFACE

INTERFACE

FILTER

kΩ

0.22

4

μF

ADC

DAC

Vm

UDA1309H

1.6 kΩ

16

14

15

5

4

2

1

41

6

36

32

31

35

29

39

28

27

23

24

ADref

BAIR

BAOR

VSS(I/O)

VDDD

VSSD

DACR

VOR

0.22 μF

ADENB

DAPON

1 nF

4.7 kΩ

ADWS

DASDA

330 pF

ADBCK

DABCK

4.7 kΩ

OVLOAD

ADSDA

DAWS

analog output

ADPON ANLPTR

VOR

MBH527

47 μF

analog input VIR

Supply decoupling on pins 19, 25, 28 and 34; 0.22 μF (ceramic), 47 μF (electrolytic).

Capacitance at pin 11 should be close to pins 11 and 9.

Fig.1 Block diagram.

DIAGRAM BLOCK

10

μF

ADC/DAC bitstream stereo power-Low

UDA1309H

Semiconductors Philips

specification Product

Philips Semiconductors					Product specification
	Low-power stereo bitstream ADC/DAC				UDA1309H
PINNING
	SYMBOL		PIN	DESCRIPTION
	ADBCK		1	ADC input bit clock; 32fs or 64fs
	ADWS		2	ADC word select input at fs
	MODE0		3	ADC/DAC mode select input
	ADENB		4	ADC serial data enable input (active HIGH)
			5	ADC output overload flag (active LOW)
	OVLOAD
	ADPON		6	ADC power-on-mode input (active HIGH)
	VSSA(AD)		7	ADC analog ground supply voltage
	VDDA(AD)		8	ADC analog supply voltage
	Vref(neg)		9	ADC negative reference voltage input (ground)
	Vref		10	ADC decoupling capacitor
	Vref(pos)		11	ADC positive reference voltage decoupling capacitor
	BAOL		12	ADC input amplifier output left
	BAIL		13	ADC input amplifier virtual ground left
	BAIR		14	ADC input amplifier virtual ground right
	BAOR		15	ADC input amplifier output right
	ADref		16	ADC decoupling capacitor
	Iref		17	ADC/DAC reference current resistor input
	DAref		18	DAC decoupling capacitor
	VDDO		19	ADC/DAC operational amplifier supply voltage
	VSSO		20	ADC/DAC operational amplifier ground supply voltage
	VOL		21	DAC output voltage left
	DACL		22	DAC output current left
	DACR		23	DAC output current right
	VOR		24	DAC output voltage right
	VDDA(DA)		25	DAC analog supply voltage
	VSSA(DA)		26	DAC analog ground supply voltage
	VSSD		27	ADC/DAC digital ground supply voltage
	VDDD		28	ADC/DAC digital supply voltage
	DAPON		29	DAC power-on-mode input (active HIGH)
	DADEM		30	DAC digital de-emphasis input (active HIGH)
	DABCK		31	DAC input bit clock; 32fs, 48fs or 64fs
	DAWS		32	DAC word select input at fs
	VSSD(F)		33	ADC/DAC digital filters ground supply voltage
	VDDD(F)		34	ADC/DAC digital filters supply voltage
	DASDA		35	DAC serial data input
	ANLPTR		36	ADC/DAC analog loop-through input (active HIGH)
	TEST0		37	ADC/DAC enable test mode 0 input (LOW is normal mode)
	TEST1		38	ADC/DAC enable test mode 1 input (LOW is normal mode)
	VSS(I/O)		39	ADC/DAC digital input/output ground supply voltage
	SYSCLK		40	ADC/DAC system clock input (fsys = 256fs; DAC also 192fs and 384fs)

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Philips Semiconductors			Product specification
Low-power stereo bitstream ADC/DAC			UDA1309H
SYMBOL	PIN	DESCRIPTION
ADSDA	41	ADC serial data output
MODE1	42	ADC/DAC mode 1 select input
MODE2	43	ADC/DAC mode 2 select input
CLKEDGE	44	ADC/DAC input bit clock rising/falling edge

handbook, full pagewidth

		CLKEDGE	MODE2	MODE1	ADSDA	SYSCLK	V	TEST1	TEST0	ANLPTR	DASDA	V
							SS(I/O)					DDD(F)
		44	43	42	41	40	39	38	37	36	35	34
	ADBCK	1
	ADWS	2
	MODE0	3
	ADENB	4
		5
OVLOAD
	ADPON	6				UDA1309H
VSSA(AD)		7
VDDA(AD)		8
Vref(neg)		9
	Vref	10
Vref(pos)		11
		12	13	14	15	16	17	18	19	20	21	22
		BAOL	BAIL	BAIR	BAOR	AD	I	DA	V	V	V	DACL
						ref	ref	ref	DDO	SSO	OL

33	VSSD(F)
32	DAWS
31	DABCK
30	DADEM
29	DAPON
28	VDDD
27	VSSD
26	VSSA(DA)
25	VDDA(DA)
24	VOR
23	DACR

MBH526

Fig.2 Pin configuration.

1998 Jan 06

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Philips Semiconductors	Product specification
Low-power stereo bitstream ADC/DAC	UDA1309H

FUNCTIONAL DESCRIPTION

Figure 1 illustrates the various components of the UDA1309H.

The analog-to-digital converter is a bitstream type converter, both channels are sampled simultaneously. The digital-to-analog converter is a BCC (Bitstream Continuous Calibration) type converter. The digital filter for the ADC is a bit serial IIR filter that produces a fairly linear phase response up to 15 kHz. A high-pass filter is incorporated in the down-sampling path to remove DC offsets. An overload detection circuit is incorporated to facilitate automatic recording level adjustment.

The digital up-sample filter for the DAC is partly IIR, with virtual linear phase response up to 15 kHz, and partly FIR. A switchable digital de-emphasis circuit is also incorporated. Due to the BCC principle used, the DAC needs only single pole post-filtering (one external capacitor) to meet the out-of-band suppression requirement.

The ADC and DAC channels have separate power-down modes, to reduce power if one of them is not in use.

An analog loop-through function enables analog-input analog-output mode without using the ADC and DAC converters or filters, thereby switching them off to reduce power consumption.

The digital interfaces accommodates, 16 and 18-bit, I2S-bus and LSB justified formats. The ADC digital output can be made 3-state by means of the ADENB signal, this enables the use of a digital bus.

The UDA1309H interface accommodates slave mode only, therefore, the system ICs must provide the system clock, bit clock and word clock signals. For the DAC, the UDA1309H accepts the data together with these clocks, for the ADC it delivers the data in response to these clocks. Within one stereo frame, the first sample always represents the left channel. When sending data the unused bit positions are set to zero, when receiving data these bit positions are don't cares.

To accommodate the various interface formats and system clock frequencies four control pins are provided, MODE0 to MODE2 for mode selection and CLKEDGE which selects the active edge of the BCK signal. Table 1 gives the interface mode selection, Fig.3 illustrates the ADC/DAC data formats and Fig.5 the operating modes.

The section of the UDA1309H is designed to accommodate two main modes:

1.The 256fs mode in which analog-to-digital and digital-to-analog can be used.

2.The 192fs or 384fs mode (digital-to-analog only).

Table 1 Interface mode selection

	DEVICE PIN					ADC/DAC FORMATS
MODE 2	MODE 1		MODE 0	TYPE	BITS		BCK			SYS; fsys	FIGURE
0	0		0	LSB justified	16		32fs			256fs	3(a)
0	0		1	LSB justified	16		64fs			256fs	3(b)
0	1		0	LSB justified	16		48fs			192fs(1)	4(a)
0	1		1	LSB justified	18		64fs			256fs	3(c)
1	0		0	I2S-bus	16		32fs			256fs	3(d)
1	0		1	I2S-bus	16		64fs			256fs	3(e)
1	1		0	I2S-bus	16		48fs			384fs(1)	4(b)
1	1		1	I2S-bus	18		64fs			256fs	3(f)
Note
1. Only digital-to-analog.
Table 2 Clock edge mode
	CLKEDGE					VALID EDGE OF BCK
					ADC					DAC
	0				falling					rising
	1				rising					falling

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Philips Semiconductors	Product specification
Low-power stereo bitstream ADC/DAC	UDA1309H

LSB JUSTIFIED 32fs 16-BIT

BCK

WS

RIGHT

LEFT

SDA

LSB MSB

LSB MSB

LSB MSB

(a)

LSB JUSTIFIED 64fs 16-BIT

BCK

RIGHT

WS

LEFT

SDA

LSB

MSB

LSB

MSB

LSB

(b)

LSB JUSTIFIED 64fs 18-BIT

BCK

RIGHT

WS

LEFT

SDA

LSB

MSB

LSB

MSB

LSB

(c)

I2S 32fs 16-BIT

BCK

LEFT

WS

RIGHT

SDA

LSB MSB

LSB MSB

LSB

(d)

I2S 64fs 16-BIT

BCK

LEFT

WS

RIGHT

SDA

MSB

LSB

MSB

LSB

MSB

(e)

I2S 64fs 18-BIT

BCK

LEFT

WS

RIGHT

SDA

MSB

LSB

MSB

LSB

MSB

(f)

MGE767

Fig.3 DAC and ADC data formats (continued in Fig.4).

1998 Jan 06

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