Philips UCB1100HL-X3C, UCB1100BE Datasheet

INTEGRATED CIRCUITS

UCB1100

Advanced modem/audio analog front-end

Preliminary specification

1998 May 08

Supersedes data of 1996 Apr 09

Version 1.2

m n r

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

Version 1.2

GENERAL DESCRIPTION

The UCB1100 is a single chip, integrated mixed signal audio and telecom codec. The single channel audio codec is designed for direct connection of a microphone and speaker. The built-in telecom codec can directly be connected to a DAA and supports high speed modem protocols. The incorporated 10 bit analogue to digital converter and the touch screen interface provides complete control and readout of a connected 4 wire resistive touch screen. The 10 additional general purpose I/O pins provides programmable inputs and/or outputs to the system.

The UCB1100 has a serial interface bus (SIB) intended to communicate to the system controller. Both the codec input and output data and the control register data is multiplexed on this SIB interface.

APPLICATIONS

•Personal Intelligent Communicators

•Personal Digital Assistants (PDA)

•Screen phones

•Smart Phone and smart Fax

•Intelligent Communicators

KEY FEATURES

•48-pin LQFP (SOT313-2) small body SMD package and low external component count result in minimal PCB space requirement.

•A 12-bit sigma delta audio codec with programmable sample rate, input and output voltage levels, capable of connecting directly to speaker and microphone, including digitally controlled mute, loopback and clip detection functions

•A 14-bit sigma delta telecom codec with programmable sample rate, including digitally controlled input voltage level, mute, loopback and clip detection functions. The telecom codec is intended for direct connection to a DAA (digital access arrangement) and includes a built-in sidetone suppression circuit.

•A complete 4 wire resistive touch screen interface circuit supporting position, pressure and plate resistance measurements.

•A 10-bit successive approximation ADC with internal track and hold circuit and analogue multiplier for touch screen readout and monitoring of four external high voltage (7.5V) analogue voltages.

•A high speed, 4 wire serial interface data bus (SIB) for communication to system controller.

•A 3.3V supply voltage and built in power saving modes make the UCB1100 optimal for portable and battery powered applications.

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . 3 2.0 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . 4 4.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 5 5.0 PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.1 PINLIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.0 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 AUDIO CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1.1 AUDIO INPUT SPECIFICATIONS . . . . . . . . 10 6.1.2 AUDIO OUTPUT SPECIFICATIONS . . . . . . . 11

6.2 TELECOM CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.1 TELECOM INPUT SPECIFICATIONS . . . . . 14 6.2.2 TELECOM OUTPUT SPECIFICATIONS . . . 15

6.3TOUCH SCREEN MEASUREMENT MODES . . . . 16

6.3.1 POSITION MEASUREMENT . . . . . . . . . . . . . 16 6.3.2 PRESSURE MEASUREMENT . . . . . . . . . . . 16 6.3.3 PLATE RESISTANCE MEASUREMENT . . . 16

6.4 TOUCH SCREEN INTERFACE . . . . . . . . . . . . . . . . . 17 6.4.1 TOUCH SCREEN SPECIFICATIONS . . . . . 18 6.5 10 BIT ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21

6.6 ON CHIP REFERENCE CIRCUIT . . . . . . . . . . . . . . 21 6.6.1 SPECIFICATION OVERVIEW . . . . . . . . . . . . 21 6.7 SERIAL INTERFACE BUS . . . . . . . . . . . . . . . . . . . . . 22 6.7.1 SIB DATA FORMAT . . . . . . . . . . . . . . . . . . . . . 23 6.7.2 CODEC DATA TRANSFER . . . . . . . . . . . . . . 24

6.7.3CONTROL REGISTER DATA TRANSFER . 26

6.7.4AC ELECTRICAL CHARACTERISTICS . . . 27

6.8 GENERAL PURPOSE I/Os . . . . . . . . . . . . . . . . . . . . 27 6.9 INTERRUPT GENERATION . . . . . . . . . . . . . . . . . . . 27 6.10 RESET CIRCUITRY . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.0 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 POWER ROUTING STRATEGY . . . . . . . . . . . . . . . . 29 8.0 CONTROL REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . 30

9.0 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 PACKAGE OUTLINE LQFP48 . . . . . . . . . . . . . . . . . . 34 10.0 DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1998 May 08

2

1998May08

Vssa1

Vdda1

2xVssd

2xVddd

test

DIAGRAM BLOCKFUNCTIONAL01.

analog modem/audioAdvanced

SemiconductorsPhilips

micp

gain[3,4]

loopback

gain[0,2]

64fsa

audio_input_enable

mux

64fs

digital

fs

serial bus

micgnd

1 bit ADC

1

decimation

12

filter

sibdout

AUDIO CODEC

blocks digital and analog other all to

encoder

vdda2

vssa1

spkrp

64fs

digital

digital

fs

registers data control

4 bit DAC

volume

noise

spkrn

4

12

control

shaper

serial bus

sibsync

vssa2

attn[0,3]

mute

64fsa

attn[4,5]

controller

sibclk

.1 Figure

audio_output_enable

side tone suppression

telecom input enable

echo on

loopback

effect

attenuation

serial bus

Block

tinp

mux

64fs

digital

fs

front

1 bit ADC

decimation

sibdin

tinn

4

14

filter

decoder

3

Diagram

TELECOM CODEC

fsa

64fsa

fst

64fst

end-

toutp

64fs

digital

fs

internal

reset

4 bit DAC

noise

of

toutn

4

shaper

14

sample

sample

reset

stretcher

nreset

frequency

frequency

the

mute

effect

divider

divider

UCB1100

external

external

telecom output enable

vrefbyp

reference

filter

divaud[0:6]

divtel0:6]

Interrupt

irqout

controller

tsmx

touch screen

touch screen

reference

power

eanble data

interrupt data

tspy

tsmy

for all

from other blocks

bias voltage

voltage

control

analog blocks

rising_edge_ena[0:15]

clear_interrupt[0:15]

vssa3

switch matrix

to external register 11

falling_edge_ena[0:15]

IOmode[0:9]

IOwdat[0:9]

IOrdat[0:9]

ad0

mux

ADC start

adc

switched

10

start

10 bit ADC

ad1

voltage

Programmable IO pin block

ad2

9 to 1

stop logic

sync

dividers

ad3

track & hold

enable

adc_sync_ena

specification Preliminary

digital pin

adcsync

io0

io1

io2

io3

io4

io5

io6

io7

io8

io9

UCB1100

SN00126

analog pin

supply pin

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

2.0 ORDERING INFORMATION

	DESCRIPTION	ORDERING	PACKAGE
		CODE	DRAWING
	Plastic low profile
	quad flat package;	UCB1100LP/X3	SOT313-2
	48 leads

3.0 ABSOLUTE MAXIMUM RATINGS

SYMBOL	PARAMETER	MIN	MAX	UNIT
VDDMAX	Supply voltage	±0.5	5.0	V
VIMAX	DC input voltage, except AD0±3 inputs	±0.5	VDD+0.5	V
VADMAX	DC input voltage AD0±3 inputs	±0.5	8.5	V
VOMAX	DC output voltage	±0.5	VDD+0.5	V
IIKMAX	DC diode input current, all inputs		10	mA
IOKMAX	DC diode output current		10	mA
IOLMAX	Continuous output current, digital outputs		4	mA
Tstg	Storage temperature	±55	150	°C

NOTES:

1.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Absolute Maximum Rating section of this specification is not implied.

2.This product includes circuitry specially designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid submitting the UCB1100 to conditions exceeding the maximum ratings.

3.Parameters are valid over the operating ambient temperature unless otherwise specified. All voltages are with respect to the VSSD pin, unless otherwise noted.

1998 May 08

4

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

4.0 DC ELECTRICAL CHARACTERISTICS

Tamb = 0°C to 70°C, VSSD = VSSA1 = VSSA2 = VSSA3 = 0V, sibclk = 10MHz, audio_divisor = 12, telecom_divisor = 40. Voltage with respect to the VSSD pin, unless otherwise specified.

	SYMBOL	PARAMETER	NOTES		LIMITS		UNIT
				MIN	TYP	MAX
	VDDD	digital supply voltage		3.0	3.3	3.6	V
	VDDA1	analogue supply voltage (excl.speaker driver)		3.0	3.3	3.6	V
	VDDA2	analogue supply voltage (speaker driver only)		3.0	3.3	3.6	V
	VSSA2	analogue ground voltage wrt. VSSD		±0.4	0	0.4	V
	VSSA3	analogue ground voltage wrt VSSD		±0.4	0	0.4	V
	IDDD	digital supply current,	Note 1
		full functionality			19		mA
		only audio codec activated			17		mA
		only telecom codec activated			19		mA
		only touch screen activated			15		mA
		only adc activated			15		mA
		no functions activated, sibclk stopped				10	μA
	IDDA1	analogue supply current,	Note 1, Note 2
		full functionality			3.8		mA
		only audio codec activated			1.5		mA
		only telecom codec activated			1.7		mA
		only touch screen activated			0.4		mA
		only adc activated			0.5		mA
		no analogue functions activated			<10		μA
	IDDA2	total speaker driver supply current	Note 1, Note 2
		full functionality			0.2		mA
		only audio codec activated			0.2		mA
		only telecom codec activated				10	μA
		only touch screen activated				10	μA
		only adc activated				10	μA
		no analogue functions activated				10	μA
	VTSCB	touch screen bias voltage			1.8		V
	ITSCB	maximum touch screen bias current		10			mA
	VADFS	full scale voltage ad0±ad3 inputs			7.5		V
	VTSFS	full scale input touch screen inputs			7.5		V
	VIL	input low voltage		±0.5		0.3*VDDD	V
	VIH	input high voltage		0.7*VDDD		VDDD+0.5	V
	VOL	output low voltage	IOL=2mA			0.2*VDDD	V
	VOH	output high voltage	IOH=2mA	0.8*VDDD			V
	fSIBCLK	clock frequency		0	10	15	MHz
	Tamb	Operating Ambient Temperature		0		70	°C

NOTES:

1.Indicative value only. Value will be frozen following silicon measurements.

2.Excluding connected touch screen and speaker load currents.

1998 May 08

5

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

5.0 PINOUT

	vddd	io6	io5	io4	not used	irqout	sibdin	sibclk	sibdout	sibsync	nreset	vssd
	48	47	46	45	44	43	42	41	40	39	38	37
io7	1											36	io3
io8	2											35	io2
io9	3											34	io1
adcsync	4											33	io0
vssd	5				UCB1100							32	vddd
not used	6											31	not used
						LQFP48
vssa2	7											30	tspx
						TOP VIEW
spkrn	8											29	tsmy
sprkp	9											28	tsmx
vdda2	10											27	tspy
toutp	11											26	vssa3
toutn	12											25	ad0
	13	14	15	16	17	18	19	20	21	22	23	24
	test	tinn	tinp	vrefbyp	vdda1	vssa1	not used	micgnd	micp	ad3	ad2	ad1	SN00127

Figure 2. LQFP48 (SOT313-2)

1998 May 08

6

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

5.1 Pinlist

	SYMBOL	PINNING	PIN TYPE	RESET	DESCRIPTION	NOTE
		LQFP48		STATE
	vddd	32, 48	supply		digital supply
	vssd	5, 37	ground		digital ground	1
	vdda1	17	supply		analogue supply
	vssa1	18	ground		analogue ground	1
	vdda2	10	supply		analogue speaker driver supply
	vssa2	7	ground		analogue speaker driver ground
	vssa3	26	ground		touch screen switch matrix ground
	sibclk	41	CMOS input		SIB serial interface master clock
	sibdin	42	CMOS input		SIB data input
	sibdout	40	CMOS output	`0' / Hi-Z	SIB data output	2
	sibsync	39	CMOS input		SIB synchronization
	irqout	43	CMOS output	`0'	interrupt output
			active-High
	micp	21	analogue input	Hi-Z	microphone signal input
	micgnd	20	analogue input	Hi-Z	microphone ground switch input
	sprkp	9	analogue output	Hi-Z	positive speaker output	3
	spkrn	8	analogue output	Hi-Z	negative speaker output	3
	tinp	15	analogue input	Hi-Z	positive telecom codec input	3
	tinn	14	analogue input	Hi-Z	negative telecom codec input	3
	toutp	11	analogue output	Hi-Z	positive telecom codec output	3
	toutn	12	analogue output	Hi-Z	negative telecom codec output	3
	ad0±3	25±22	analogue input	Hi-Z	analogue high voltage inputs
	tspx	30	analogue IO	Hi-Z	positive X-plate touch screen
	tsmx	28	analogue IO	Hi-Z	negative X-plate touch screen
	tspy	27	analogue IO	Hi-Z	positive Y-plate touch screen
	tsmy	29	analogue IO	Hi-Z	negative Y-plate touch screen
	adcsync	4	digital input		adc synchronization pulse input
	vrefbyp	16	analogue IO	Hi-Z	external reference voltage input, external filter connection
	io0±9	33±36,	CMOS IO	input	general purpose IO pins
		45±47,
		1±3
	nreset	38	CMOS input		asynchronous reset input
			active-Low
	test	13	CMOS input	`0'	test mode protection	4
	not used	6, 19,			not connected pins
		31, 44

NOTES:

1.The vssd and vssa1 pins are connected to each other within the UCB1100.

2.The first 64 bits of the sib frame will be `0', the remaining bits in the sib frame will be Hi-Z.

3.The spkrp/spkrn, tinp/tiln and toup/toutn are differential pairs.

4.The test pin contains a internal pull down. This pin should be connected to vssd in normal mode of the UCB1100.

1998 May 08

7

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

6.0 FUNCTIONAL DESCRIPTION

The UCB1100 consists of several analogue and digital sub circuits which can be programmed via the Serial Interface Bus (SIB). This enables the user to set the UCB1100 functionality according actual application requirements.

6.1 Audio codec

The audio codec contains an input channel, built up from a 64 times oversampling sigma delta analogue to digital converter (ADC) with digital decimation filters and a programmable gain microphone preamp. The output path consists of a digital up sample filter, a 64 time oversampling 4 bit digital to analogue converter (DAC) circuit followed by a speaker driver, capable of driving directly a low impedance bridge tied (BTL) speaker. The output path features digitally programmable attenuation and a mute function. The audio codec also incorporates a loopback mode, in which codec output path and the input path are connected in series.

The audio sample rate is derived from the SIB interface clock pin (SIBclk) and is programmable through the SIB interface. The audio sample rate is given by the following equation:

For example, a serial clock of 10 MHz, with a divisor of 14, results in an audio sample rate of 22.321kHz. Both the rising and the falling edges of the sibclk are used in case an odd audio_divisor is set. Thus a 50% duty cycle of the sibclk signal is mandatory to obtain time equidistant sampling with odd divisors.

The frequency response of the audio codec depends mainly on the selected sample rate, since the bandwidth is limited in the down and up sampling filters. These digital filters both contain several FIR and IIR low pass filters and a DC removal filter (high pass filter). A 1st order analogue anti aliasing filter is implemented at the input of the microphone input to prevent aliasing in the adc path. A 3rd order smoothing filter is implemented between dac and speaker driver stage to reduce the spurious frequencies at the speaker outputs.

The audio codec input (=ADC) and output (= DAC) paths can be enabled individually by setting the audio_adc and/or audio_dac bits in the audio control register B. These enable bits operate both on the associated analogue and digital functions, for optimal power control of both the analogue and the digital parts.

(2 * Fsibclk)
Fsa (64 * audio_divisor)	(5 audio_divisor			128)
micp	gain[3,4]	loopback	gain[0,2]		64fsa		audio_input_enable
		mux				64fs
micgnd					1 bit ADC	1
		loop input
vssa1
									fs
							+3dB	round	12
								up
				16			2	2
			Sinc4		DC	half band	half band
			FIR		removal	WDF	WDF
	low pass	half band				half band		DC
interpolator	FIR		FIR			WDF		removal
									fs
					round		+3dB		12
					up
4		2		2			2	2
							noise
vdda2		loop input					shaper
spkrp						64fs	digital
					4 bit DAC		volume
spkrn						4
							control
vssa2			attn[0,3]
		mute			64fsa		attn[4,5]
							audio_output_enable
									SN00128

Figure 3. Detailed Block Diagram Audio codec

1998 May 08

8

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

UCB1100	UCB1100
vdda1	vdda1
micp	micp
micgnd	micgnd
vssa1	vssa1

`Passive' Microphone `Active' Microphone

SN00129

Figure 4. Possible Microphone Connections

The UCB1100 audio codec input path accepts microphone signals directly, only a DC blocking capacitor is needed, since the micp input is biased around 1.4V. The `ground' side of the microphone is either connected to the analogue ground (vssa1) or to the micgnd pin of the UCB1100. The latter will decrease the current consumption of active microphones, since the micgnd pin is made Hi-Z when the audio codec input path is disabled.

The full scale input voltage of the audio input path is programmable in 1.5dB steps by setting the appropriate data in the audio-input-gain bits in the audio control register A.

The output level can be attenuated in 3dB steps down to -69dB. The 8 highest attenuation steps are implemented in the analogue circuitry, while the two 24dB steps are implemented in the digital domain. This preserves the `audio quality' of the output signal at lowest attenuation settings. The speaker driver is muted when the audio-mute bit in the audio control register B is set. The speaker driver will remain activated in that case, however no signal is produced by the speaker driver circuitry.

UCB1100	UCB1100	UCB1100
spkrp	spkrp	spkrp
spkrn	spkrn	spkrn

Bridge Tied	Single Ended Speaker Connections
Speaker
Load	SN00131
Figure 6.	Possible Speaker Connections

A clip detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage. In that case the clip detect status bit in audio control register B is set. An interrupt is generated on the irqout pin of the UCB1100 whenever the enable audio clip detect rising interrupt or the enable audio detect falling edge interrupt bit is set in the rising edge interrupt enable or falling edge interrupt control register B is set.

	48dB
attenuation	24dB
digital
	0dB
analog attenuation	21dB
	0dB
	24dB	48dB	69dB
	programmed attenuation
			SN00130

The speaker driver is designed to directly drive a bridge tied load (BTL). This yields the highest output power and it does not require external DC blocking capacitors. The speaker driver also accepts single ended connection of a speaker, in which case the maximum output power is reduced to a quarter of the BTL situation. Consequently this way of connecting the speaker to the speaker driver reduces the power consumption of the speaker driver in the UCB1100 by a factor of 2. Figure 6 shows possible ways to connect a speaker to the UCB1100.

The audio input and output path are activated independently; the input path is enabled when the audio-input-enable bit is set, the output path is enabled when the audio-output-enable bit is set in the audio control register B. This provides the user the means to reduce the current consumption of the UCB1100 if one part of the audio codec is not used in the application.

The audio codec has a loopback mode for system test purposes, which is activated when the audio_loopback enable bit in the audio control register B is set. This is an analogue loopback which internally connects the output of the audio output path to the input of the audio input path, (see Figure 3). In this mode the normal microphone input is ignored, but the speaker driver can be operated normally.

Figure 5. Analogue and Digital Attenuation Settings

Audio Output Path

1998 May 08

9

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

6.1.1 Audio Input Specifications

	SYMBOL	PARAMETER	CONDITIONS		LIMITS		UNIT
				MIN	TYP	MAX
	FSA	audio sample frequency				26	kHz
	VINAM	full scale input voltage	0 dB gain setting		0.28		Vpp
	VMICP	DC bias voltage micp input	audio input path enabled		1.4		V
	RINPAI	input impedance	audio input path enabled		25		kΩ
	RHINE	impedance micgnd to vssa1	audio input path enabled			100	Ω
	GSA	gain step size		1.3	1.5	1.7	dB
	NAGS	number of gain steps			32
	GmA	maximum gain			46.5		dB
	GEAR	gain error (accuracy of gain setting)	0 dB gain setting,	±1	0	1	dB
			full scale input voltage
	ROESAI	resolution audio input			12		bit
	DNAAI	differential non linearity audio input ADC				0.9	LSB
	THUDAI	total harmonic distortion	0db input gain selected			0.03	%
			0.28Vpp, 1kHz to micp
	THDMGAI	total harmonic distortion	46.5dB gain setting,			0.1	%
			1mVpp, 1kHz to micp
	SNRAI	signal to noise ratio	0dB input gain selected	65			dB
		audio input	0.28Vpp, 1kHz to micp
	SNRMGAI	signal to noise ratio	46.5dB gain selected	50			dB
			1mVpp, 1kHz to micp
	RIPIA	pass band ripple	FPLAI <Fsig < FPHAI			0.5	dB
	SBRIA	stop band rejection	FSHAI<Fsig.<20kHz	70			dB
		audio input
	EIA	out of band rejection	F > 20kHz		t.b.f.		mVrms
		audio input

NOTE: Coding scheme for ADC output data is 2's complement.

	RIPIA
0dB
SBRIA
FPLA	FPHA	FSHA

FREQUENCY (Hz)

SN00132

Figure 7. Audio Input Path Frequency Response

FPLA = 0.00016 * FSA

FPHA = 0.42 * FSA

FSHA = 0.6 * FSA

1998 May 08

10

Philips Semiconductors	Preliminary specification
Advanced modem/audio analog front-end	UCB1100

6.1.2 Audio Output Specifications

	SYMBOL	PARAMETER	CONDITIONS		LIMITS		UNIT
				MIN	TYP	MAX
	VOFFIA	offset error	No signal applied to micp		0		LSB
			0dB attenuation,
	VOOA	full scale output voltage	16ohm speaker		3.2		Vpp
			differential Spkrp±Spkrn
	VOFFOA	offset error	16ohm speaker			50	mVpp
	VSPK	DC bias voltage	Audio output path enabled		1.4		V
		spkrp and spkrn pin
	ASOA	attenuation step size		2.8	3.0	3.2	dB
	NSOA	number of attenuation steps			24
	AMOA	maximum attenuation			69		dB
	ROESOA	resolution			12		bit
	DNAOA	differential non linearity DAC				0.9	LSB
	THUDOAS	total harmonic distortion	0dB attenuation		0.5	2	%
		16Ω speaker	20Hz to 20kHz
	THUDOAH	total harmonic distortion	0dB attenuation			0.03	%
		1kΩ headphone	20Hz to 20kHz bandwidth
	SNROAS	signal to noise ratio	0dB attenuation	40	80		dB
		16Ω speaker	20Hz to 20kHz bandwidth
	SNROAH	signal to noise ratio,	0dB attenuation	65	80		dB
		1kHΩ headphone	20Hz to 20kHz bandwidth
	RIPOA	pass band ripple	FPLAO < Fsig <± FPHAO			0.5	dB
	FSUOA	cut off frequency upper stop band				0.6	FSA
	SBROA	stop band rejection	FSHAO<Fsig.<20kHz	70			dB
	EIOA	integrated out of band energy	F > 20kHz		30		mVrms
	ZSPKR	speaker impedance		8	16		Ω

NOTE: Coding scheme for DAC input data is 2's complement.

	RIPOA
0dB
SBROA
FPLA	FPHA	FSHA

FREQUENCY (Hz)

SN00133

Figure 8. Audio Output Filter Frequency Response

FPLA = 0.00016 * FSA

FPHA = 0.42 * FSA

FSHA = 0.6 * FSA

1998 May 08

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