Philips tsa5526 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TSA5526; TSA5527

1.3 GHz universal bus-controlled TV synthesizers

Product speciﬁcation Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02

1996 Sep 24

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TV synthesizers

FEATURES

• Complete 1.3 GHz single chip system

• Four PNP band switch buffers (40 mA)

• 33 V output tuning voltage

• In-lock detector

• 5-step ADC

• 15-bit programmable divider

• Programmable reference divider ratio

(512, 640 or 1024)

• Programmable charge-pump current (60 or 280 µA)

• Programmable automatic charge-pump current switch

• Varicap drive disable

• Universal bus protocol I – bus protocol for 18 or 19 bits transmission

(3-wire bus)

– extra protocol for 27 bits for test and features

(3-wire bus)

– address plus 4 data bytes transmission (I2C-bus write

mode)

– address plus 1 status byte transmission (I2C-bus

read mode)

– three independent I2C-bus addresses

• Low power and low radiation.

C-bus or 3-wire bus:

TSA5526; TSA5527

APPLICATIONS

• TV tuners and front ends

• VCR tuners.

ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TSA5526M SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5526T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSA5527M SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5527T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSA5526AM SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5526AT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TSA5527AM SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1 TSA5527AT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

1996 Sep 24 2

PACKAGE

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TSA5526; TSA5527

TV synthesizers

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CC1

CC2

CC1

CC2

i(RF)

xtal

o(PNP)

tot

stg

amb

supply voltage (+5 V) 4.5 − 5.5 V band switch supply voltage (12 V) V

CC1

12 13.5 V supply current − 20 25 mA band switch supply current note 1 − 50 55 mA RF input frequency 64 − 1300 MHz RF input voltage fi= 80 to 150 MHz −25 − 3 dBm

= 150 to 1000 MHz −28 − 3 dBm

= 1000 to 1300 MHz −15 − 3 dBm

crystal oscillator input frequency 3.2 4.0 4.48 MHz PNP band switch buffers output

note 2 4 − 50 mA

current total power dissipation note 3 − 250 400 mW storage temperature −40 − +150 °C operating ambient temperature −20 − +85 °C

Notes

1. One band switch buffer ON, I

= 40 mA.

2. One band switch buffer ON, Io= 40 mA; two buffers ON, maximum sum of Io=50mA.

3. The power dissipation is calculated as follows: P

CC1ICC1VCC2ICC2Io

–()I

CE satPNP()

V33 2⁄()

27⁄+×+×+×=

kΩ.

1996 Sep 24 3

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TV synthesizers

GENERAL DESCRIPTION

The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output. Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA.

Depending on the reference divider ratio (512, 640 or

1024), the phase comparator operates at 3.90625 kHz,

6.25 kHz or 7.8125 kHz using a 4 MHz crystal.

The device can be controlled in accordance with the

C-bus format or the 3-wire bus format depending on the

I voltage applied to the SW input (see Table 2). In the 3-wire bus mode (SW = HIGH) pin 12 is the LOCK output. The lock output is LOW when the PLL loop is locked. In the I2C-bus mode (SW = LOW) the LOCK detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. The ADC input is available on pin 12 for AFC control in the I2C-bus mode only. The ADC code is read during a read operation on the I2C-bus. In the test mode pin 12 is used as a test output for f

and1⁄2f

ref

(see Table 6). When the automatic charge-pump current switch mode is

activated, depending on the device given in Table 6, and when the loop is phase-locked, the charge-pump current value is automatically switched to LOW.

in the I2C-bus mode and the 3-wire bus mode

div

TSA5526; TSA5527

This action is taken to improve the carrier-to-noise ratio. The status of this feature can be read in the ACPS flag during a read operation on the I

C-bus format (SW = LOW)

Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four PNP band switch buffers, set the charge-pump current and the reference divider ratio.

The device has three independent I2C-bus addresses which can be selected by applying a specific voltage on the CE input (see Table 5). The general address C2 is always valid. When the I2C-bus format is fully used, TSA5526 and TSA5527 are equal.

3-wire bus format (SW = V

Data is transmitted to the device during a HIGH level on the CE input (enable line pin 15). The device is compatible with 18-bit and 19-bit data formats. The first four bits are used to program the PNP band switch buffers and the remaining bits are used to control the programmable divider. A 27-bit data format may also be used to set the charge-pump current, the reference divider ratio and for test purposes. The differences between TSA5526 and TSA5527 are given in Table 1.

When the 27-bit format is used, the TSA5526 and TSA5527 are equal and the reference divider is controlled by the RSA and RSB bits (see Table 7 and Figs 3, 4 and 5).

C-bus (see Table 8).

or open-circuit)

CC1

Table 1 Differences between TSA5526 and TSA5527

TYPE NUMBER DATA WORD REFERENCE DIVIDER FREQUENCY STEP (kHz)

TSA5526 18-bit 512 TSA5526 19-bit 1024 TSA5527 19-bit 640

Notes

1. The selection of the reference divider is given by an automatic identification of the data word length.

2. The reference divider is set to 640 at power-on reset.

1996 Sep 24 4

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62.5

31.25 50

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TV synthesizers

BLOCK DIAGRAM

tune

AMP

PUMP

CHARGE

PHASE

DIGITAL

COMPARATOR

T2,T1,T0

LOGIC

IN-LOCK

DETECTOR

lock

CC1

RSA,RSB

7-BIT CONTROL

LOCK/

T2,T1,T0

TSA5526; TSA5527

ADC

MBE327

div

ref

15-BIT

DIVIDER

PROGRAMMABLE

DIVIDER

DIVIDE-BY-8

PRESCALER

handbook, full pagewidth

512/640/1024

XTAL

OSCILLATOR

XTAL

15-BIT FREQUENCY

RSA RSB

RESET

POWER-ON

I C/3-WIRE BUS

SCL

SDA

GATE

4-BIT BAND SWITCH

TRANSCEIVER

5-LEVEL

ADC

TSA5526

TSA5527

BS4

BS3

BS2

BS1

CC2

Fig.1 Block diagram.

1996 Sep 24 5

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TV synthesizers

PINNING

SYMBOL PIN DESCRIPTION

RF 1 RF signal input V

CC1

CC2

BS4 5 PNP band switch buffer output 4 BS3 6 PNP band switch buffer output 3 BS2 7 PNP band switch buffer output 2 BS1 8 PNP band switch buffer output 1 CP 9 charge-pump output V

tune

SW 11 bus format selection input, I

LOCK/ADC 12 lock detector output (3-wire bus/

SCL 13 serial clock input SDA 14 serial data input/output CE 15 chip enable/address selection input XTAL 16 crystal oscillator input

2 ground 3 supply voltage (+5 V) 4 band switch supply voltage (+12 V)

10 tuning voltage output

C-bus

or 3-wire

ADC input (I

C-bus)

handbook, halfpage

TSA5526; TSA5527

CC1

CC2

BS4 BS3 BS2 BS1

Fig.2 Pin configuration.

5 6 7 8

TSA5526 TSA5527

MBE326

XTAL

16 15

SDA SCL

13 12

LOCK/ADC

SW V

tune

FUNCTIONAL DESCRIPTION

The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are CE (Chip Enable), SDA (serial data input) and SCL (serial clock input). A LOW level on the SW input enables the I2C-bus inputs which are AS (Address Selection input), SDA (serial data input/output) and SCL (serial clock input). The bus format selection is given in Table 2.

C-bus mode (SW = LOW); see Table 3

RITE MODE (R/W = 0)

Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes).

The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3.

The first bit of the first data byte transmitted indicates whether frequency data (first bit = logic 0) or control and band switch data (first bit = logic 1) will follow. Until an

C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to readdress the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB).

C-BUS ADDRESS SELECTION

I The module address contains programmable address bits

(MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input.

The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 5.

1996 Sep 24 6

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TSA5526; TSA5527

TV synthesizers

Table 2 Bus format selection

PIN NAME 3-WIRE BUS MODE I

11 SW OPEN or HIGH LOW 12 LOCK/ADC LOCK/TEST output ADC input/TEST output 13 SCL clock input SCL input 14 SDA data input SDA input/output 15 CE chip enable input address selection input

Table 3 I

C-bus data format

BYTE MSB DATA BYTE LSB

Address Byte (ADB) 1 1000MA1MA0R/W=0 A Divider Byte 1 (DB1) 0 N14 N13 N12 N11 N10 N9 N8 A Divider Byte 2 (DB2) N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte (CB) 1 CP T2 T1 T0 RSA RSB OS A Band switch Byte (BB) X X X X BS4 BS3 BS2 BS1 A

C-BUS MODE

SLAVE

ANSWER

Table 4 Description of Table 3

SYMBOL DESCRIPTION

A acknowledge MA1 and MA0 programmable address bits (see Table 5)

N14 to N0 programmable divider bits; N = N14 × 2

+ N13 × 213+...+N1×2+N0 CP charge-pump current; CP = 0 = 60 µA; CP = 1 = 280 µA (default) T2 to T0 test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 (default) RSA and RSB reference divider ratio select bits (see Table 7) OS tuning ampliﬁer control bit; for normal operation OS = 0 and tuning voltage is ON (default);

when OS = 1 tuning voltage is OFF (high impedance)

BS4 to BS1 PNP band switch buffers control bits; when BS

= 0 buffer n is OFF; when BSn= 1 buffer n

is ON

X don’t care

Table 5 I

C-bus address selection

VOLTAGE APPLIED TO THE CE INPUT (SW = LOW) MA1 MA0

0 V to 0.1V

CC1

Always valid 0 1

0.4V

0.9V

CC1 CC1

to 0.6V to V

CC1

10 11

1996 Sep 24 7

Philips Semiconductors Product speciﬁcation

1.3 GHz universal bus-controlled TSA5526; TSA5527

TV synthesizers

Table 6 Test bits

T2 T1 T0 TSA5526; TSA5527 TSA5526A; TSA5527A REMARKS

0 0 0 normal operation with automatic

charge-pump switch ON

0 0 1 normal operation with automatic

charge-pump switch OFF 0 1 X charge-pump is OFF charge-pump is OFF 1 1 0 charge-pump is sinking current charge-pump is sinking current 1 1 1 charge-pump is sourcing current charge-pump is sourcing current 100f

101

is available at LOCK output f

ref

⁄2f

is available at LOCK output

div

Table 7 Ratio select bits

RSA RSB REFERENCE DIVIDER

X 0 640 0 1 1024 1 1 512

automatic charge-pump switch OFF

automatic charge-pump switch ON status at POR

is available at LOCK output the ADC cannot be used

ref

when test mode is active

⁄2f

is available at LOCK output the ADC cannot be used

div

when test mode is active

The device will then release the data line to allow the microcontroller to generate a stop condition. The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with the in-lock flag (FL) which indicates when the loop is locked (FL = logic 1).

EAD MODE (R/W = LOGIC 1); see Table 8

R Data can be read from the device by setting the R/W bit to

logic 1. After the slave address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge

The Automatic Charge-Pump Switch flag (ACPS) is LOW when the automatic charge-pump switch mode is ON and the loop is locked. In other conditions ACPS = logic 1. When ACPS = logic 0, the charge-pump current is forced to the LOW value.

A built-in ADC is available at pin 12 (I2C-bus only). This converter can be used to apply AFC information to the microcontroller from the IF section of the television. The relationship between the bits A2 to A0 is given in Table 9.

occurs.

Table 8 Read data format

BYTE MSB DATA BYTE LSB

ANSWER

Address Byte (ADB) 1 1 0 0 0 MA1 MA0 R/W = 1 A Status Byte (SB) POR

(2)

(3)

ACPS

(4)

11A2

(5)

Notes

1. A = acknowledge.

2. POR = power-on reset flag (POR = logic 1 at power-on).

3. FL = in-lock flag (FL = logic 1 when the loop is locked).

4. ACPS = automatic charge-pump switch flag (active ACPS = logic 0; non-active ACPS = logic 1).

5. A2 to A0 = digital outputs of the 5-level ADC.

SLAVE

(1)

−

1996 Sep 24 8

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