Philips tsa5523m DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TSA5523M

1.4 GHz I

C-bus controlled

multimedia synthesizer

Product speciﬁcation File under Integrated Circuits, IC02

1996 Dec 17

Philips Semiconductors Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia synthesizer

FEATURES

• Complete 1.4 GHz single-chip system

• Adaptive DC/DC converter driver output

• On-board tuning amplifier output

• Varicap drive disable

• Four NPN open-collector output ports (10 mA)

• Four bus-controlled bidirectional ports

(NPN open-collector outputs)

• In-lock detector

• 5-step Analog-to-Digital Converter (ADC)

• Mixer/Oscillator (M/O) band-switch output

• 15-bit programmable divider

• Programmable reference divider ratio

(512, 640 or 1024)

• Programmable charge-pump current (50 or 250 µA)

C-bus format

• I – Address plus four data bytes transmission

(write mode)

– Address plus one status byte transmission

(read mode)

– Four independent addresses

• Low power, low radiation.

TSA5523M

An output is provided to control a Philips mixer/oscillator IC controlled by bits P7, P5 and P4. Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 3.90625, 6.25 or 7.8125 kHz with a 4 MHz crystal.

The lock detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. The ADC is available for digital AFC control. The ADC code is read during a read operation on

the I

C-bus. The ADC input is combined with the port P6. In the test mode, this port is also used as a test output for f

and f

ref

a DC/DC converter driver connected to the IDC pin to control the amplitude of an external oscillator followed by a voltage rectifier.

The voltage rectifier is used to generate the correct tuning supply voltage to maintain a constant current into the tuning amplifier. The DC/DC converter driver can be disabled by setting the IDC pin to V tuning supply voltage is delivered by a fixed 33 V supply.

(see Table 4). In addition, the circuit includes

div/2

in this event the

CC1

GENERAL DESCRIPTION

The device is a single chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider, a phase/frequency detector combined with a charge-pump which drives the tuning amplifier, including 33 V output. Three NPN open-collector outputs are provided for band switching together with five open-collector NPN outputs. Four of these ports can also be used as input ports (one ADC and three general purpose I/O ports).

ORDERING INFORMATION

TYPE

NUMBER

TSA5523M/C1 SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

NAME DESCRIPTION VERSION

Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the ports, set the charge-pump current and set the reference divider ratio. The device has four independent I2C-bus addresses which can be selected by applying a specific voltage on the AS input (see Table 3).

APPLICATIONS

• Multimedia TV tuners and front-ends

• VCR tuners.

PACKAGE

1996 Dec 17 2

Philips Semiconductors Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia TSA5523M

synthesizer

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CC1

iRF

XTAL

NPN

amb

stg

supply voltage 4.5 − 5.5 V supply current − 22 30 mA RF frequency range 64 − 1400 MHz RF input voltage level 80 to 150 MHz −25 − +3 dBm

150 MHz to 1 GHz −28 − +3 dBm

1 to 1.4 GHz −26 − +3 dBm crystal oscillator frequency − 4 − MHz NPN open-collector output

− 10 15 mA

current operating ambient temperature −20 − +85 °C IC storage temperature −40 − +150 °C

1996 Dec 17 3

Philips Semiconductors Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia synthesizer

BLOCK DIAGRAM

tune

AMP

BUMP

CHARGE

PHASE

COMPARATOR

LOGIC

T2, T1, T0

handbook, full pagewidth

IDC

DC/DC

DRIVER

DIGITAL

IN-LOCK

DETECTOR

LOCK

CC1

RSA, RSB

GND

7-BIT CONTROL

T2, T1, T0

BAND

SWITCH

TSA5523M

MGG747

div

15-BIT

DIVIDER

PROGRAMMABLE

DIVIDE-BY-8

PRESCALER

RF1

RF2

ref

DIVIDER

512/640/1024

XTAL

OSCOLLATOR

XTAL

TSA5523M

15-BIT

RSBRSA

POWER-ON

FREQUENCY

RESET

C-BUS

TRANSCEIVER

SCL

SDA

8-BIT PORTS

GATE

COMPARATORS

ADC

Fig.1 Block diagram.

13 12 11 15 5 6 7 14

P3 P2 P1 P0 P6 P4 P5 P7

1996 Dec 17 4

Philips Semiconductors Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia synthesizer

PINNING

SYMBOL PIN DESCRIPTION

XTAL 1 crystal oscillator input AS 2 address selection input SDA 3 serial data input/output SCL 4 serial clock input P4 5 Port 4 NPN open-collector

band-switch output

P5 6 Port 5 NPN open-collector

band-switch output

P7 7 Port 7 NPN open-collector

band-switch output

IDC 8 DC/DC converter control I/O

terminal

tune

CP 10 NPN open-collector I/O port P0 11 Port 0 NPN open-collector I/O port P1 12 Port 1 NPN open-collector I/O port P2 13 Port 2 NPN open-collector I/O port P3 14 Port 3 NPN open-collector output P6 15 Port 6 NPN open-collector

GND 16 ground BS 17 band-switch output to

RF2 18 RF signal input 2 RF1 19 RF signal input 1 V

CC1

9 tuning voltage output

output/ADC input

mixer/oscillator driver

20 supply voltage (+5 V)

handbook, halfpage

XTAL

SDA

SCL

TSA5523M

7 8

IDC

tune

MGG746

Fig.2 Pin configuration.

TSA5523M

CC1

RF1

RF2

GND P6

1996 Dec 17 5

Philips Semiconductors Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia synthesizer

FUNCTIONAL DESCRIPTION

The device is controlled via the two-wire I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for selecting the read or the write mode.

Write mode: R/

After the address transmission (first byte), data bytes can be sent to the device. Four data bytes are needed to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes).

The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or Control Byte (CB). The meaning of the bits in the data bytes is given in Table 1.

Table 1 I2C-bus data format

W=0(see Table 1)

TSA5523M

The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and ports data (first bit = 1) will follow. Until an I condition is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the control byte and the ports register is loaded after the 8th clock pulse of the Ports Byte (PB).

C-bus address selection

The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 4) in one system by applying a specific voltage to the AS input. The relationship between MA1 and MA0 and the input voltage on the AS input is given in Table 2.

C-bus STOP

DATA BYTES MSB LSB ACK

Address Byte (ADR) 11000MA1MA00A Divider Byte 1 (DB1) 0 N14 N13 N12 N11 N10 N9 N8 A Divider Byte 2 (DB2) N7 N6 N5 N4 N3 N2 N1 N0 A Control Byte (CB) 1 CP T2 T1 T0 RSA RSB OS A Ports Byte (PB) P7 P6 P5 P4 P3 P2 P1 P0 A

(1) (1) (1) (1) (1)

Note

1. A = Acknowledge.

Table 2 Explanation to Table 1

SYMBOL DESCRIPTION

MA1 and MA0 programmable address bits (see Table 3) N14 to N0 programmable divider bits N = N14 × 2

14+213

+ ... + N1 × 2+N0 CP charge-pump current CP = 0 50 µA CP = 1 250 µA T2, T1 and T0 test bits; normal operation; T2 = 0, T1 = 0, T0 = 1 (see Table 4) RSA and RSB reference divider ratio select bits (see Table 5) OS tuning ampliﬁer control bit OS = 0 normal operation; tuning voltage is ON OS = 1 tuning voltage is OFF (high impedance), IDC output voltage is LOW P7 to P0 NPN open-collector control bits Pn = 0 output n is OFF Pn = 1 output n is ON

1996 Dec 17 6

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