INTEGRATED CIRCUITS
TEA6360
5-band stereo equalizer circuit
Preliminary specification |
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May 1991 |
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File under Integrated Circuits, IC01 |
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Philips Semiconductors |
Preliminary specification |
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5-band stereo equalizer circuit |
TEA6360 |
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FEATURES
∙Monolithic integrated 5-band stereo equalizer circuit
∙Five filters for each channel
∙Centre frequency, bandwidth and maximum boost/cut defined by external components
∙Choise for variable or constant Q-factor via I2C software
∙Defeat mode
∙All stages are DC-coupled
∙I2C-bus control for all functions
∙Two different modul addresses programmable.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The 5-band stereo equalizer is an 12C-bus controlled tone processor for application in car radio sets, TV sets and music centres. It offers the possibility of sound control as well as equalization of sound pressure behaviour of different rooms or loudspeakers, especially in cars.
SYMBOL |
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PARAMETER |
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MIN. |
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TYP. |
MAX. |
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UNIT |
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Vp |
supply voltage (pin 14) |
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7 |
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8.5 |
13.2 |
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V |
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Ip |
supply current |
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− |
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24.5 |
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mA |
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V1,32 |
input voltage range |
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− |
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2.1 to |
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VP−1 |
− |
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V |
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Vo |
maximum output signal level |
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- |
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(RMS value, pins 13 and 20) |
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1.1 |
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− |
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V |
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Gv |
total signal gain, all filters linear |
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−0.5 |
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0 |
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dB |
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B |
−1 dB frequency response (linear) |
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0 to 20 |
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− |
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kHz |
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Tamb |
operating ambient temperature |
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−40 |
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− |
85 |
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°C |
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ORDERING INFORMATION |
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EXTENDED |
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PACKAGE |
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TYPE NUMBER |
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PINS |
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PIN POSITION |
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MATERIAL |
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CODE |
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TEA6360(1) |
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32 |
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shrink DIL |
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plastic |
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SOT232 |
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TEA6360/T(2) |
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32 |
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mini-pack |
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plastic |
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SOT287 |
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Notes
1.SOT232; SOT232-1; 1996 August 08.
2.SOT287; SOT287-1; 1996 August 08.
May 1991 |
2 |
Philips Semiconductors |
Preliminary specification |
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5-band stereo equalizer circuit |
TEA6360 |
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Fig.1 Block diagram, test and application circuit.
May 1991 |
3 |
Philips Semiconductors |
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Preliminary specification |
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5-band stereo equalizer circuit |
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TEA6360 |
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PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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ViL |
1 |
audio frequency input LEFT |
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F1LA |
2 |
connection A for filter 1 LEFT (f = 2.95 kHz) |
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n.c. |
3 |
not connected |
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F1LB |
4 |
connection B for filter 1 LEFT (f = 2.95 kHz) |
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F2LA |
5 |
connection A for filter 2 LEFT (f = 12 kHz) |
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F2LB |
6 |
connection B for filter 2 LEFT (f = 12 kHz) |
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F3LA |
7 |
connection A for filter 3 LEFT (f = 790 Hz) |
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F3LB |
8 |
connection B for filter 3 LEFT (f = 790 Hz) |
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F4LA |
9 |
connection A for filter 4 LEFT (f = 205 Hz) |
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F4LB |
10 |
connection B for filter 4 LEFT (f = 205 Hz) |
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F5LA |
11 |
connection A for filter 5 LEFT (f = 59 Hz) |
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F5LB |
12 |
connection B for filter 5 LEFT (f = 59 Hz) |
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VoL |
13 |
audio frequency output LEFT |
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VP |
14 |
supply voltage (+8.5 V) |
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SDA |
15 |
I2C-bus data line |
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SCL |
16 |
I2C-bus clock line |
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GND2 |
17 |
ground 2 (I2C-bus ground) |
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MAD |
18 |
modul address |
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GND1 |
19 |
ground 1 (analog ground) |
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VoR |
20 |
audio frequency output RIGHT |
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F5RB |
21 |
connection B for filter 5 RIGHT (f = 59 Hz) |
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F5RA |
22 |
connection A for filter 5 RIGHT (f = 59 Hz) |
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Fig.2 Pin configuration |
F4RB |
23 |
connection B for filter 4 RIGHT (f = 205 Hz) |
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F4RA |
24 |
connection A for filter 4 RIGHT (f = 205 Hz) |
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F3RB |
25 |
connection B for filter 3 RIGHT (f = 790 Hz) |
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F3RA |
26 |
connection A for filter 3 RIGHT (f = 790 Hz) |
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F2RB |
27 |
connection B for filter 2 RIGHT (f = 12 kHz) |
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F2RA |
28 |
connection A for filter 2 RIGHT (f = 12 kHz) |
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F1RB |
29 |
connection B for filter 1 RIGHT (f = 2.95 kHz) |
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n.c. |
30 |
not connected |
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F1RA |
31 |
connection A for filter 1 RIGHT (f = 2.95 kHz) |
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ViR |
32 |
audio frequency input RIGHT |
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May 1991 |
4 |
Philips Semiconductors |
Preliminary specification |
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5-band stereo equalizer circuit |
TEA6360 |
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FUNCTIONAL DESCRIPTION
The TEA6360 is performed with two stereo channels (RIGHT and LEFT), each one consists of five equal filter amplifiers (Fig.1).
The centre frequencies for the different filters as well as the bandwidth and the control ranges for boost and cut depend on the external components. Each filter can have different external components but for one definite pair of filters the centre frequency as well as the control range for boost and cut are the same. That means, they have symmetrical curves for boost and cut.
The control range (maximum value in dB) is divided into five steps and one extra step for the linear position.
At maximum gain of 12 dB the typical step resolution is 2.4 dB. The internal resistor chain of each filter amplifier is optimized for 12 dB maximum gain. Therefore the typical gain factors for 15 dB application are as follows:
step 1 |
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2.7 |
dB |
step 2 |
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5.5 |
dB |
step 3 |
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8.4 |
dB |
step 4 |
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11.6 |
dB |
step 5 |
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15.0 |
dB |
The position of the filter in the left channel and that in the right channel is always the same (stereo).
The position of the boost part and the cut part is independently controllable (Tables 2 and 3).
The quality factor of the filter has its maximum in the maximum position (steps 5), if boost (cut on step 0) or cut (boost on step 0) is used. The quality factor decreases also with the step number (variable quality factor).
In this mode the control pattern are according to Table 4.
A different control is necessary to achieve a constant quality factor over the whole control range. For boost with a constant quality factor over the boost range position +5 is selected and boost control is then performed using cut. This control technique is applied to the cut range with position −5 selected and the boost is varied (Table 5).
The cut part has to follow the boost part in each filter for economic reasons. So the signal is first amplified and then attenuated. This has to be taken into account for the internal level diagram in case of constant quality factor. This may result in a mode between constant Q and non-constant Q mode; for example for the position +2 it is not necessary to amplify by step +5 and then attenuate by −3 step. The combination of step +4 and step −2 to reach position +2 is a good result (quasi constant quality factor, Table 6).
The control of the different filters is obtained by selecting the appropriate subaddress byte (Table 1).
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
Ground pins 19, 28 and 43 connected together.
SYMBOL |
PARAMETER |
MIN. |
MAX. |
UNIT |
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VP |
supply voltage (pin 14) |
0 |
13.2 |
V |
Vn |
voltage on all pins, grounds excluded |
0 |
VP |
V |
Ptot |
total power dissipation |
0 |
500 |
mW |
Tstg |
storage temperature range |
−40 |
150 |
°C |
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storage temperature range |
−40 |
150 |
°C |
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Tamb |
operating ambient temperature range |
−40 |
85 |
°C |
VESD |
electrostatic handling(1) for all pins |
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±500 |
V |
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
May 1991 |
5 |
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