Philips TEA6324T-V1 Datasheet

DATA SH EET

Preliminary specification
File under Integrated Circuits, IC01

1997 Mar 13

INTEGRATED CIRCUITS

TEA6324T

Sound control circuit

1997 Mar 13 2

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

FEATURES

• Source selector for two stereo and one mono inputs

• Interface for noise reduction circuits

• Interface for external equalizer

• Volume and balance control

• Bass control with equalizer filters

• Treble control

• Mute control at audio signal zero crossing

• Fast mute control via I2C-bus

• Fast mute control via pin

• I

2

C-bus control for all functions

• Power supply with internal power-on reset.

GENERAL DESCRIPTION

The sound control circuit TEA6324T is an I

2

C-bus
controlled stereo preamplifier for car radio hi-fi sound
applications.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 7.5 8.5 9.5 V

I

CC

supply current VCC= 8.5 V − 26 − mA

V

o(rms)

maximum output voltage level VCC= 8.5 V; THD ≤ 0.1% − 2000 − mV

G

v

voltage gain −86 − +20 dB

G

step(vol)

step resolution (volume) − 1 − dB

G

bass

bass control −18 − +18 dB

G

treble

treble control −12 − +12 dB

G

step(treble)

step resolution (treble) − 1.5 − dB

(S+N)/N signal-plus-noise to noise ratio V

o

= 2.0 V; Gv= 0 dB;

unweighted

− 105 − dB

RR

100

ripple rejection V

r(rms)

< 200 mV; f = 100 Hz;

Gv=0dB

− 75 − dB

α

cs

channel separation 250 Hz ≤ f ≤ 10 kHz; Gv=0dB 90 96 − dB

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TEA6324T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1997 Mar 13 3

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGK105

3.4 kΩ

3.4 kΩ

5.6 nF 10 nF

MUTE

C

m

100 µF

47 µF

POWER

SUPPLY

VOLUME I

LEFT

+20 to −31 dB

SOURCE

SELECTOR

input

left

source

input

right

source

input

mono

source

BASS

LEFT

±18 dB

TREBLE

LEFT

±12 dB

VOLUME I

RIGHT

+20 to −31 dB

BASS

RIGHT

±18 dB

TREBLE

RIGHT

±12 dB

MUTE

FUNCTION

ZERO CROSS

DETECTOR

VOLUME II

0 to −55 dB

BALANCE

OUTPUT LEFT

I

2

C-BUS

RECEIVER

VOLUME II

0 to −55 dB

BALANCE

OUTPUT RIGHT

LOGIC

TEA6324T

C

KVL

V

ref

220 nF

270 nF 270 nF

5.6 nF

C

KVL

C

KIN

220 nF

270 nF

17 18 20 21

495678

16

23

2

GND

V

CC

15

12

5 × 220 nF

10

14

13

11

22

1

24

3

19

270 nF

SCL

SDA

1997 Mar 13 4

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

PINNING

SYMBOL PIN DESCRIPTION

SDA 1 serial data input/output (I

2

C-bus)
GND 2 ground
OUTL 3 output left
TL 4 treble control capacitor left channel

or input from an external equalizer

B2L 5 bass control left channel or output to

an external equalizer
B1L 6 bass control, left channel
IVL 7 input volume I, left control part
QSL 8 output source selector, left channel
MUTE 9 mute control
IMO 10 input mono source
IBL 11 input B left source
IAL 12 input A left source
IAR 13 input A right source
IBR 14 input B right source
CAP 15 electronic filtering for supply
V

ref

16 reference voltage (0.5VCC)
QSR 17 output source selector right channel
IVR 18 input volume I, right control part
B1R 19 bass control right channel
B2R 20 bass control right channel or output

to an external equalizer

TR 21 treble control capacitor right channel

or input from an external equalizer
OUTR 22 output right
V

CC

23 supply voltage

SCL 24 serial clock input (I

2

C-bus)

Fig.2 Pin configuration.

handbook, halfpage

SDA

GND

OUTL

TL
B2L
B1L

IVL

QSL

MUTE

IMO

IBL
IAL

SCL
V

CC

OUTR
TR

B1R
IVR

B2R

QSR
V

ref

CAP
IBR
IAR

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17

16
15
14
13

TEA6324T

MGK104

1997 Mar 13 5

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

FUNCTIONAL DESCRIPTION

The source selector selects one of 2 stereo inputs or the
mono input. The maximum input signal voltage is
V

i(rms)

= 2 V. The outputs of the source selector and the
inputs of the following volume control parts are available at
pins 7 and 8 for the left channel and pins 17 and 18 for the
right channel. This offers the possibility of interfacing a
noise reduction system.

The volume control function is split into two sections:
volume I control block and volume II control block.

The control range of volume I is between +20 dB and

−31 dB in steps of 1 dB. The volume II control range is
between 0 dB and −55 dB in steps of 1 dB.
The recommended control range to be used is 86 dB
(+20 to −66 dB) although in theory, a range of 106 dB
(+20 to −86 dB) can be attained. The gain/attenuation
setting of the volume I control block is common for both
channels.

The volume I control block is followed by the bass control
block. The frequency response of the bass control (see
Fig.3) is provided for each channel by an external filter in
combination with internal resistors. The adjustable range
is between −18 and +18 dB in steps of 1.8 dB at 46 Hz.

The treble control block offers a control range between

−12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter
characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).

The basic step width of treble control is 3 dB.
The intermediate steps are obtained by switching 1.5 dB
boost and 1.5 dB attenuation steps.

The bass and treble control functions can be switched off
via I

2

C-bus. In this event the internal signal flow is
disconnected. The connections B2L and B2R are outputs
and TL and TR are inputs for inserting an external
equalizer.

The last section of the circuit is the volume II block.
The balance function uses the same control block. This is
achieved by 2 independently controllable attenuators, one
for each output. The control range of these attenuators is
55 dB in steps of 1 dB with an additional mute step.

The circuit provides 3 mute modes:

1. Zero crossing mode mute via I2C-bus using

2 independent zero crossing detectors (ZCM,
see Tables 2 and 8 and Fig.15)

2. Fast mute via MUTE pin (see Fig.9)

3. Fast mute via I

2

C-bus either by general mute (GMU,
see Tables 2 and 8) or volume II block setting
(see Table 4).

The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. Two comparators are built-in to
provide independent mute switches to control each of the
audio channels (left and right).

To avoid a large delay of mute switching when very low
frequencies are processed, the maximum delay time is
limited to typically 100 ms by an integrated timing circuit
and an external capacitor (Cm= 10 nF, see Fig.9). This
timing circuit is triggered by reception of a new data word
for the switch function which includes the GMU bit. After a
discharge and charge period of an external capacitor the
muting switch follows the GMU bit, only if no zero crossing
was detected during that time.

The mute function can also be controlled externally (see
Fig.9). If the mute pin is switched to ground all outputs are
muted immediately (hardware mute). This mute request
overwrites all mute controls via the I2C-bus for the time the
pin is held LOW. The hardware mute position is not stored
in the TEA6324T.

Typically, the turn on/off can be used to avoid AF output.
This can be caused by the input signal from preceding
stages, which may produce output during a drop of VCC.
To avoid this, the mute must be set prior to a VCC drop and
can be achieved either by I2C-bus control, or by grounding
the MUTE pin.

In cases where there is no mute in the application before
turn off, a supply voltage drop of more than 1 × VBE will
result in a mute during the voltage drop.

The power supply should include a VCC buffer capacitor,
which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after a certain time. A 4.7 kΩ resistor
discharges the VCC buffer capacitor, because the internal
current of the IC does not discharge it completely.

The hardware mute function is ideal for use in Radio Data
System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).

1997 Mar 13 6

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: C = 100 pF; R = 1.5 kΩ; V ≥ 2 kV. Machine model: C = 200 pF; R = 0 Ω; V ≥ 500 V.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage 0 10 V

V

n

voltage at all pins relative to pin 2 0 V

CC

V

T

amb

operating ambient temperature −40 +85 °C

T

stg

storage temperature −65 +150 °C

V

es

electrostatic handling note 1 −−

1997 Mar 13 7

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

CHARACTERISTICS

VCC= 8.5 V; RS= 600 Ω; RL=10kΩ; CL= 2.5 nF; AC coupled; f = 1 kHz; T

amb

=25°C; gain control Gv= 0 dB; bass

linear; treble linear; balance in mid position; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 7.5 8.5 9.5 V

I

CC

supply current − 26 33 mA

V

DC

internal DC voltage at inputs and
outputs

3.83 4.25 4.68 V

V

ref

internal reference voltage at pin 16 − 4.25 − V

G

v(max)

maximum voltage gain RS=0Ω; RL= ∞ 19 20 21 dB

V

o(rms)

output voltage level (RMS value) for

P

max

at the power output stage THD ≤ 0.1%; see Fig.10 − 2000 − mV

start of clipping THD = 1% 2300 −−mV

R

L

=2kΩ; CL= 10 nF;

THD = 1%

2000 −−mV

V

i(rms)

input sensitivity Vo= 2000 mV; Gv=20dB − 200 − mV

f

ro

roll-off frequency C

KIN

= 220 nF;

C

KVL

= 220 nF; Zi=Z

i(min)

low frequency (−1 dB) 60 −−Hz
low frequency (−3 dB) 30 −−Hz
high frequency (−1 dB) 20000 −−Hz

C

KIN

= 470 nF;

C

KVL

= 100 nF; Zi=Z

i(typ)

low frequency (−3 dB)

17 −−Hz

α

cs

channel separation Vi= 2 V; frequency range

250 Hz to 10 kHz

90 96 − dB

THD total harmonic distortion frequency range

20 Hz to 12.5 kHz

V

i

= 100 mV; Gv=20dB − 0.1 − %

V

i

= 1 V; Gv=0dB − 0.05 0.15 %

V

i

= 2 V; Gv=0dB − 0.1 − %

V

i

= 2 V; Gv= −10 dB − 0.1 − %

RR ripple rejection V

r(rms)

< 200 mV
f = 100 Hz 70 76 − dB
f = 40 Hz to 12.5 kHz − 66 − dB

(S+N)/N signal-plus-noise to noise ratio unweighted;

20 Hz to 20 kHz RMS;
V

o

= 2.0 V; see Figs 5 and 6

− 105 − dB

CCIR468-2 weighted; quasi
peak; V

o

= 2.0 V

G

v

=0dB − 95 − dB

G

v

=12dB − 88 − dB

G

v

=20dB − 81 − dB

1997 Mar 13 8

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

P

no(rms)

noise output power (RMS value) only
contribution of TEA6324T; power
amplifier for 6 W

mute position; note 1 −− 10 nW

α

ct

crosstalk between bus inputs and
signal outputs

note 2 − 110 − dB

Source selector

Z

i

input impedance 25 35 45 kΩ

α

S

input isolation of one selected source
to any other input

f = 1 kHz − 105 − dB
f = 12.5 kHz − 95 − dB

V

i(rms)

maximum input voltage (RMS value) THD < 0.5%; VCC= 8.5 V − 2.15 − V

THD < 0.5%; V

CC

= 7.5 V − 1.8 − V

V

offset

DC offset voltage at source selector
output by selection of any inputs

−− 10 mV

Z

o

output impedance − 80 120 Ω

R

L

output load resistance 10 −−kΩ

C

L

output load capacity 0 − 2500 pF

G

v

voltage gain, source selector − 0 − dB

Control part (source selector disconnected; source resistance 600 Ω)

Z

i

input impedance volume input 100 150 200 kΩ

Z

o

output impedance − 80 120 Ω

R

L

output load resistance 2 −−kΩ

C

L

output load capacity 0 − 10 nF

R

DCL

DC load resistance at output to ground 4.7 −−kΩ

V

i(rms)

maximum input voltage (RMS value) THD < 0.5% − 2.15 − V

V

n(o)

noise output voltage CCIR468-2 weighted; quasi

peak

G

v

=20dB − 110 220 µV

G

v

=0dB − 33 50 µV

G

v

= −66 dB − 13 22 µV

mute position − 10 −µV

CR

tot

total continuous control range − 106 − dB
recommended control range − 86 − dB

G

step

step resolution − 1 − dB
step error between any adjoining step −− 0.5 dB

∆G

a

attenuator set error Gv= +20 to −50 dB −− 2dB

G

v

=−51 to −66 dB −− 3dB

∆G

t

gain tracking error Gv= +20 to −50 dB −− 2dB

α

mute

mute attenuation see Fig.9 100 110 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

20

V

bus p p–()

V

o rms()

-------------------------- -log







1997 Mar 13 9

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

V

offset

DC step offset between any adjoining
step

Gv=0to−66 dB − 0.2 10 mV
G

v

=20to0dB − 215mV

DC step offset between any step to
mute

G

v

=0to−66 dB −− 10 mV

Volume I control

CR

tot(vol)1

continuous volume control range − 51 − dB

G

v

voltage gain −31 − +20 dB

G

step

step resolution − 1 − dB

Bass control

G

bass

bass control, maximum boost f = 46 Hz 16 18 19 dB
maximum attenuation f = 46 Hz 16 18 19 dB

G

step

step resolution (toggle switching) f = 46 Hz − 1.8 − dB
step error between any adjoining step f = 46 Hz −− 0.5 dB

V

offset

DC step offset in any bass position −− 25 mV

Treble control

G

treble

treble control, maximum boost f = 15 kHz 11 12 13 dB
maximum attenuation f = 15 kHz 11 12 13 dB
maximum boost f > 15 kHz −− 15 dB

G

step

step resolution (toggle switching) f = 15 kHz − 1.5 − dB
step error between any adjoining step f = 15 kHz −− 0.5 dB

V

offset

DC step offset in any treble position −− 10 mV

Volume II and balance control

CR

tot(vol)2

continuous attenuation of volume
control range

53.5 55 56.5 dB

G

step

step resolution − 12dB

attenuation set error −− 1.5 dB
Mute function (see Fig.9)
HARDWARE MUTE
V

sw

mute switch level (2 × VBE) − 1.45 − V

mute active

V

swLOW

input level −− 1.0 V
I

i

input current V

swLOW

=1V −300 −−µA

mute passive: level internally defined

V

swHIGH

saturation voltage −− VCCV
t

d(mute)

delay until mute passive −− 0.5 ms
ZERO CROSSING MUTE
I

dch

discharge current 0.3 0.6 1.2 µA
I

ch

charge current −300 −150 −µA
V

swDEL

delay switch level (3 × VBE) − 2.2 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Mar 13 10

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

Notes to the characteristics

1. The indicated values for output power assume a 6 W power amplifier at 4 Ω with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.

2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).

3. The AC characteristics are in accordance with the I2C-bus specification. This specification,

“The I2C-bus and how to

use it”

, can be ordered using the code 9398 393 40011.

t

d

delay time Cm=10nF − 100 − ms

V

(w)

window for audio signal zero crossing
detection

− 30 40 mV

Muting at power supply drop

V

CCdrop

supply drop for mute active − V23− 0.7 − V

Power-on reset when reset is active the GMU-bit (general mute) is set and the I

2

C-bus receiver is in reset

position

V

CC

increasing supply voltage start of reset −− 2.5 V
end of reset 5.2 6.5 7.2 V
decreasing supply voltage start of

reset

4.2 5.5 6.2 V

Digital part (I

2

C-bus pins); note 3

V

IH

HIGH-level input voltage 3 − 9.5 V

V

IL

LOW-level input voltage −0.3 − +1.5 V

I

IH

HIGH-level input current −10 − +10 µA

I

IL

LOW-level input current −10 − +10 µA

V

OL

LOW-level output voltage IL=3mA −− 0.4 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Mar 13 11

Philips Semiconductors Preliminary specification

Sound control circuit TEA6324T

I2C-BUS PROTOCOL
I

2

C-bus format

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 0101 0000.

3. A = acknowledge, generated by the slave.

4. SUBADDRESS (SAD), see Table 1.

5. DATA, see Table 1.

6. P = STOP condition.

Table 1 Second byte after MAD

Note

1. Significant subaddress.

S

(1)

SLAVE ADDRESS

(2)

A

(3)

SUBADDRESS

(4)

A

(3)

DATA

(5)

A

(3)

P

(6)

FUNCTION BIT

MSB LSB

765432

(1)

1

(1)

0

(1)

Volume V 00000000
Output right OUTR 00000001
Output left OUTL 00000010
No function − 00000011
No function − 00000100
Bass BA 00000101
Treble TR 00000110
Switch S 00000111