Philips TEA6322T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TEA6322T

Sound fader control circuit

Preliminary specification
File under Integrated Circuits, IC01

1995 Dec 19

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

FEATURES

• Source selector for three stereo and one differential
stereo input for remote sources

• The differential stereo input works optional as a fourth
stereo input and the common mode pin can be used as
well as an additional mono input

• Interface for noise reduction circuits

• Interface for external equalizer

• Volume, balance and fader control

• Output at volume I for external booster

• Special loudness characteristic automatically controlled

in combination with volume setting

• Bass and treble control

• Mute control at audio signal zero crossing

• Logic output to read mute status

2

• Fast mute control via I

C-bus

• Fast mute control via pin

• I2C-bus control for all functions

• Power supply with internal power-on reset

• Power-down indication.

GENERAL DESCRIPTION

The sound fader control circuit TEA6322T is an I

2

C-bus
controlled stereo preamplifier for car radio hi-fi sound
applications.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

o(rms)

G

v

G

step(vol)

G

bass

G

treble

G

step(treble)

(S+N)/N signal-plus-noise to noise ratio V

supply voltage 7.5 8.5 9.5 V
supply current VCC= 8.5 V − 26 − mA
maximum output voltage level VCC= 8.5 V; THD ≤ 0.1% − 2000 − mV
voltage gain −86 − +20 dB
step resolution (volume) − 1 − dB
bass control −15 − +15 dB
treble control −12 − +12 dB
step resolution (bass, treble) − 1.5 − dB

= 2.0 V; Gv= 0 dB;

O

− 105 − dB

unweighted

RR

100

ripple rejection V

r(rms)

< 200 mV;

− 75 − dB

f = 100 Hz; Gv=0dB

CMRR common mode rejection ratio

43 53 − dB

differential stereo input

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TEA6322T VSO40 plastic very small outline package; 40 leads SOT158-1

1995 Dec 19 2

1995 Dec 19 3

BLOCK DIAGRAM

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

OVL

V

GND

input

left

source

input

mono

source

input

right

source

CC

100 µF

47 µF

9 x 220 nF

C

KIN

26
38
3
4
24

20
18
16
14

17

27
25
23
21

POWER
SUPPLY

8.2 nF

220 nF

13

SOURCE

SELECTOR

220 nF

8.2 nF

C

C

20 kΩ

KVL

KVL

20 kΩ

2.2 kΩ

150 nF

1211

VOLUME I

+20 to −31 dB

LOUDNESS

LEFT

VOLUME I

+20 to −31 dB

LOUDNESS

RIGHT

150 nF

2.2 kΩ

33 nF

BASS

LEFT

± 15 dB

LOGIC

BASS

RIGHT

± 15 dB

33 nF

TREBLE

LEFT

± 12 dB

TREBLE

RIGHT

± 12 dB

5.6 nF

FUNCTION

ZERO CROSS

DETECTOR

TEA6322T

34333231293028

5.6 nF

+ 5 V

MUTE

4.7 kΩ

278910

VOLUME II
0 to −55 dB

BALANCE

FADER REAR

VOLUME II
0 to −55 dB

BALANCE

FADER FRONT

I2C-BUS

RECEIVER

VOLUME II
0 to −55 dB

BALANCE

FADER FRONT

VOLUME II
0 to −55 dB

BALANCE

FADER REAR

40

35

36

MHA084

MUTE

5

output

left

6

SCL

1

SDA

output

right

OVR

Fig.1 Block diagram.

handbook, full pagewidth

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

PINNING

SYMBOL PIN DESCRIPTION

SDA 1 serial data input/output
MUTE 2 mute control input and output
DGND 3 digital ground
AGND 4 analog ground
OUTLR 5 output left rear
OUTLF 6 output left front
TL 7 treble control capacitor left channel or input from external equalizer
B2L 8 bass control capacitor left channel or output to an external equalizer
B1L 9 bass control capacitor, left channel
OVL 10 output volume I, left channel
IVL 11 input volume I, left control part
ILL 12 input loudness, left control part
QSL 13 output source selector, left channel
IDL 14 input D left source
i.c. 15 COMM, common mode rejection adjust, centre position
ICL 16 input C left source
COM 17 common mode input / mono source input
IBL 18 input B left source
i.c. 19 COML, common mode rejection adjust, left position
IAL 20 input A differential source left
IAR 21 input A differential source right
i.c. 22 COMR, common mode rejection adjust, right position
IBR 23 input B right source
CAP 24 electronic filtering for supply
ICR 25 input C right source
V

ref

IDR 27 input D right source
QSR 28 output source selector right channel
ILR 29 input loudness right channel
IVR 30 input volume I, right control part
OVR 31 output volume I, right channel
B1R 32 bass control capacitor right channel
B2R 33 bass control capacitor right channel or output to an external equalizer
TR 34 treble control capacitor right channel or input from an external equalizer
OUTRF 35 output right front
OUTRR 36 output right rear
n.c. 37 not connected
V

CC

n.c. 39 not connected
SCL 40 serial clock input

26 reference voltage (0.5 VCC)

38 supply voltage

1995 Dec 19 4

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

The volume control function is split into two sections:

handbook, halfpage

OUTLR

OUTLF

SDA
MUTE
DGND
AGND

TL
B2L

B1L

OVL

IVL

ILL

QSL

IDL

i.c.

ICL

COM

IBL

i.c.

IAL

1
2
3
4
5
6
7
8
9

10

TEA6322T

11
12
13
14
15
16
17
18
19
20

MHA085

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

SCL
n.c.
V

CC

n.c.

OUTRR
OUTRF
TR
B2R
B1R
OVR
IVR
ILR
QSR
IDR

V

ref

ICR
CAP
IBR

i.c.
IAR

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

The source selector allows either the source selection
between the differential stereo input (IAL, IAR and COM)
and three stereo inputs, or selection of four stereo inputs
and the mono input (COM). The maximum input signal
voltage is V

= 2 V. The outputs of the source selector

i(rms)

and the inputs of the following volume control parts are
available at pins 13 and 11 for the left channel and pins 28
and 30 for the right channel. This offers the possibility of
interfacing a noise reduction system.

The volume control part is following the source selector.
The signal phase from input volume control part to all
outputs is 180°.

volume I control block and volume II control block.
The control range of volume I is between +20 dB and

−31 dB in steps of 1 dB. The volume II control range is
between 0 dB and −55 dB in steps of 1 dB. Although the
theoretical possible control range is 106 dB
(+20 to −86 dB), in practice a range of 86 dB
(+20 to −66 dB) is recommended. The gain/attenuation
setting of the volume I control block is common for both
channels.

The volume I control block operates in combination with
the loudness control. The filter is linear when the maximum
gain for the volume I control (+20 dB) is selected. The filter
characteristic increases automatically over a range of
32 dB down to a setting of −12 dB. That means the
maximum filter characteristic is obtained at −12 dB setting
of volume I. Further reduction of the volume does not
further influence the filter characteristic (see Fig.5). The
maximum selected filter characteristic is determined by
external components. The proposed application gives a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus control
(see Table 7).

The volume I control block has an output pin and is
followed by the bass control block. A single external
capacitor of 33 nF for each channel in combination with
internal resistors, provides the frequency response of the
bass control (see Fig.3). The adjustable range is between

−15 and +15 dB at 40 Hz.
Both loudness and bass control result in a maximum bass

boost of 32 dB for low volume settings.
The treble control block offers a control range between

−12 and +12 dB in steps of 1.5 dB at 15 kHz. The filter
characteristic is determined by a single capacitor of 5.6 nF
for each channel in combination with internal resistors
(see Fig.4).

The basic step width of bass and treble control is 3 dB. The
intermediate steps are obtained by switching 1.5 dB boost
and 1.5 dB attenuation steps.

The bass and treble control functions can be switched off
via I2C-bus. In this event the internal signal flow is
disconnected. The connections B2L and B2R are outputs
and TL and TR are inputs for inserting an external
equalizer.

1995 Dec 19 5

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

The last section of the circuit is the volume II block. The
balance and fader functions are performed using the same
control blocks. This is realized by 4 independently
controllable attenuators, one for each output. The control
range of these attenuators is 55 dB in steps of 1 dB with an
additional mute step.

The circuit provides 3 mute modes:

1. Zero crossing mode mute via I2C-bus using
2 independent zero crossing detectors
(ZCM, see Tables 2 and 9).

2. Fast mute via MUTE pin.

3. Fast mute via I2C-bus either by general mute (GMU,
see Tables 2 and 9) or volume II block setting
(see Table 4).

The mute function is performed immediately if ZCM is
cleared (ZCM = 0). If the bit is set (ZCM = 1) the mute is
activated after changing the GMU bit. The actual mute
switching is delayed until the next zero crossing of the
audio frequency signal. As the two audio channels (left and
right) are independent, two comparators are built-in to
control independent mute switches.

To avoid a large delay of mute switching when very low
frequencies are processed or the output signal amplitude
is lower than the DC offset voltage a second I2C-bus
transmission is needed. Both transmissions have the
same data and the second transmission a delay time of
e.g. 100 ms. The first transmission starts the zero cross
circuit, but second transmission moves the mute switch
immediately if the circuit has no zero cross detected.

The mute function can also be controlled externally. If the
mute pin is switched to ground all outputs are muted
immediately (except the outputs volume left and right (OVL
and OVR) and hardware mute). This mute request
overwrites all mute controls via the I2C-bus for the time the
pin is held LOW. The hardware mute position is not stored
in the TEA6322T.

The MUTE pin can also be used as output. The mute pin
voltage is LOW when all outputs are in mute position.

For the turn on/off behaviour the following explanation is
generally valid. To avoid AF output caused by the input
signal coming from preceding stages, which produces
output during drop of VCC, the mute has to be set, before
the VCC will drop. This can be achieved by I2C-bus control
or by grounding the MUTE pin.

For use where is no mute in the application before turn off,
a supply voltage drop of more than 1 × VBE will result in a
mute during the voltage drop.

The power supply should include a VCC buffer capacitor,
which provides a discharging time constant. If the input
signal does not disappear after turn off the input will
become audible after certain time. A 4.7 kΩ resistor
discharges the VCC buffer capacitor, because the internal
current of the IC does not discharge it completely.

The hardware mute function is favourable for use in Radio
Data System (RDS) applications. The zero crossing mute
avoids modulation plops. This feature is an advantage for
mute during changing presets and/or sources (e.g. traffic
announcement during cassette playback).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

n

supply voltage 0 10 V
voltage at pins 1, 2 and 5 to 40

0VCCV

to pins 3 and 4

T

amb

T

stg

V

es

operating ambient temperature −40 +85 °C
storage temperature −65 +150 °C
electrostatic handling note 1

Note

1. Human body model: C = 100 pF; R = 1.5 kΩ; V ≥ 2 kV. Charge device model: C = 200 pF; R = 0 Ω; V ≥ 500 V.

1995 Dec 19 6

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

CHARACTERISTICS

VCC = 8.5 V; RS= 600 Ω; RL=10kΩ; CL= 2.5 nF; AC coupled; f = 1 kHz; T
linear; treble linear; fader off; balance in mid position; loudness off; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

DC

supply voltage 7.5 8.5 9.5 V
supply current − 26 33 mA
internal DC voltage at inputs and

outputs

V

ref

G
V

o(rms)

v(max)

internal reference voltage at pin 26 − 4.25 − V
maximum voltage gain RS=0Ω; RL= ∞ 19 20 21 dB
output voltage level for

at the power output stage THD ≤ 0.5%; see Fig.10 − 2000 − mV

P

max

start of clipping THD = 1%; G

R

=2kΩ; CL= 10 nF;

L

= 3 dB 2300 −−mV

v

THD = 1%
V
f

ro

i(rms)

input sensitivity Vo= 2000 mV; Gv=20dB − 200 − mV
roll-off frequency C

= 220 nF;

KIN

C

= 220 nF; Zi=Z

KVL

low frequency (−1 dB) 60 −−Hz
low frequency (−3 dB) 30 −−Hz
high frequency (−1 dB) 20000 −−Hz

C

= 470 nF;

KIN

C

= 100 nF; Zi=Z

KVL

low frequency (−3 dB)

α

cs

channel separation Vi= 2 V; frequency range

250 Hz to 10 kHz
THD total harmonic distortion frequency range

20 Hz to 12.5 kHz

Vi= 100 mV; Gv=20dB − 0.1 − %
V

= 1 V; Gv=0dB − 0.05 0.1 %

i

V

= 2 V; Gv=0dB − 0.1 − %

i

= 2 V; Gv= −10 dB − 0.1 − %

V

i

RR ripple rejection V

r(rms)

< 200 mV
f = 100 Hz 70 76 − dB
f = 40 Hz to 12.5 kHz − 66 − dB

=25°C; gain control Gv= 0 dB; bass

amb

3.83 4.25 4.68 V

2000 −−mV

i(min)

17 −−Hz

i(typ)

74 80 − dB

1995 Dec 19 7

Philips Semiconductors Preliminary specification



Sound fader control circuit TEA6322T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(S+N)/N signal-plus-noise to noise ratio unweighted;

20 Hz to 20 kHz (RMS);
Vo= 2.0 V;
see Figs 6 and 7

CCIR468-2 weighted;
quasi peak; V

G

=0dB − 95 − dB

v

G

=12dB − 88 − dB

v

=20dB − 81 − dB

G

v

differential input

G

=0dB − 90 − dB

v

=20dB − 79 − dB

G

v

CMRR common mode rejection ratio

differential stereo input

P

no(rms)

noise output power (RMS value)

mute position; note 1 −−10 nW

only contribution of TEA6322T;
power amplifier for 6 W

α

ct

crosstalk

V



20



bus p p–()

-------------------------- -log
V

o rms()

between bus

note 2 − 110 − dB

inputs and signal outputs

= 2.0 V

o

− 105 − dB

43 53 − dB

Source selector

Z

α

V

V

i
S

i(rms)

offset

input impedance 25 35 45 kΩ
input isolation of one selected

source to any other input
maximum input voltage

(RMS value)

f=1kHz − 105 − dB
f = 12.5 kHz − 95 − dB
THD < 0.5%; VCC= 8.5 V − 2.15 − V
THD < 0.5%; V

= 7.5 V − 1.8 − V

CC

DC offset voltage at source selector
output

by selection of any stereo inputs −−10 mV
by selection of differential input or

mono input

Z

o

R

L

C

L

G

v

output impedance − 80 120 Ω
output load resistance 10 −−kΩ
output load capacity 0 − 2500 pF
voltage gain, source selector − 0 − dB

Control part (source selector disconnected; source resistance 600 Ω)

Z

i

input impedance volume input 100 150 200 kΩ
input impedance loudness input 25 33 40 kΩ

Z

o

R

L

C

L

output impedance − 80 120 Ω
output load resistance 2 −−kΩ
output load capacity 0 − 10 nF

−−20 mV

1995 Dec 19 8

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

i(rms)

V

no

CR

tot

G

step

∆G

a

∆G

t

MUTE
V

offset

maximum input voltage

THD < 0.5% − 2.15 − V

(RMS value)
noise output voltage CCIR468-2 weighted;

quasi peak

=20dB − 110 220 µV

G

v

G

=0dB − 33 50 µV

v

G

= −66 dB − 13 22 µV

v

mute position − 10 −µV
total continuous control range − 106 − dB
recommended control range − 86 − dB
step resolution − 1 − dB
step error between any adjoining

−−0.5 dB

step
attenuator set error Gv= +20 to −50 dB −−2dB

G

=−51 to −66 dB −−3dB

v

gain tracking error Gv= +20 to −50 dB −−2dB
mute attenuation see Fig.9 100 110 − dB

att

DC step offset between any
adjoining step

DC step offset between any step to
mute

Gv=0to−66 dB − 0.2 10 mV

=20to0dB − 215mV

G

v

G

=0to−66 dB −−10 mV

v

G

=20to0dB −−40 mV

v

G

=0to−31 dB;

v

−−17 mV

loudness on

Volume I control and loudness

CR
G
G
L

vol
v
step

Bmax

continuous volume control range − 51 − dB
voltage gain −31 − +20 dB
step resolution − 1 − dB
maximum loudness boost loudness on; referred to

loudness off; boost is
determined by external
components

f = 40 Hz − 17 − dB
f = 10 kHz − 4.5 − dB

Bass control

G

bass

bass control, maximum boost f = 40 Hz 14 15 16 dB
maximum attenuation f = 40 Hz 14 15 16 dB

G

step

step resolution (toggle switching) f = 40 Hz − 1.5 − dB
step error between any adjoining

f = 40 Hz −−0.5 dB

step

V

offset

DC step offset in any bass position −−20 mV

1995 Dec 19 9

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Treble control

G

treble

G

step

V

offset

Volume II, balance and fader control

CR continuous attenuation fader and

G

step

treble control, maximum boost f = 15 kHz 11 12 13 dB
maximum attenuation f = 15 kHz 11 12 13 dB
maximum boost f > 15 kHz −−15 dB
step resolution (toggle switching) f = 15 kHz − 1.5 − dB
step error between any adjoining

f = 15 kHz −−0.5 dB

step
DC step offset in any treble position −−10 mV

53.5 55 56.5 dB

volume control range
step resolution − 12dB
attenuation set error −−1.5 dB

Mute function

V

muteLOWI

input level for fast mute detection −−1.0 V
input level for no mute detection 2.2 −−V

V

muteLOWO

V

muteHIGH

V

CCdrop

Power-on reset (when reset is active the GMU-bit (general mute) is set and the I

output level for mute I ≤ 1 mA; CL≤ 100 pF −−0.4 V
pull-up voltage open collector −−VCCV
supply drop to V

for mute active −−0.7 − V

CAP

2

C-bus receiver is in

reset position)

V

CC

increasing supply voltage start of

−−2.5 V

reset
end of reset 5.2 6.5 7.2 V
decreasing supply voltage start of

4.2 5.5 6.2 V

reset

Digital part (I

V

iH

V

iL

I

iH

I

iL

V

oL

2

C-bus pins); note 3

HIGH level input voltage 3 − 9.5 V
LOW level input voltage −0.3 − +1.5 V
HIGH level input current VCC= 0 to 9.5 V −10 − +10 µA
LOW level input current −10 − +10 µA
LOW level output voltage IL=3mA −−0.4 V

Notes to the characteristics

1. The indicated values for output power assume a 6 W power amplifier at 4 Ω with 20 dB gain and a fixed attenuator
of 12 dB in front of it. Signal-to-noise ratios exclude noise contribution of the power amplifier.

2. The transmission contains: total initialization with MAD and subaddress for volume and 8 data words, see also
definition of characteristics, clock frequency = 50 kHz, repetition burst rate = 400 Hz, maximum bus signal
amplitude = 5 V (p-p).

3. The AC characteristics are in accordance with the I2C-bus specification. This specification, “

use it

”, can be ordered using the code 9398 393 40011.

The I2C-bus and how to

1995 Dec 19 10

Philips Semiconductors Preliminary specification

Sound fader control circuit TEA6322T

I2C-BUS PROTOCOL

2

C-bus format

I

(1)

S

SLAVE ADDRESS

Notes

1. S = START condition.

2. SLAVE ADDRESS (MAD) = 1000 0000.

3. A = acknowledge, generated by the slave.

4. SUBADDRESS (SAD), see Table 1.

5. DATA, see Table 1; if more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is
performed.

6. P = STOP condition.

Table 1 Second byte after MAD

(2)

(3)

A

SUBADDRESS

(4)

(3)

A

DATA

(5)

(3)

A

(6)

P

FUNCTION BIT

765432

(1)

(1)

1

(1)

0

Volume/loudness V 00000000
Fader front right FFR 00000001
Fader front left FFL 00000010
Fader rear right FRR 00000011
Fader rear left FRL 00000100
Bass BA 00000101
Treble TR 00000110
Switch S 00000111

Note

1. Significant subaddress.

MSB LSB

1995 Dec 19 11