Philips tda8790 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8790

8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

Product speciﬁcation Supersedes data of 1995 May 08 File under Integrated Circuits, IC02

1996 Feb 21

Philips Semiconductors Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

FEATURES

• 8-bit resolution

• Operation between 2.7 and 5.5 V

• Sampling rate up to 40 MHz

• DC sampling allowed

• High signal-to-noise ratio over a large analog input

frequency range (7.3 effective bits at 4.43 MHz full-scale input at f

• CMOS/TTL compatible digital inputs and outputs

• External reference voltage regulator

• Power dissipation only 30 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• Sleep mode (4 mW)

• No sample-and-hold circuit required.

QUICK REFERENCE DATA

= 40 MHz)

clk

TDA8790

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Camera

• Camcorder

• Radio communication.

GENERAL DESCRIPTION

The TDA8790 is an 8-bit universal analog-to-digital converter (ADC) for video and general purpose applications. It converts the analog input signal from

2.7 to 5.5 V into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are CMOS/TTL compatible. A sleep mode allows reduction of the device power consumption down to 4 mW.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

V

DDD

V

DDO

∆V

DD

I

DDA

I

DDD

I

DDO

analog supply voltage 2.7 3.3 5.5 V digital supply voltage 2.7 3.3 5.5 V output stages supply voltage 2.5 3.3 5.5 V supply voltage difference

V V

DDA DDD

− V

DDD DDO

−0.2 − +0.2 V

−0.2 − +2.25 V

analog supply current − 46mA digital supply current − 58mA output stages supply current f

= 40 MHz; CL= 20 pF;

clk

− 12mA

ramp input INL integral non-linearity f DNL differential non-linearity f f

clk(max)

P

tot

maximum clock frequency 40 −−MHz total power dissipation V

= 40 MHz; ramp input −±0.5 ±0.75 LSB

clk

= 40 MHz; ramp input −±0.25 ±0.5 LSB

clk

DDA=VDDD=VDDO

= 3.3 V − 30 53 mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8790M SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1996 Feb 21 2

Philips Semiconductors Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

RM

V

DDA

5

CLOCK DRIVER

10

R

LAD

I

9

8

ANALOG -TO - DIGITAL

CONVERTER

CLK

1

LATCHES

V

DDD

3

TDA8790

CMOS

OUTPUTS

2

19

D7

18

D6

17

D5 16 D4 15

D3 14

D2 13 D1 12

D0

TDA8790

SLEEP

MSB

data outputs

LSB

V

RB

7

6

V

analog ground

SSA

V

output

ground

411

SSOVSSD1

digital

ground

20

MBE502

V

DDO

Fig.1 Block diagram.

1996 Feb 21 3

Philips Semiconductors Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input SLEEP 2 sleep mode input V

DDD

V

SSD

V

DDA

V

SSA

V

RB

V

RM

V

I

V

RT

V

SSO

D0 12 data output; bit 0 (LSB) D1 13 data output; bit 1 D2 14 data output; bit 2 D3 15 data output; bit 3 D4 16 data output; bit 4 D5 17 data output; bit 5 D6 18 data output; bit 6 D7 19 data output; bit 7 (MSB) V

DDO

3 digital supply voltage (2.7 to 5.5 V) 4 digital ground 5 analog supply voltage (2.7 to 5.5 V) 6 analog ground 7 reference voltage BOTTOM input 8 reference voltage MIDDLE

9 analog input voltage 10 reference voltage TOP input 11 digital output ground

20 positive supply voltage for output

stage (2.7 to 5.5 V)

1

CLK

2

SLEEP

V

3

DDD

V

4

SSD

V

5

DDA

V

SSA V

RB

RM

V

RT

TDA8790

6 7 8

V

9

I

10

MBE501

Fig.2 Pin configuration.

TDA8790

V

20

DDO

19

D7

18

D6

17

D5

16

D4

15

D3

14

D2 D1

13

D0

12

V

11

SSO

1996 Feb 21 4

Philips Semiconductors Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD

V

DDO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

DD

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference

− V

V V V

DDA DDA DDD

− V

DDD DDO DDO

input voltage referenced to V AC input voltage for switching

referenced to V

SSA SSD

−1.0 +4.0 V

−0.3 +7.0 V

− V

DDD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature −20 +75 °C junction temperature − +150 °C

V

Note

1. The supply voltages V

DDA

, V

DDD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

DDO

voltage ∆VDD remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 120 K/W

1996 Feb 21 5

Philips Semiconductors Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal

TDA8790

analog-to-digital converter

CHARACTERISTICS

V

DDA=V5

V

i(p-p)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

V

DDA

V

DDD

V

DDO

∆V

I

DDA

I

DDD

I

DDO

Inputs

to V6= 3.3 V; V

= 1.84 V; CL= 20 pF; T

analog supply voltage 2.7 3.3 5.5 V digital supply voltage 2.7 3.3 5.5 V output stages supply voltage 2.5 3.3 5.5 V

DD

supply voltage difference

− V

V

DDA

− V

V

DDD

analog supply current − 46 mA digital supply current − 58 mA output stages supply current f

DDD=V3

DDD DDO

to V4= 3.3 V; V

=0to+70°C; typical values measured at T

amb

DDO=V20

= 40 MHz; ramp input;

clk

to V11= 3.3 V; V

CL=20pF

SSA,VSSD

=25°C; unless otherwise speciﬁed.

amb

and V

shorted together;

SSO

−0.2 − +0.2 V

−0.2 − +2.25 V

− 12 mA

LOCK INPUT CLK (REFERENCED TO V

C V

IL

V

IH

I

IL

I

IH

Z

I

C

I

INPUT SLEEP (REFERENCED TO V V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V

LOW level input current V HIGH level input current V input impedance f input capacitance f

SSD

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V

LOW level input current VIL= 0.3V

HIGH level input current VIH= 0.7V VI(ANALOG INPUT VOLTAGE REFERENCED TO V I

IL

I

IH

Z

I

C

I

LOW level input current VI=V

HIGH level input current VI=V

input impedance fi= 1 MHz − 20 − kΩ

input capacitance fi= 1 MHz − 2 − pF

); see note 1

SSD

); see Table 2

SSA

≤ 3.6 V 0.6V

V

DDD

= 0.3V

clk

= 0.7V

clk

= 40 MHz − 4 − kΩ

clk

= 40 MHz − 3 − pF

clk

≤ 3.6 V 0.6V

V

DDD

)

Reference voltages for the resistor ladder; see Table 1 V

RB

V

RT

V

diff

I

ref

reference voltage BOTTOM 1.1 1.2 − V

reference voltage TOP V

TOP

≤ V

differential reference voltage

VRT− V

RB

reference current − 0.95 − mA

RB RT

DDD

DDA

DDD DDD

V

DDD DDD DDD

− V

DDD DDD

V V

−10+1µA

−−5µA

V

DDD DDD DDD

− V

DDD DDD

V V

−1 −− µA

−−+1 µA

− 0 −µA

− 9 −µA

2.7 3.3 V

DDA

V

1.5 2.1 2.7 V

1996 Feb 21 6