Philips tda8786 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8786; TDA8786A

10-bit analog-to-digital interface for
CCD cameras

Objective specification
File under Integrated Circuits, IC02

1996 May 15

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for
CCD cameras

FEATURES

• Correlated double sampling (CDS), AGC, soft clipper,
pre- blanking, 10-bit ADC and reference regulator
included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 18 MHz

• AGC gain from 3.5 dB to 33.5 dB (in 0.1 dB steps)

• Programmable soft clipper for white compression

(starting at 40% of the input signal)

• Standby mode available for each block for power saving
applications

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 400 mW (typ.)

• 5 V operation and 2.5 to 5 V operation for the digital

outputs

• Active control pulse: TDA8786 = HIGH;
TDA8786A = LOW

• TTL compatible inputs, TTL and CMOS compatible
outputs.

TDA8786; TDA8786A

GENERAL DESCRIPTION

The TDA8786; TDA8786A is a 10-bit analog-to-digital
interface for CCD cameras. The device includes a
correlated double sampling circuit, AGC, a soft clipper
circuit and a low power 10-bit analog-to-digital converter
(ADC) together with its reference voltage regulator.

The AGC and soft clipper circuits are controlled by on-chip
DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.
A pre-blanking function is also included.
An additional DAC is provided for additional system

controls; its output voltage range is 1 V (p-p) which is
available at pin OFD.

APPLICATIONS

• CCD camera systems.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
V
V
I

CCA

I

CCD

I

CCO

CCA
CCD
CCO

analog supply voltage 4.5 4.75 5.5 V
digital supply voltage 4.5 4.75 5.5 V
digital outputs supply voltage 2.5 2.6 5.5 V
analog supply current − 67 − mA
digital supply current − 15 − mA
digital outputs supply current f

= 18 MHz; CL=20pF;

CLK

− 1 − mA

ramp input
ADC
V

iCDS(p-p)

res

ADC resolution − 10 − bits
CDS input voltage

− 400 1200 mV

(peak-to-peak value)

G

CDS

f

ss(max)

AGC
P

tot

dyn

CDS output amplifier gain − 6 − dB
maximum clock frequency 18 −−MHz
AGC dynamic range − 30 − dB
total power consumption − 400 − mW

ORDERING INFORMATION

TYPE

NUMBER

TDA8786

TDA8786A

NAME DESCRIPTION VERSION

LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

PACKAGE

1996 May 15 2

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for
CCD cameras

BLOCK DIAGRAM

handbook, full pagewidth

AGND1



AMPOUT

PBK

AGCOUT

CLPOPB

PBIN

V

CCA1

PBOUT

ADCIN

CLPADC

IN2

47

5

4
2

7

1


8

6

9
10

11

IN1 AGND3

TDA8786

TDA8786A

OPTICAL

BLACK
CLAMP

CLAMP

V

TRACK-

AND-HOLD

CLIPPER

10-BIT DAC

CCA3

CDSP2 CDSP1 CLPCDS CLK

454846

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

CLAMP

SOFT

PRE-

BLANKING

TRACK-

AND-HOLD

TRACK-

AND-HOLD

+

6 dB

AGC

9-BIT DAC

4-BIT DAC

REGULATOR

DGND2

CLOCK

GENERATOR

10-BIT ADC

SERIAL

INTERFACE

TDA8786; TDA8786A

V

V

CCD2

OUTPUTS

BUFFER

8-BIT DAC

OE

CCO

3738394041424344

36

35

34

33

32

30

29

28

27

26
25

31

3

OGND

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0
DGND1
OFDOUT

1996 May 15 3

DEC1

DEC2

19

23

STDBY

14

12

V

ref

13 15 16 17 18

AGND2

V

CCA2

V

RB

DACOUT

V

RT

SEN

22

SCLK

21

SDATA

20

V

CCD1

24

MGE361

Fig.1 Block diagram.

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

CLPOPB 1 optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A)
PBK 2 pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical

black level for TDA8786 (TDA8786A)
OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT 4 CDS amplifier output (fixed gain = +6 dB)
AGND1 5 analog ground 1
V

CCA1

AGCOUT 7 AGC and soft clipper amplifier signal output
PBIN 8 optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor)
PBOUT 9 optical black clamp and pre-blanking block signal output
ADCIN 10 ADC analog signal input (from PBOUT or AGCOUT via a capacitor)
CLPADC 11 clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active

V

ref

DACOUT 13 DAC output for ADC clamp level
AGND2 14 analog ground 2
V

CCA2

V

RB

V

RT

DEC1 18 decoupling1 (decoupled to ground via a capacitor)
DEC2 19 decoupling2 (decoupled to ground via a capacitor)
SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper;

SCLK 21 serial clock input for the control DACs and their serial interface; see Table 1
SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY 23 standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled
V

CCD1

DGND1 25 digital ground 1
D0 26 ADC digital output 0 (LSB)
D1 27 ADC digital output 1
D2 28 ADC digital output 2
D3 29 ADC digital output 3
D4 30 ADC digital output 4
D5 31 ADC digital output 5
D6 32 ADC digital output 6
D7 33 ADC digital output 7
D8 34 ADC digital output 8
D9 35 ADC digital output 9 (MSB)
OGND 36 digital output ground

6 analog supply voltage 1

LOW for TDA8786A)

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT)

15 analog supply voltage 2
16 ADC reference voltage (BOTTOM) code 0
17 ADC reference voltage (TOP) code 1023

additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby

mode per block; see Table 1)

24 digital supply voltage 1

1996 May 15 4

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

SYMBOL PIN DESCRIPTION

V

CCO

OE 38 output enable (LOW: digital outputs active; HIGH: digital outputs high impedance)
V

CCD2

DGND2 40 digital ground 2
CLK 41 ADC clock input
CLPCDS 42 CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP1 43 CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A)
CDSP2 44 CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A)
V

CCA3

IN1 46 input signal 1 from CCD (usually black channel)
IN2 47 input signal 2 from CCD (usually video channel)
AGND3 48 analog ground 3

37 digital output supply voltage

39 digital supply voltage 2

45 analog supply voltage 3

CLPOPB

PBK

OFDOUT

AMPOUT

AGNDI

V

CCAI

AGCOUT

PBIN

PBOUT

ADCIN

CLPADC

V

ref

CCA3

IN1

IN2
47

46

14

15

V

AGND2

CCA2

V

CDSP2

45

44

TDA8786

TDA8786A

16

17

RT

RB

V

V

AGND3

48

1
2
3
4
5
6
7
8
9

10
11
12

13

DACOUT

CLPCDS

CDSP1
43

42

18

19

DEC2

DEC1

CLK
41

20

DGND2
40

21

SCLK

SDATA

CCD2

V

39

22

SEN

OE

V

38

24 37

23

STDBY

V

CCO

CCD1

36
35
34
33
32
31
30
29
28
27
26
25

MGE360

OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DGND1

1996 May 15 5

Fig.2 Pin configuration.

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

V

i

V

clk(p-p)

I

o

T

stg

T

amb

T

j

CC

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
output stages supply voltage note 1 −0.3 +7.0 V
supply voltage difference

between V
between V
between V

CCA
CCA
CCD

and V
and V
and V

CCD
CCO
CCO

input voltage referenced to V
AC input voltage for switching

referenced to V

−1.0 +1.0 V

−1.0 +4.0 V

−1.0 +4.0 V

−0.3 +7.0 V

SSA

− V

SSD

CCD

(peak-to peak-value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature −20 +75 °C
junction temperature − 150 °C

V

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 76 (typ.) K/W

1996 May 15 6

Philips Semiconductors Objective specification

10-bit analog-to-digital interface for

TDA8786; TDA8786A

CCD cameras

CHARACTERISTICS

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Digital inputs

C

LOCK INPUT: CLK (REFERENCED TO DGND)

V

IL

V

IH

I

IL

I

IH

Z

I

C

I

INPUTS: CDSP1 AND CDSP2
V

IL

V

IH

I

IL

I

IH

INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC
V

IL

V

IH

I

i

Correlated double sampling; CDS

V

iCDS(p-p)

I

IN1,IN2

t

CDS(min)

ϕ CDSP1 phase with respect

= 4.75 V; V

CCO

= 2.6 V; f

= 18 Msps; T

CLK

=25°C; unless otherwise specified.

amb

analog supply voltage 4.5 4.75 5.5 V
digital supply voltage 4.5 4.75 5.5 V
supply voltage output 2.5 2.6 5.5 V
analog supply current − 67 − mA
digital supply current − 15 − mA
supply current output CL= 20 pF on all data

− 1 − mA

outputs; ramp input

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V
LOW level input current V
HIGH level input current V
input impedance f
input capacitance f

= 0.6 V −1 − +1 µA

CLK

= 2.2 V −−20 µA

CLK

=18MHz − 2 − kΩ

CLK

=18MHz − 2 − pF

CLK

CCD

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD

LOW level input current VIL= 0.6 V −−100 −µA
HIGH level input current VIH= 2.2 V − 0 −µA

LOW level input voltage 0 − 0.6 V
HIGH level input voltage 2.2 − V

CCD

input current −2 − +2 µA

CDS input amplitude

− 400 1200 mV

(peak-to-peak value)
input current pins 46 and 47 −2 − +2 µA
CDS control pulses

f

iCDS1,2=fCLK(pix)

12 −−ns
minimum active time
(HIGH for TDA8786,
LOW for TDA8786A)

− 180 − deg

to CDSP2 phase

V

V

V

1996 May 15 7