INTEGRATED CIRCUITS
DATA SHEET
TDA8784
18 Msps, 10-bit analog-to-digital interface for CCD cameras
Product specification |
1999 Sep 21 |
Supersedes data of 1998 Aug 05
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
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18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
FEATURES
∙Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included, adjustable bandwidth (CDS and AGC)
∙Fully programmable via a 3-wire serial interface
∙Sampling frequency up to 18 MHz
∙AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)
∙CDS programmable bandwidth from 4 to 120 MHz
∙AGC programmable bandwidth from 4 to 54 MHz
∙Standby mode available for each block for power saving applications (20 mW typical)
∙6 dB fixed gain analog output for analog iris control
∙8-bit and 10-bit DAC included for analog settings
∙Low power consumption of only 483 mW typical
∙5 V operation and 2.5 to 5.25 V operation for the digital outputs
∙TTL compatible inputs, TTL and CMOS compatible outputs.
APPLICATIONS
∙ CCD camera systems.
GENERAL DESCRIPTION
The TDA8784 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator.
The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface.
A 10-bit DAC controls the ADC input clamp level.
An additional 8-bit DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.
ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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TDA8784HL |
LQFP48 |
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm |
SOT313-2 |
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1999 Sep 21 |
2 |
Philips Semiconductors |
Product specification |
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18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VCCA |
analog supply voltage |
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4.75 |
5 |
5.25 |
V |
VCCD |
digital supply voltage |
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4.75 |
5 |
5.25 |
V |
VCCO |
digital outputs supply voltage |
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2.5 |
3 |
5.25 |
V |
ICCA |
analog supply current |
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− |
78 |
85 |
mA |
ICCD |
digital supply current |
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− |
18 |
20 |
mA |
ICCO |
digital outputs supply current |
fCLK = 18 MHz; |
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1 |
− |
mA |
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CL = 20 pF; ramp input |
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ADCres |
ADC resolution |
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10 |
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bits |
Vi(CDS)(p-p) |
CDS input voltage (peak-to-peak value) |
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400 |
1200 |
mV |
GCDS |
CDS output amplifier gain |
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6 |
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dB |
fCLK(max) |
maximum clock frequency |
fcut(CDS) = 120 MHz; |
18 |
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MHz |
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fcut(AGC) = 54 MHz |
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AGCdyn |
AGC dynamic range |
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30 |
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dB |
Ntot(rms) |
total output noise from CDS input to |
gain = 4.5 dB; |
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0.125 |
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LSB |
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ADC output (RMS value) |
fcut(CDS) = 120 MHz; |
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fcut(AGC) = 40 MHz |
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Ein(rms) |
equivalent input noise (RMS value) |
gain = 34.5 dB |
− |
125 |
− |
μV |
Ptot |
total power consumption |
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− |
483 |
550 |
mW |
1999 Sep 21 |
3 |
Philips Semiconductors |
Product specification |
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18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
BLOCK DIAGRAM
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IND INP AGND3 VCCA3 |
SHD |
SHP |
CLPOB |
CLPDM |
CLK |
DGND2 |
VCCD2 |
OE |
VCCO |
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47 |
46 |
48 |
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1 |
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40 |
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38 |
37 |
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36 |
OGND |
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TRACK- |
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TRACK- |
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CLOCK |
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AND-HOLD |
AND-HOLD |
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GENERATOR |
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TRACK- |
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D9 |
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AND-HOLD |
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8 |
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34 |
D8 |
CPCDS |
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CLAMP |
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AGND1 |
5 |
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33 |
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4-BIT DAC |
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D7 |
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CUT-OFF |
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CLAMP |
ref1 |
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32 |
D6 |
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31 |
D5 |
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AMPOUT |
4 |
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6 dB |
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10-BIT ADC |
OUTPUTS |
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BUFFER |
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2 |
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30 |
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AGND4 |
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D4 |
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TDA8784 |
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AGCOUT |
7 |
1 |
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AGC |
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29 |
D3 |
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28 |
D2 |
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VCCA1 |
6 |
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1 |
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4-BIT DAC |
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CUT-OFF |
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9-BIT DAC |
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27 |
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9 |
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D1 |
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AGND5 |
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ADCIN |
10 |
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26 |
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D0 |
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Vref |
12 |
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25 |
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DGND1 |
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CLPADC |
11 |
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3 |
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8-BIT DAC |
OFDOUT |
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10-BIT DAC |
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SERIAL |
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REGULATOR |
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INTERFACE |
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13 |
14 |
15 |
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16 |
17 |
18 |
19 |
23 |
22 |
21 |
20 |
24 |
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DACOUT |
VCCA2 |
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V |
RT |
AGND6 |
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SEN |
SDATA |
VCCD1 |
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MGM505 |
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AGND2 |
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VRB |
DEC1 |
STDBY |
SCLK |
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Fig.1 |
Block diagram. |
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1999 Sep 21 |
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4 |
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Philips Semiconductors |
Product specification |
|
|
18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
PINNING
SYMBOL |
PIN |
DESCRIPTION |
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CLPOB |
1 |
clamp pulse input at optical black |
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AGND4 |
2 |
analog ground 4 |
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OFDOUT |
3 |
analog output of the additional 8-bit control DAC (controlled via the serial interface) |
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AMPOUT |
4 |
CDS amplifier output (fixed gain = 6 dB) |
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AGND1 |
5 |
analog ground 1 |
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VCCA1 |
6 |
analog supply voltage 1 |
AGCOUT |
7 |
AGC amplifier signal output |
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CPCDS |
8 |
clamp storage capacitor pin |
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AGND5 |
9 |
analog ground 5 |
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ADCIN |
10 |
ADC analog signal input from AGCOUT via a short circuit |
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CLPADC |
11 |
clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground) |
Vref |
12 |
ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to |
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ground via a capacitor) |
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DACOUT |
13 |
DAC output for ADC clamp level |
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AGND2 |
14 |
analog ground 2 |
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VCCA2 |
15 |
analog supply voltage 2 |
VRB |
16 |
ADC reference voltage (BOTTOM) code 0 |
VRT |
17 |
ADC reference voltage (TOP) code 1023 |
DEC1 |
18 |
decoupling 1 (decoupled to ground via a capacitor) |
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AGND6 |
19 |
analog ground 6 |
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SDATA |
20 |
serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off; |
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additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode |
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per block and edge pulse control); see Table 1 |
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SCLK |
21 |
serial clock input for the control DACs and their serial interface; see Table 1 |
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SEN |
22 |
enable input for the serial interface shift register (active when SEN = logic 0); see Table 1 |
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STDBY |
23 |
standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled |
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VCCD1 |
24 |
digital supply voltage 1 |
DGND1 |
25 |
digital ground 1 |
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D0 |
26 |
ADC digital output 0 (LSB) |
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D1 |
27 |
ADC digital output 1 |
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D2 |
28 |
ADC digital output 2 |
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D3 |
29 |
ADC digital output 3 |
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D4 |
30 |
ADC digital output 4 |
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D5 |
31 |
ADC digital output 5 |
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D6 |
32 |
ADC digital output 6 |
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D7 |
33 |
ADC digital output 7 |
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D8 |
34 |
ADC digital output 8 |
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D9 |
35 |
ADC digital output 9 (MSB) |
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OGND |
36 |
digital output ground |
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VCCO |
37 |
digital output supply voltage |
1999 Sep 21 |
5 |
Philips Semiconductors |
Product specification |
|
|
18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
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SYMBOL |
PIN |
DESCRIPTION |
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38 |
output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance) |
OE |
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VCCD2 |
39 |
digital supply voltage 2 |
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DGND2 |
40 |
digital ground 2 |
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CLK |
41 |
ADC clock input |
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CLPDM |
42 |
clamp pulse input at dummy pixel |
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SHP |
43 |
pre-set sample-and-hold pulse input |
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SHD |
44 |
data sample-and-hold pulse input |
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VCCA3 |
45 |
analog supply voltage 3 |
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INP |
46 |
pre-set input signal from CCD |
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IND |
47 |
data input signal from CCD |
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AGND3 |
48 |
analog ground 3 |
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AGND3 |
IND |
INP |
V |
SHD |
SHP |
CLPDM |
CLK |
DGND2 |
V |
OE |
V |
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CCA3 |
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CCD2 |
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CCO |
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48 |
47 |
46 |
45 |
44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
CLPOB |
1 |
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AGND4 |
2 |
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OFDOUT |
3 |
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AMPOUT |
4 |
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AGND1 |
5 |
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VCCA1 |
6 |
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TDA8784H |
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AGCOUT |
7 |
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CPCDS |
8 |
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AGND5 |
9 |
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ADCIN |
10 |
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CLPADC |
11 |
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Vref |
12 |
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13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
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DACOUT |
AGND2 |
V |
V |
V |
DEC1 |
AGND6 |
SDATA |
SCLK |
SEN |
STDBY |
V |
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CCA2 |
RB |
RT |
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CCD1 |
36 OGND
35 D9
34 D8
33 D7
32 D6
31 D5
30 D4
29 D3
28 D2
27 D1
26 D0
25 DGND1
MGM506
Fig.2 Pin configuration.
1999 Sep 21 |
6 |
Philips Semiconductors |
Product specification |
|
|
18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VCCA |
analog supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCCD |
digital supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCCO |
output stages supply voltage |
note 1 |
−0.3 |
+7.0 |
V |
VCC |
supply voltage difference |
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between VCCA and VCCD |
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−1.0 |
+1.0 |
V |
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between VCCA and VCCO |
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−1.0 |
+4.0 |
V |
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between VCCD and VCCO |
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−1.0 |
+4.0 |
V |
Vi |
input voltage |
referenced to AGND |
−0.3 |
+7.0 |
V |
VCLK(p-p) |
AC input voltage for switching |
referenced to DGND |
− |
VCCD |
V |
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(peak-to-peak value) |
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Io |
output current |
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− |
10 |
mA |
Tstg |
storage temperature |
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−55 |
+150 |
°C |
Tamb |
ambient temperature |
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−20 |
+75 |
°C |
Tj |
junction temperature |
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150 |
°C |
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL |
PARAMETER |
CONDITIONS |
VALUE |
UNIT |
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Rth(j-a) |
thermal resistance from junction to ambient |
in free air |
76 |
K/W |
1999 Sep 21 |
7 |
Philips Semiconductors |
Product specification |
|
|
18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
CHARACTERISTICS
VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 18 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VCCA |
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analog supply voltage |
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4.75 |
5 |
5.25 |
V |
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VCCD |
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digital supply voltage |
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4.75 |
5 |
5.25 |
V |
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VCCO |
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digital outputs supply voltage |
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2.5 |
3 |
5.25 |
V |
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ICCA |
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analog supply current |
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− |
78 |
85 |
mA |
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ICCD |
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digital supply current |
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− |
18 |
20 |
mA |
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ICCO |
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digital outputs supply current |
CL = 20 pF on all data outputs; |
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1 |
− |
mA |
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ramp input |
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Digital inputs |
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CLOCK INPUT: CLK (REFERENCED TO DGND) |
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VIL |
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LOW-level input voltage |
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0 |
− |
0.8 |
V |
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VIH |
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HIGH-level input voltage |
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2.0 |
− |
VCCD |
V |
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IIL |
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LOW-level input current |
VCLK = 0.8 V |
−1 |
− |
+1 |
μA |
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IIH |
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HIGH-level input current |
VCLK = 2.0 V |
− |
− |
20 |
μA |
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Zi |
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input impedance |
fCLK = 18 MHz |
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46 |
− |
kΩ |
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Ci |
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input capacitance |
fCLK = 18 MHz |
− |
1 |
− |
pF |
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INPUTS: SHP AND SHD |
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VIL |
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LOW-level input voltage |
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0 |
− |
0.8 |
V |
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VIH |
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HIGH-level input voltage |
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2.0 |
− |
VCCD |
V |
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IIL |
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LOW-level input current |
VIL = 0.6 V |
− |
−6 |
− |
μA |
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IIH |
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HIGH-level input current |
VIH = 2.2 V |
− |
0 |
− |
μA |
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INPUTS: SEN, SCLK, SDATA, |
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STDBY, CLPDM, CLPOB AND CLPADC |
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OE, |
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VIL |
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LOW-level input voltage |
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0 |
− |
0.8 |
V |
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VIH |
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HIGH-level input voltage |
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2.0 |
− |
VCCD |
V |
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Ii |
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input current |
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−2 |
− |
+2 |
μA |
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Correlated Double Sampling (CDS) |
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Vi(CDS)(p-p) |
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CDS input amplitude |
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− |
400 |
1200 |
mV |
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(peak-to-peak value) |
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ICPCDS,INP,IND |
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input current pins 8, 46 |
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−2 |
− |
+2 |
μA |
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and 47 |
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tCDS(min) |
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CDS control pulses minimum |
fi(CDS1,2) = fCLK(pix); |
12 |
− |
− |
ns |
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active time |
Vi(CDS) = 1200 mV (p-p) |
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black-to-white transition in |
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1 pixel (±1 LSB typ.); |
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fcut(CDS) = 40 MHz; |
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fcut(AGC) = 40 MHz |
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thd1 |
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hold time INP compared to |
see Fig.5 |
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1 |
− |
ns |
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control pulse SHP |
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1999 Sep 21 |
8 |
Philips Semiconductors |
Product specification |
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18 Msps, 10-bit analog-to-digital
TDA8784
interface for CCD cameras
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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thd2 |
hold time of IND compared to |
see Fig.5 |
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1 |
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ns |
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control pulse SHD |
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tset(CDS) |
CDS settling time |
see Fig.12; control DAC 4 bits |
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input code; AGC gain = 0 dB; |
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fcut(AGC) = 54 MHz; |
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Vi(CDS) = 1200 mV (p-p) |
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black-to-white transition in 1 |
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pixel (1 LSB typ.) |
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0000 |
- |
12 |
- |
ns |
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0001 |
- |
25 |
- |
ns |
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0010 |
- |
45 |
- |
ns |
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0011 |
- |
55 |
- |
ns |
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0100 |
- |
105 |
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ns |
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0111 |
- |
140 |
- |
ns |
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1000 |
- |
270 |
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ns |
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1011 |
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300 |
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ns |
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1111 |
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365 |
- |
ns |
Amplifier outputs |
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GAMPOUT |
output amplifier gain |
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6 |
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dB |
ZAMPOUT |
output amplifier impedance |
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300 |
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W |
VAMPOUT(p-p) |
output amplifier dynamic |
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2.4 |
- |
V |
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voltage (peak-to-peak value) |
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VAMPOUT(bl) |
output amplifier black level |
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- |
1.5 |
- |
V |
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voltage |
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VAGCOUT(p-p) |
AGC output amplifier dynamic |
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- |
2000 |
- |
mV |
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voltage level (peak-to-peak |
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value) |
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VAGCOUT |
AGC output amplifier |
Vref connected to DACOUT |
- |
Vref |
- |
V |
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black level voltage |
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ZAGCOUT |
AGC output amplifier output |
at 10 kHz |
- |
5 |
- |
W |
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impedance |
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IAGCOUT |
AGC output static drive |
static |
- |
- |
1 |
mA |
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current |
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GAGC(min) |
minimum gain of AGC circuit |
AGC DAC input code = 00 |
- |
4.5 |
- |
dB |
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(9-bit control) |
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GAGC(max) |
maximum gain of AGC circuit |
AGC DAC input code ³319 |
- |
34.5 |
- |
dB |
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(9-bit control) |
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fcut(AGC) |
cut-off frequency AGC |
control DAC 4-bit |
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input code = 00 |
- |
54 |
- |
MHz |
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input code = 01 |
- |
40 |
- |
MHz |
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input code = 15 |
- |
4 |
- |
MHz |
1999 Sep 21 |
9 |