Philips TDA8783HL-C3, TDA8783HL-C2, TDA8783HL-C1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA8783

40 Msps, 10-bit analog-to-digital interface for CCD cameras

Product specification

1999 Jun 25

Supersedes data of 1998 Jul 31

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

FEATURES

∙Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included, adjustable bandwidth (CDS and AGC)

∙Fully programmable via a 3-wire serial interface

∙Sampling frequency up to 40 MHz

∙AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)

∙CDS programmable bandwidth from 4 to 120 MHz

∙AGC programmable bandwidth from 4 to 54 MHz

∙Standby mode available for each block for power saving applications 20 mW (typ.)

∙6 dB fixed gain analog output for analog iris control

∙8-bit and 10-bit DAC included for analog settings

∙Low power consumption of only 483 mW (typ.)

∙5 V operation and 2.5 to 5.25 V operation for the digital outputs

∙TTL compatible inputs, TTL and CMOS compatible outputs.

APPLICATIONS

∙ CCD camera systems.

GENERAL DESCRIPTION

The TDA8783 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator.

The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level.

An additional 8-bit DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8783HL	LQFP48	plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm	SOT313-2

1999 Jun 25

2

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VCCA	analog supply voltage		4.75	5	5.25	V
VCCD	digital supply voltage		4.75	5	5.25	V
VCCO	digital outputs supply voltage		2.5	3	5.25	V
ICCA	analog supply current		−	78	85	mA
ICCD	digital supply current		−	18	20	mA
ICCO	digital outputs supply current	fCLK = 27 MHz;	−	1	−	mA
		CL = 20 pF; ramp input
ADCres	ADC resolution		−	10	−	bits
Vi(CDS)(p-p)	CDS input voltage (peak-to-peak value)		−	400	1200	mV
GCDS	CDS output amplifier gain		−	6	−	dB
fCLK(max)	maximum clock frequency	fcut(CDS) = 120 MHz;	40	−	−	MHz
		fcut(AGC) = 54 MHz
AGCdyn	AGC dynamic range		−	30	−	dB
Ntot(rms)	total noise from CDS input to ADC output	gain = 4.5 dB;	−	0.125	−	LSB
	(RMS value)	fcut(CDS) = 120 MHz;
		fcut(AGC) = 54 MHz
Ptot	total power consumption		−	483	550	mW

1999 Jun 25

3

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

BLOCK DIAGRAM

	IND INP AGND3 VCCA3				SHD		SHP	CLPOB		CLPDM		CLK		DGND2	VCCD2	OE	VCCO
	47	46	48	45		44	43		1		42		41	40	39	38	37
																	36	OGND
			TRACK-		TRACK-								CLOCK
		AND-HOLD		AND-HOLD								GENERATOR
					TRACK-												35	D9
				AND-HOLD
	8																34	D8
CPCDS					CLAMP
AGND1	5																33
			4-BIT DAC															D7
			CUT-OFF
					CLAMP		ref1										32	D6
																	31	D5
AMPOUT	4							6 dB					10-BIT ADC		OUTPUTS
															BUFFER
	2																30
AGND4																		D4
				TDA8783
AGCOUT	7	1						AGC									29	D3
																	28	D2
			1
	6				4-BIT DAC
VCCA1
					CUT-OFF			9-BIT DAC									27
	9																	D1
AGND5
ADCIN	10																26
																		D0
	12			+													25	DGND1
Vref
	11			-
CLPADC																	3
															8-BIT DAC			OFDOUT
			10-BIT DAC				REGULATOR						SERIAL
													INTERFACE
				13	14	15		16	17	18	19	23	22	21	20	24
			DACOUT		VCCA2			V	RT	AGND6			SEN	SDATA		VCCD1		MGM491
				AGND2			VRB		DEC1		STDBY		SCLK
							Fig.1		Block diagram.
1999 Jun 25									4

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

PINNING

SYMBOL	PIN	DESCRIPTION
CLPOB	1	clamp pulse input at optical black
AGND4	2	analog ground 4
OFDOUT	3	analog output of the additional 8-bit control DAC (controlled via the serial interface)
AMPOUT	4	CDS amplifier output (fixed gain = 6 dB)
AGND1	5	analog ground 1
VCCA1	6	analog supply voltage 1
AGCOUT	7	AGC amplifier signal output
CPCDS	8	clamp storage capacitor pin
AGND5	9	analog ground 5
ADCIN	10	ADC analog signal input from AGCOUT via a short circuit
CLPADC	11	clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground)
Vref	12	ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or shorted to
		ground via a capacitor)
DACOUT	13	DAC output for ADC clamp level
AGND2	14	analog ground 2
VCCA2	15	analog supply voltage 2
VRB	16	ADC reference voltage (BOTTOM) code 0
VRT	17	ADC reference voltage (TOP) code 1023
DEC1	18	decoupling 1 (decoupled to ground via a capacitor)
AGND6	19	analog ground 6
SDATA	20	serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off,
		additional 8-bit DAC for OFD output voltage and 10-bit DAC for ADC clamp level and standby
		mode per block and edge pulse control; see Table 1
SCLK	21	serial clock input for the control DACs and their serial interface; see Table 1
SEN	22	enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
STDBY	23	standby control (active HIGH); all the output bits are logic 0 when standby is enabled
VCCD1	24	digital supply voltage 1
DGND1	25	digital ground 1
D0	26	ADC digital output 0 (LSB)
D1	27	ADC digital output 1
D2	28	ADC digital output 2
D3	29	ADC digital output 3
D4	30	ADC digital output 4
D5	31	ADC digital output 5
D6	32	ADC digital output 6
D7	33	ADC digital output 7
D8	34	ADC digital output 8
D9	35	ADC digital output 9 (MSB)
OGND	36	digital output ground
VCCO	37	digital output supply voltage

1999 Jun 25

5

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

	SYMBOL		PIN	DESCRIPTION
			38	output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance)
	OE
VCCD2			39	digital supply voltage 2
DGND2			40	digital ground 2
CLK			41	ADC clock input
CLPDM			42	clamp pulse input at dummy pixel
SHP			43	pre-set sample-and-hold pulse input
SHD			44	data sample-and-hold pulse input
VCCA3			45	analog supply voltage 3
INP			46	pre-set input signal from CCD
IND			47	data input signal from CCD
AGND3			48	analog ground 3

	AGND3	IND	INP	V	SHD	SHP	CLPDM	CLK	DGND2	V	OE	V
				CCA3						CCD2		CCO
	48	47	46	45	44	43	42	41	40	39	38	37
CLPOB	1
AGND4	2
OFDOUT	3
AMPOUT	4
AGND1	5
VCCA1	6				TDA8783H
AGCOUT	7
CPCDS	8
AGND5	9
ADCIN	10
CLPADC	11
Vref	12
	13	14	15	16	17	18	19	20	21	22	23	24
	DACOUT	AGND2	V	V	V	DEC1	AGND6	SDATA	SCLK	SEN	STDBY	V
			CCA2	RB	RT							CCD1

36 OGND

35 D9

34 D8

33 D7

32 D6

31 D5

30 D4

29 D3

28 D2

27 D1

26 D0

25 DGND1

MGM492

Fig.2 Pin configuration.

1999 Jun 25

6

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCCA	analog supply voltage	note 1	−0.3	+7.0	V
VCCD	digital supply voltage	note 1	−0.3	+7.0	V
VCCO	output stages supply voltage	note 1	−0.3	+7.0	V
VCC	supply voltage difference
	between VCCA and VCCD		−1.0	+1.0	V
	between VCCA and VCCO		−1.0	+4.0	V
	between VCCD and VCCO		−1.0	+4.0	V
Vi	input voltage	referenced to AGND	−0.3	+7.0	V
VCLK(p-p)	AC input voltage for switching	referenced to DGND	−	VCCD	V
	(peak-to-peak value)
Io	output current		−	10	mA
Tstg	storage temperature		−55	+150	°C
Tamb	operating ambient temperature		−20	+75	°C
Tj	junction temperature		−	150	°C

Note

1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	VALUE	UNIT
Rth(j-a)	thermal resistance from junction to ambient	in free air	76	K/W

1999 Jun 25

7

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

CHARACTERISTICS

VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 27 MHz; Tamb = 25 °C; unless otherwise specified.

SYMBOL		PARAMETER			CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VCCA		analog supply voltage				4.75	5	5.25	V
VCCD		digital supply voltage				4.75	5	5.25	V
VCCO		digital outputs supply voltage				2.5	3	3.6	V
ICCA		analog supply current				−	78	85	mA
ICCD		digital supply current				−	18	20	mA
ICCO		digital outputs supply current			CL = 20 pF on all data	−	1	−	mA
					outputs; ramp input
Digital inputs
CLOCK INPUT: CLK (REFERENCED TO DGND)
VIL		LOW-level input voltage				0	−	0.8	V
VIH		HIGH-level input voltage				2.0	−	VCCD	V
IIL		LOW-level input current			VCLK = 0.8 V	−1	−	+1	μA
IIH		HIGH-level input current			VCLK = 2.0 V	−	−	20	μA
Zi		input impedance			fCLK = 27 MHz	−	46	−	kΩ
Ci		input capacitance			fCLK = 27 MHz	−	1	−	pF
INPUTS: SHP AND SHD
VIL		LOW-level input voltage				0	−	0.8	V
VIH		HIGH-level input voltage				2.0	−	VCCD	V
IIL		LOW-level input current			VIL = 0.6 V	−	−6	−	μA
IIH		HIGH-level input current			VIH = 2.2 V	−	0	−	μA
INPUTS: SEN, SCLK, SDATA,				STDBY, CLPDM, CLPOB AND CLPADC
			OE,
VIL		LOW-level input voltage				0	−	0.8	V
VIH		HIGH-level input voltage				2.0	−	VCCD	V
Ii		input current				−2	−	+2	μA
Correlated Double Sampling; CDS
Vi(CDS)(p-p)		CDS input amplitude				−	400	1200	mV
		(peak-to-peak value)
ICPCDS,INP,IND		input current pins 8, 46 and 47				−2	−	+2	μA
tCDS(min)		CDS control pulses minimum			fi(CDS1,2) = fCLK(pix);	8	−	−	ns
		active time			Vi(CDS)(p-p) = 600 mV
					black-to-white transition in
					1 pixel (±1 LSB typ.);
					fcut(CDS) = 120 MHz;
					fcut(AGC) = 54 MHz
thd1		hold time INP compared to control			see Fig.5	−	1	−	ns
		pulse SHP
thd2		hold time of IND compared to			see Fig.5	−	1	−	ns
		control pulse SHD

1999 Jun 25

8

Philips Semiconductors	Product specification

40 Msps, 10-bit analog-to-digital interface

TDA8783

for CCD cameras

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
tset(CDS)	CDS setting time	control DAC 4 bits input
		code; AGC gain = 0 dB;
		fcut(AGC) = 54 MHz;
		Vi(CDS) = 600 mV (p-p)
		black-to-white transition in
		1 pixel (±1 LSB typ.)
		0000	-	8	-	ns
		0001	-	21	-	ns
		0010	-	42	-	ns
		0011	-	52	-	ns
		0100	-	82	-	ns
		0111	-	94	-	ns
		1000	-	195	-	ns
		1011	-	219	-	ns
		1111	-	280	-	ns
Amplifier outputs
GAMPOUT	output amplifier gain		-	6	-	dB
ZAMPOUT	output amplifier impedance		-	300	-	W
VAMPOUT(p-p)	output amplifier dynamic voltage		-	2.4	-	V
	(peak-to-peak value)
VAMPOUT(bl)	output amplifier black level		-	1.5	-	V
	voltage
VAGCOUT(p-p)	AGC output amplifier dynamic		-	2000	-	mV
	voltage level (peak-to-peak value)
VAGCOUT(bl)	AGC output amplifier black level	Vref connected to DACOUT	-	Vref	-	V
	voltage
ZAGCOUT(bl)	AGC output amplifier output	at 10 kHz	-	5	-	W
	impedance
IAGCOUT	AGC output static drive current	static	-	-	1	mA
GAGC(min)	minimum gain of AGC circuit	AGC DAC input code = 00	-	4.5	-	dB
		(9-bit control)
GAGC(max)	maximum gain of AGC circuit	AGC DAC input code ³ 319	-	34.5	-	dB
		(9-bit control)
fcut(AGC)	cut-off frequency AGC	4-bit control DAC
		input code = 00	-	54	-	MHz
		input code = 15	-	4	-	MHz
Clamps
gm(ADC)	ADC clamp transconductance	at clamp level	-	7	-	mS
gm(CDS)	CDS clamp transconductance	at clamp level	-	1.5	-	mS

1999 Jun 25

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