Philips tda8779h DATASHEETS

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DATA SH EET

TDA8779H

10-bit converter interface (ADC/DAC) for quadrature transceiver

Product speciﬁcation Supersedes data of 1999 Jan 18 File under Integrated Circuits, IC02

1999 Sep 16

Philips Semiconductors Product speciﬁcation

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

FEATURES

• Two 10-bit ADCs with multiplexed outputs

• Two 10-bit DACs with multiplexed inputs

• Sampling rate for the ADCs and DACs up to 20 MHz

• Digital outputs (for the ADC) and inputs (for the DAC)

are TTL/CMOS compatible

• Internal reference voltage regulator

• Power dissipation 520 mW

• Standby mode.

APPLICATIONS

• Wireless communication.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CCA1

analog supply voltage for the ADC part

CCD1

digital supply voltage for the ADC part

CCA2

analog supply voltage for the DAC part

CCD2

digital supply voltage for the DAC part

CCO

CCA

CCD

CCO

CLK(ADC)max

output stage supply voltage 2.7 3.0 3.3 V analog supply current 59 74 85 mA digital supply current 15 23 35 mA output stage supply current ramp input;

=20MHz

CLK

maximum clock frequency for the ADC part

INLA integral non linearity for the

ADC part

DNLA differential non linearity for

the ADC part

CLK(DAC)max

maximum clock frequency

full-scale; ramp input; f

=20MHz

CLK

full-scale; ramp input;

=20MHz

CLK

for the DAC part

INLD integral non linearity for the

DAC part

DNLD differential non linearity for

the DAC part

tot

total power dissipation − 520 745 mW

full-scale; ramp input;

=20MHz

CLK

full-scale; ramp input; f

=20MHz

CLK

GENERAL DESCRIPTION

The TDA8779 contains two 10-bit high speed ADCs and two 10-bit DACs for wireless communication (for use in transceiver modules). This device converts two analog input signals (channels I and Q) and digital inputs (D0 to D9) at a maximum sampling rate of 20 MHz. The input bias voltages for the analog input voltages are provided internally at the middle code. The analog input and output voltages are AC coupled.

The data sampling is performed on the rising edge of the clock for ADCs and DACs.

All reference voltages are generated internally.

4.75 5.0 5.5 V

− 7 − mA

20 −−MHz

−±2.25 ±4 LSB

− +1.55 to −0.9 +2.8 to −1.1 LSB

20 −−MHz

−±0.4 ±1.25 LSB

−±0.35 ±1.5 LSB

1999 Sep 16 2

Philips Semiconductors Product speciﬁcation

10-bit converter interface (ADC/DAC) for quadrature transceiver

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8779H QFP44 plastic quad ﬂat package; 44 leads (lead length 1.3 mm);

body 10 × 10 × 1.75 mm

BLOCK DIAGRAM

CCA1

INPUT

BIAS

DEC2 DEC3

DEC1

REFERENCE REGULATOR

10-BIT

ADC

10-BIT

ADC

LATCHES

handbook, full pagewidth

INI

INQ

PACKAGE

CCD1

DGND1

TDA8779

10 10

MUX

STDBYA

BUFFER

TDA8779H

SOT307-2

34-43

D0A to D9A

CCO

AGND1

OUTI

OUTQ

AGND2

BUFFER

CCA2

10-BIT

DAC

10-BIT

DAC

REFERENCE REGULATOR

DEC5

DEC4

LATCHES

CCD2

10 10

BUFFER

DGND2

15-24

STDBYD

CLKA CLKD

OGND

D0D to D9D

MGG075

Fig.1 Block diagram.

1999 Sep 16 3

Philips Semiconductors Product speciﬁcation

10-bit converter interface (ADC/DAC) for quadrature transceiver

PINNING

SYMBOL PIN DESCRIPTION

AGND1 1 analog ground 1 DEC1 2 decoupling input 1 DEC2 3 decoupling input 2 INI 4 I channel ADC input DEC3 5 decoupling input 3 INQ 6 Q channel ADC input V

CCA1

CCA2

OUTI 9 I channel DAC analog output DEC4 10 decoupling input 4 OUTQ 11 Q channel DAC analog output DEC5 12 decoupling input 5 AGND2 13 analog ground 2 V

CCD2

D0D 15 multiplexed input for the DACs; bit 0 D1D 16 multiplexed input for the DACs; bit 1 D2D 17 multiplexed input for the DACs; bit 2 D3D 18 multiplexed input for the DACs; bit 3 D4D 19 multiplexed input for the DACs; bit 4 D5D 20 multiplexed input for the DACs; bit 5 D6D 21 multiplexed input for the DACs; bit 6 D7D 22 multiplexed input for the DACs; bit 7 D8D 23 multiplexed input for the DACs; bit 8 D9D 24 multiplexed input for the DACs; bit 9 DGND2 25 digital ground 2 CLKD 26 transmission block clock STDBYD 27 power standby for the DAC part (active HIGH) DGND1 28 digital ground 1 STDBYA 29 power standby for the ADC part (active HIGH) CLKA 30 reception block clock V

CCD1

OE 32 ADCs digital output enable (3-state output); (active LOW) OGND 33 input/output ground D0A 34 I and Q digital outputs; bit 0 D1A 35 I and Q digital outputs; bit 1 D2A 36 I and Q digital outputs; bit 2 D3A 37 I and Q digital outputs; bit 3 D4A 38 I and Q digital outputs; bit 4 D5A 39 I and Q digital outputs; bit 5 D6A 40 I and Q digital outputs; bit 6

7 analog supply voltage 1 for ADC part (5 V) 8 analog supply voltage 2 for DAC part (5 V)

14 digital supply voltage 2 for DAC part (5 V)

31 digital supply voltage 1 for ADC part (5 V)

TDA8779H

1999 Sep 16 4

Philips Semiconductors Product speciﬁcation

10-bit converter interface (ADC/DAC) for quadrature transceiver

SYMBOL PIN DESCRIPTION

D7A 41 I and Q digital outputs; bit 7 D8A 42 I and Q digital outputs; bit 8 D9A 43 I and Q digital outputs; bit 9 V

CCO

handbook, full pagewidth

44 output supply voltage (2.7 to 3.3 V)

CCO

D8A

AGND1

DEC1 DEC2

INI

DEC3

INQ

CCA1

CCA2

OUTI

DEC4

OUTQ

D9A 43

D7A 41

TDA8779H

V 44

1 2 3 4 5 6 7 8

9 10 11

D6A 40

D5A 39

D4A 38

D3A 37

D2A 36

D1A 35

D0A 34

33 32 31 30 29 28 27 26 25 24 23

OGND OE V

CCD1

CLKA STDBYA DGND1 STDBYD CLKD DGND2 D9D D8D

TDA8779H

D0D

CCD2

D1D

DEC5

AGND2

Fig.2 Pin configuration.

D2D

D3D

D4D

D5D

D6D

D7D

MGG074

1999 Sep 16 5

Philips Semiconductors Product speciﬁcation

10-bit converter interface (ADC/DAC) for

TDA8779H

quadrature transceiver

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

CCA1

CCA2

CCD1

CCD2

CCO

∆V

clk(p-p)

stg

amb

analog supply voltage for the ADC part −0.3 +6.0 V analog supply voltage for the DAC part −0.3 +6.0 V digital supply voltage for the ADC part −0.3 +6.0 V digital supply voltage for the DAC part −0.3 +6.0 V output stage supply voltage −0.3 +6.0 V voltage difference between

V V V

CCA CCA CCD

− V

CCD CCO CCO

−1.0 +1.0 V

−1.0 +4.0 V

output current − 10 mA input voltage with respect to AGND −0.3 +6.0 V AC input switching voltage

with respect to DGND − V

CCD

(peak-to-peak value) storage temperature −55 +150 °C ambient temperature −20 +75 °C junction temperature − 150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 75 K/W

CHARACTERISTICS

CCA=V7

CCO=V44

amb

and V8 to V1and V13= 4.75 to 5.5 V; V

to V33= 2.7 to 3.3 V; AGND1, AGND2, OGND, DGND1 and DGND2 are shorted together;

= −20 to +75 °C; measured typically at V

CCD=V31

CCA=VCCD

and V14 to V28and V25= 4.75 to 5.5 V;

= 5 V and V

= 3.0 V; CL= 15 pF; T

CCO

=25°C; unless

amb

otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

CCA1

analog supply voltage for

4.75 5.0 5.5 V

the ADC part

CCD1

digital supply voltage for the

4.75 5.0 5.5 V

ADC part

CCA2

analog supply voltage for

4.75 5.0 5.5 V

the DAC part

CCD2

digital supply voltage for the

4.75 5.0 5.5 V

DAC part

CCO

output stage supply voltage 2.7 3.0 3.3 V

1999 Sep 16 6

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